CN113130664B - Novel PIN pipe microstructure - Google Patents
Novel PIN pipe microstructure Download PDFInfo
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- CN113130664B CN113130664B CN202110357101.4A CN202110357101A CN113130664B CN 113130664 B CN113130664 B CN 113130664B CN 202110357101 A CN202110357101 A CN 202110357101A CN 113130664 B CN113130664 B CN 113130664B
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- 239000000758 substrate Substances 0.000 claims description 17
- 238000000605 extraction Methods 0.000 claims description 11
- 229910052796 boron Inorganic materials 0.000 claims description 3
- -1 boron ions Chemical class 0.000 claims description 3
- 230000015556 catabolic process Effects 0.000 abstract description 9
- 230000002708 enhancing effect Effects 0.000 abstract description 2
- 238000009825 accumulation Methods 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005034 decoration Methods 0.000 description 2
- 238000003384 imaging method Methods 0.000 description 2
- 238000002955 isolation Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 241001391944 Commicarpus scandens Species 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 230000037431 insertion Effects 0.000 description 1
- 238000007689 inspection Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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Abstract
The invention discloses a novel PIN tube microstructure which is characterized by comprising a Metal1 layer, a Metal2 layer, an anode leading-out layer AC, a cathode leading-out layer CC and a PIN tube; the anode lead-out layer AC and the cathode lead-out layer CC are arranged on two electrodes of the PIN tube, the Metal1 layer is arranged above the anode lead-out layer AC and the cathode lead-out layer CC, and the Metal2 layer is arranged above the Metal1 layer; a Via hole Via 1 is arranged between the Metal1 layer and the anode lead-out layer AC or the cathode lead-out layer CC, and a Via hole Via2 is arranged between the Metal1 layer and the Metal2 layer; the invention provides a novel PIN tube microstructure which is simple and reasonable in structure and capable of enhancing breakdown voltage and overcurrent capacity of a PIN tube.
Description
Technical Field
The invention relates to the field of PIN tubes, in particular to a novel PIN tube microstructure.
Background
The millimeter wave switch and the amplitude limiter are important devices in a radio frequency front-end control circuit, mainly play roles in channel switching, signal modulation, waveform transformation, overvoltage protection and the like, and are widely applied to important fields of high-speed broadband communication, security inspection fine imaging, space detection and the like. With the further requirements of the imaging system in terms of miniaturization, high performance and the like, the core circuit and the module thereof are generally required to have the characteristics of high integration level, high isolation level, strong voltage endurance, high operating frequency and the like. The types of diodes currently used in switching and limiter circuits include mainly PHEMT transistors and PIN diodes. The PIN switch has small insertion loss, large isolation and larger bearing power. Therefore, in millimeter wave circuits and systems with certain power requirements, GaAs-based PIN diodes are generally used as components.
In the traditional PIN microstructure, the cathode and the anode are led out through a via hole connected with Metal2 (upper Metal) after being in direct ohmic contact, so that a part of an ohmic contact layer in contact with a substrate cannot be in direct contact with the Metal2, and the part is thin, high in resistivity, poor in overcurrent capacity and low in power resistance. The X-axis distance between the traditional cathode and anode ohmic contact layer is about (4-7 um), so that the substrate needs to bear certain overcurrent capacity and is easy to break down under the condition of high power. In the traditional PIN structure, the arc-shaped structure is adopted only in the part of the metal layer of the cathode and the anode, which is contacted with the substrate, so that point discharge, charge accumulation and poor voltage resistance can be caused at a square contact point.
Disclosure of Invention
The invention overcomes the defects of the prior art and provides a novel PIN tube microstructure which is simple and reasonable in structure and enhances the breakdown voltage and the overcurrent capacity of the PIN tube.
The technical scheme of the invention is as follows:
a novel PIN tube microstructure is characterized by comprising a Metal1 layer, a Metal2 layer, an anode lead-out layer AC, a cathode lead-out layer CC and a PIN tube; the anode lead-out layer AC and the cathode lead-out layer CC are arranged on two electrodes of the PIN tube, the Metal1 layer is arranged above the anode lead-out layer AC and the cathode lead-out layer CC, and the Metal2 layer is arranged above the Metal1 layer; a Via hole Via 1 is arranged between the Metal1 layer and the anode extraction layer AC or the cathode extraction layer CC, and a Via hole Via2 is arranged between the Metal1 layer and the Metal2 layer.
Further, the cathode extraction layer AC and the one near the anode extraction layer AC have a lateral closest distance of 1.5 um.
Further, the PIN tube is arranged on the substrate; the PIN tube comprises a P layer, an I layer and an N layer, wherein the P layer, the I layer and the N layer are sequentially arranged on the substrate, the area covered by the N layer is larger than that covered by the I layer, and the area covered by the I layer is larger than that covered by the P layer.
Furthermore, the whole P layer is in a strip shape, and the corners of the P layer are in a semi-arc shape; the N layers are integrally concave, and corners of the N layers are 1/4 circular arcs.
Furthermore, different devices on the substrate are isolated by adopting an IS layer, and boron ions are implanted into the IS layer at corresponding positions of the substrate.
Furthermore, the corners of the Via holes Via 1, Via holes Via2, Metal1 layer and Metal2 layer are in the shape of a semi-arc or arc.
Compared with the prior art, the invention has the advantages that:
the invention changes the microstructure of the PIN, optimizes the weak point of micro withstand voltage and overcurrent, and enhances the breakdown voltage and overcurrent capacity of the PIN tube.
The extraction of the cathode and the anode of the PIN tube is realized through the ohmic contact layer, the ohmic contact layer is connected with the Metal1 (namely the ohmic contact layer and the Metal1 are connected through the Via hole Via 1) and extracted through the Via hole Via2, and due to the introduction of the Metal1, the ohmic contact layer is completely superposed with the Metal1 and the ohmic contact layer at the microscopic level, and no ohmic contact layer in independent contact exists, so that the ohmic contact layer is prevented from bearing voltage and current independently, and the breakdown voltage and the overcurrent capacity of the PIN tube are enhanced.
The invention shortens the X-axis distance of the ohmic contact layer between the cathode and the anode to 1.5um, thus shortening the length of the substrate bearing voltage and current and enhancing the breakdown voltage and overcurrent capacity of the PIN tube.
The corner of the anode adopts a semicircular arc shape, the corner of the cathode adopts an 1/4 circular arc shape, so that the charge accumulation and the point discharge are reduced, and the breakdown voltage and the overcurrent capacity of the PIN tube are enhanced.
Drawings
FIG. 1 is a schematic view of the present invention;
FIG. 2 is a schematic diagram of a conventional PIN microstructure;
FIG. 3 is a schematic view of a partial microstructure of the PIN tube of the present invention;
FIG. 4 is a schematic view of a PIN tube of the present invention;
FIG. 5 is a schematic view of the AC/CC layer of the partial microstructure of the PIN tube of the present invention;
FIG. 6 is a schematic diagram of Metal1 of the partial microstructure of the PIN tube of the present invention;
FIG. 7 is a schematic diagram of Metal2 of the partial microstructure of the PIN tube of the present invention;
FIG. 8 is a schematic view of a partial microstructure Via 1 of a PIN tube of the invention;
FIG. 9 is a schematic view of a partial microstructure Via2 of a PIN tube of the present invention;
fig. 10 IS a schematic view of the IS of the partial microstructure of the PIN tube of the present invention.
Detailed Description
The invention is further described with reference to the following figures and detailed description.
As shown in fig. 1 to 10, a novel PIN tube microstructure is characterized by comprising a Metal1 layer, a Metal2 layer, an anode lead-out layer AC, a cathode lead-out layer CC and a PIN tube; the anode lead-out layer AC and the cathode lead-out layer CC are arranged on two electrodes of the PIN tube, the Metal1 layer is arranged above the anode lead-out layer AC and the cathode lead-out layer CC, and the Metal2 layer is arranged above the Metal1 layer; a Via hole Via 1 is arranged between the Metal1 layer and the anode extraction layer AC or the cathode extraction layer CC, and a Via hole Via2 is arranged between the Metal1 layer and the Metal2 layer. Namely, the cathode and the anode are led out through the ohmic contact layer, the ohmic contact layer is connected with Metal1 (namely, the ohmic contact layer and the Metal1 are connected through the Via Via 1), and the ohmic contact layer is led out through the Via and Metal 2. In the scheme, due to the introduction of the Metal1, the Metal1 and the ohmic contact layer are completely overlapped on a microscopic level, and the ohmic contact layer which is contacted independently does not exist, so that the ohmic contact layer is prevented from bearing voltage and current independently, and the breakdown voltage and the overcurrent capacity of the PIN tube are enhanced.
Preferably, the PIN tube is disposed on the substrate; the PIN tube comprises a P layer, an I layer and an N layer, wherein the P layer, the I layer and the N layer are sequentially arranged on the substrate, the area covered by the N layer is larger than that covered by the I layer, and the area covered by the I layer is larger than that covered by the P layer. The P layer is integrally in a strip shape, and the corner of the P layer is in a semi-arc shape; the N layers are integrally concave, and corners of the N layers are 1/4 circular arcs. Therefore, charge accumulation and point discharge are reduced, and the breakdown voltage and the overcurrent capacity of the PIN tube are enhanced.
The corners of the Via holes Via 1, Via holes Via2, Metal1 layer and Metal2 layer are in the shape of semi-circular arc or circular arc. By such a change in shape, the lateral closest distance between the cathode extraction layer AC and the both near the anode extraction layer AC can be up to 1.5 um. Therefore, the length of the substrate bearing voltage and current is shortened, and the breakdown voltage and the overcurrent capacity of the PIN tube are enhanced.
Wherein, different devices on the substrate are isolated by adopting an IS layer, and boron ions are implanted into the IS layer at corresponding positions of the substrate.
The foregoing is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and decorations can be made without departing from the spirit of the present invention, and these modifications and decorations should also be regarded as being within the scope of the present invention.
Claims (5)
1. A PIN tube microstructure is characterized by comprising a Metal1 layer, a Metal2 layer, an anode lead-out layer AC, a cathode lead-out layer CC and a PIN tube; the anode lead-out layer AC and the cathode lead-out layer CC are arranged on two electrodes of the PIN tube, the Metal1 layer is arranged above the anode lead-out layer AC and the cathode lead-out layer CC, and the Metal2 layer is arranged above the Metal1 layer; a Via hole Via 1 is arranged between the Metal1 layer and the anode lead-out layer AC or the cathode lead-out layer CC, and a Via hole Via2 is arranged between the Metal1 layer and the Metal2 layer;
the PIN tube is arranged on the substrate; the PIN tube comprises a P layer, an I layer and an N layer, wherein the P layer, the I layer and the N layer are sequentially arranged on the substrate, the area covered by the N layer is larger than that covered by the I layer, and the area covered by the I layer is larger than that covered by the P layer.
2. A PIN tube microstructure according to claim 1, wherein: the cathode extraction layer CC is at a lateral closest distance of 1.5 μm to both of them near the anode extraction layer AC.
3. A PIN tube microstructure according to claim 1, wherein: the P layer is integrally in a strip shape, and the corner of the P layer is in a semi-arc shape; the N layers are integrally concave, and corners of the N layers are 1/4 circular arcs.
4. A PIN tube microstructure according to claim 1, wherein: different devices on the substrate are isolated by adopting an IS layer, and boron ions are implanted into the IS layer at corresponding positions of the substrate.
5. A PIN tube microstructure according to claim 1, wherein: the corners of the Via holes Via 1, Via holes Via2, Metal1 layer and Metal2 layer are in the shape of semi-circular arc or circular arc.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110357101.4A CN113130664B (en) | 2021-04-01 | 2021-04-01 | Novel PIN pipe microstructure |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110357101.4A CN113130664B (en) | 2021-04-01 | 2021-04-01 | Novel PIN pipe microstructure |
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| Publication Number | Publication Date |
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| CN113130664A CN113130664A (en) | 2021-07-16 |
| CN113130664B true CN113130664B (en) | 2022-07-12 |
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| CN202110357101.4A Active CN113130664B (en) | 2021-04-01 | 2021-04-01 | Novel PIN pipe microstructure |
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Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW365026B (en) * | 1997-04-22 | 1999-07-21 | Koninkl Philips Electronics Nv | Semiconductor cathode and electron tube comprising a semiconductor cathode |
| US6303975B1 (en) * | 1999-11-09 | 2001-10-16 | International Business Machines Corporation | Low noise, high frequency solid state diode |
| JP2002305309A (en) * | 2001-02-01 | 2002-10-18 | Hitachi Ltd | Semiconductor device and its manufacturing method |
| IT1403137B1 (en) * | 2010-06-28 | 2013-10-04 | Selex Sistemi Integrati Spa | METHOD OF MANUFACTURE OF VERTICAL PIN DIODES |
| CN102386239B (en) * | 2010-08-31 | 2013-05-22 | 中国科学院上海微系统与信息技术研究所 | Indium phosphide (InP)-based PIN switching diode of planar structure and preparation method of indium phosphide-based PIN switching diode |
| US10297714B1 (en) * | 2018-04-05 | 2019-05-21 | Wisconsin Alumni Research Foundation | Heterogeneous tunneling junctions for hole injection in nitride based light-emitting devices |
| CN110544719A (en) * | 2019-09-16 | 2019-12-06 | 河北工业大学 | GaN-based PIN diode device structure and preparation method thereof |
| CN112038393B (en) * | 2020-07-01 | 2023-05-05 | 湖南三安半导体有限责任公司 | Silicon carbide power diode device and preparation method thereof |
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