CN113130485A - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device Download PDF

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Publication number
CN113130485A
CN113130485A CN202110350865.0A CN202110350865A CN113130485A CN 113130485 A CN113130485 A CN 113130485A CN 202110350865 A CN202110350865 A CN 202110350865A CN 113130485 A CN113130485 A CN 113130485A
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region
semiconductor material
substrate
regions
layer
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Inventor
李永亮
程晓红
马雪丽
杨红
王晓磊
王文武
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Institute of Microelectronics of CAS
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Institute of Microelectronics of CAS
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Priority to CN202110350865.0A priority Critical patent/CN113130485A/en
Publication of CN113130485A publication Critical patent/CN113130485A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/0886—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

The invention discloses a manufacturing method of a semiconductor device, relates to the technical field of semiconductors, and aims to reduce defects in channel regions included by transistors under the condition that the transistors formed in different threshold regulation and control regions in the semiconductor device have different threshold voltages. The manufacturing method of the semiconductor device comprises the following steps: a substrate is provided. The substrate has multiple types of regions. Grooves are respectively formed in at least part of the classification regions of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in each type of region, so that each type of region of the substrate forms a corresponding type of threshold value regulating region. And etching the substrate and the part of the semiconductor material layer, which is positioned in each type of threshold regulating region, so as to form a fin-shaped structure extending along the first direction in each type of threshold regulating region. Transistors are formed in each type of threshold adjustment region on a per fin structure basis such that transistors in different types of threshold adjustment regions have different threshold voltages.

Description

Method for manufacturing semiconductor device
Technical Field
The invention relates to the technical field of semiconductors, in particular to a manufacturing method of a semiconductor device.
Background
In order to meet practical working requirements in the manufacturing process of a semiconductor device, channels made of different materials are generally manufactured for different transistors, so that different transistors included in the semiconductor device have different threshold voltages.
However, the semiconductor device manufactured by the conventional manufacturing method has the defects in the channel of the transistor included in the semiconductor device, so that the semiconductor device has poor working performance.
Disclosure of Invention
The invention aims to provide a manufacturing method of a semiconductor device, which is used for reducing defects in a channel region included in each transistor and improving the working performance of the semiconductor device under the condition that transistors formed in different types of threshold regulating and controlling regions in the semiconductor device have different threshold voltages.
In order to achieve the above object, the present invention provides a method of manufacturing a semiconductor device, the method comprising:
providing a substrate; the substrate has a plurality of types of regions;
respectively forming grooves in at least partial classification regions of the substrate, and forming semiconductor material layers of corresponding materials in the grooves in each type of region, so that each type of region of the substrate respectively forms a corresponding type of threshold value regulation region;
etching the substrate and the part of the semiconductor material layer, which is positioned in each type of threshold value regulating and controlling area, so as to form a fin-shaped structure extending along a first direction in each type of threshold value regulating and controlling area;
transistors are formed in each type of threshold adjustment region on a per fin structure basis such that transistors in different types of threshold adjustment regions have different threshold voltages.
Compared with the prior art, the substrate provided in the manufacturing method of the semiconductor device provided by the invention has multiple types of regions. And grooves are respectively formed in at least part of the regions of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in each region, so that the threshold value regulating and controlling regions of corresponding types can be respectively formed in each region of the substrate. And etching the substrate and the part of the semiconductor material layer, which is positioned in each type of threshold regulating region, so as to form a fin-shaped structure in each type of threshold regulating region. Based on the above, the channel regions formed subsequently based on the fin structures formed in the different threshold control regions are also located in the different threshold control regions, so that transistors formed in the different threshold control regions in the manufactured semiconductor device have different threshold voltages. In addition, the semiconductor material layer is formed in grooves formed in different types of regions, and the fin-shaped structure located in each type of threshold value regulating region is formed by etching the semiconductor material layer and the part of the substrate located in the corresponding type of threshold value regulating region, so that the width of the semiconductor material layer is larger than that of the fin-shaped structure. Compared with the prior STI First scheme for forming the semiconductor material layer in the groove obtained by etching the fin-shaped structure, the semiconductor material layer is formed in the groove with larger width in the manufacturing method of the semiconductor device provided by the invention, so that the formed semiconductor material layer has good crystal quality, the quality of a channel region formed based on the semiconductor material layer can be improved, the defects of the channel region are reduced, and the working performance of the semiconductor device is improved.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and not to limit the invention. In the drawings:
fig. 1 is a flowchart of a method for manufacturing a semiconductor device according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a structure after a mask layer is formed on a substrate according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a structure after forming a groove according to an embodiment of the present invention;
FIG. 4 is a schematic view of another embodiment of the present invention after forming a groove;
FIG. 5 is a schematic structural diagram illustrating a protective material layer formed according to an embodiment of the present invention;
FIG. 6 is a schematic structural diagram illustrating a sidewall protection layer formed according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating a structure after an oxide layer is formed according to an embodiment of the present invention;
FIG. 8 is a schematic diagram illustrating another structure after an oxide layer is formed according to an embodiment of the present invention;
FIG. 9 is a schematic diagram illustrating a structure after removing an oxide layer according to an embodiment of the present invention;
FIG. 10 is a schematic diagram illustrating another example of the structure after removing the oxide layer according to the present invention;
FIG. 11 is a schematic view of a structure after an epitaxial layer is formed in an embodiment of the invention;
FIG. 12 is a schematic view of another structure after an epitaxial layer is formed in an embodiment of the invention;
FIG. 13 is a schematic diagram of a structure after forming a semiconductor material in accordance with an embodiment of the present invention;
FIG. 14 is a schematic view of another structure after forming a semiconductor material in accordance with an embodiment of the present invention;
FIG. 15 is a schematic diagram illustrating a structure of a semiconductor material after a first planarization process is performed thereon according to an embodiment of the present invention;
FIG. 16 is a schematic view of another structure after a first planarization process is performed on a semiconductor material according to an embodiment of the present invention;
FIG. 17 is a schematic structural diagram illustrating a semiconductor material layer after a first etching back process is performed on the semiconductor material layer according to an embodiment of the invention;
FIG. 18 is a schematic structural diagram illustrating the removal of the mask layer and the removal of the portion of the sidewall protection layer outside the trench in accordance with the embodiment of the present invention;
FIG. 19 is a schematic diagram illustrating another structure of the embodiment of the invention after removing the mask layer and the sidewall protection layer outside the groove;
FIG. 20 is a schematic diagram illustrating a structure of a semiconductor device after sequentially performing a first planarization process and a hard mask layer removal process on the semiconductor material according to an embodiment of the present invention;
FIG. 21 is a schematic view of another structure after forming a semiconductor material layer according to an embodiment of the present invention;
FIG. 22 is a schematic view of another structure after forming a layer of semiconductor material in accordance with an embodiment of the present invention;
FIG. 23 is a schematic diagram illustrating another structure after forming a mask layer according to an embodiment of the present invention;
FIG. 24 is a schematic view of another embodiment of the present invention after forming a groove;
FIG. 25 is a schematic view of another structure after forming a semiconductor material layer according to an embodiment of the present invention;
figure 26 illustrates a structure after forming fin structures in accordance with an embodiment of the present invention;
figure 27 is a schematic view of another embodiment of a fin structure after forming the fin structure;
FIG. 28 is a schematic structural diagram illustrating a third planarization process performed on a spacer material formed according to an embodiment of the present invention;
fig. 29 is a schematic structural diagram after shallow trench isolation is formed in the embodiment of the present invention.
Reference numerals: 11 is a substrate, 111 is a first type region, 112 is a second type region, 113 is a third type region, 12 is a mask layer, 13 is a groove, 14 is a protective material layer, 141 is a sidewall protection layer, 15 is an oxide layer, 16 is an epitaxial layer, 17 is a semiconductor material, 171 is a semiconductor material layer, 18 is a fin structure, 181 is a fin portion, 19 is an isolation material, and 191 is shallow trench isolation.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
Various structural schematics according to embodiments of the present disclosure are shown in the figures. The figures are not drawn to scale, wherein certain details are exaggerated and possibly omitted for clarity of presentation. The shapes of various regions, layers, and relative sizes and positional relationships therebetween shown in the drawings are merely exemplary, and deviations may occur in practice due to manufacturing tolerances or technical limitations, and a person skilled in the art may additionally design regions/layers having different shapes, sizes, relative positions, as actually required.
In the context of the present disclosure, when a layer/element is referred to as being "on" another layer/element, it can be directly on the other layer/element or intervening layers/elements may be present. In addition, if a layer/element is "on" another layer/element in one orientation, then that layer/element may be "under" the other layer/element when the orientation is reversed. In order to make the technical problems, technical solutions and advantageous effects to be solved by the present invention more clearly apparent, the present invention is further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
Furthermore, the terms "first", "second" and "first" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of the present invention, "a plurality" means two or more unless specifically defined otherwise. The meaning of "a number" is one or more unless specifically limited otherwise.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as meaning either a fixed connection, a removable connection, or an integral connection; can be mechanically or electrically connected; either directly or indirectly through intervening media, either internally or in any other relationship. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.
In order to meet practical requirements, in a manufacturing process of a semiconductor device, channels made of different materials are generally manufactured for different transistors (the conductivity types of the different transistors may be the same or different), so that the different transistors included in the semiconductor device have different threshold voltages.
In addition, as device feature sizes enter the 5 nm technology node, semiconductor devices suffer from degradation of channel mobility due to small-scale quantum effects. Meanwhile, the strain engineering brought by the continuous shrinkage of the size of the semiconductor device has a saturation effect, so that the performance of the semiconductor device is degraded. And high mobility materials such as silicon germanium and germanium have the characteristic of high carrier mobility. For a CMOS device, when a conductive channel in a PMOS transistor included in the CMOS device is manufactured using a silicon germanium or germanium high mobility material, carrier mobility of the conductive channel in the PMOS transistor can be improved, thereby improving performance of the PMOS transistor. However, when the high mobility material is used to fabricate the conductive channel of the NMOS transistor, there are problems of poor interface state, high source-drain contact resistance, and the like. Thus, silicon germanium or germanium high mobility materials generally serve as the conduction channel of PMOS transistors. While NMOS transistors employ strained silicon, lower germanium content silicon germanium or group iii-v materials to fabricate the conductive channel.
Whether a semiconductor device integrating a plurality of transistors having different channel materials in order to satisfy the requirement of multiple threshold voltages or a CMOS device integrating PMOS transistors and NMOS transistors having different channel materials in order to improve the operation performance, it is often necessary to form an integration of a plurality of channel materials on a substrate and then to separately manufacture channels of the respective transistors based on the plurality of channel materials.
At present, most of the existing manufacturing methods realize integration of forming a plurality of channel materials on a substrate through an STI First scheme. Taking the example of manufacturing a CMOS device having a type of NMOS transistor and a type of PMOS transistor, and the type of PMOS transistor and the type of NMOS transistor having different channel materials, the process of manufacturing the semiconductor device by the STI First scheme is briefly described: firstly, a silicon substrate or an SOI substrate can be etched by adopting photoetching and etching processes, and at least one fin-shaped structure is respectively formed on an N well region and a P well region. An isolation material for forming shallow trench isolation is then deposited between adjacent fin structures and planarized and etched back to expose tops of the fin structures. And etching the fin-shaped structure on the N well region to form a groove. And finally, forming a conductive channel of the PMOS transistor made of the high-mobility material in the groove in an extending mode, so that manufacturing of the NMOS transistor and the PMOS transistor which are made of different channel materials is achieved. As can be seen from the above, the process of manufacturing the semiconductor device using the STI first scheme is complicated. And, the high mobility material is epitaxially formed in a recess formed by etching the fin structure. In this case, the maximum width of the recess is equal to the width of the fin structure. At this time, the width of the groove is small, so that defects caused by lattice mismatch appear in the epitaxial high-mobility material along the length direction of the groove, the formation of the high-mobility material is not facilitated, and the conductive channel in the PMOS transistor has more defects, so that the performance of the semiconductor device is poor.
While the conventional STI Last scheme can achieve integration of a high mobility channel and a simple process for manufacturing a semiconductor device, the conventional STI Last scheme generally can only achieve manufacturing of a plurality of transistors having the same channel material, and it is difficult to form the semiconductor device.
In order to solve the above technical problem, embodiments of the present invention provide a method for manufacturing a semiconductor device. Wherein the substrate is provided having a plurality of types of regions. And grooves are formed in at least part of the regions of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in each region, so that the threshold value regulating and controlling regions of corresponding types can be formed in each region of the substrate. And then, fin-shaped structures are formed in each type of threshold value regulating region on the etched substrate and the part of the semiconductor material layer, which is positioned in each type of threshold value regulating region. Based on the above, the channel regions formed subsequently based on the fin structures formed in the different threshold control regions are also located in the different threshold control regions, so that transistors formed in the different threshold control regions in the manufactured semiconductor device have different threshold voltages. In addition, the semiconductor material layer is formed in the groove with a larger width, so that the formed semiconductor material layer has good crystal quality, the quality of a channel region formed on the basis of the semiconductor material layer can be improved, the defects of the channel region are reduced, and the working performance of a semiconductor device is improved.
As shown in fig. 1, an embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing process will be described below based on the cross-sectional views of the operations shown in fig. 2 to 29. Specifically, the manufacturing method of the semiconductor device comprises the following steps:
first, a substrate is provided. The substrate has a plurality of types of regions.
Specifically, the substrate may be a semiconductor substrate such as a silicon substrate or a silicon-on-insulator substrate. In addition, the number of the regions of the substrate may be set according to the actual application scenario, and is not limited specifically here. In one example, the semiconductor device being fabricated is a semiconductor device having at least two PMOS (or NMOS) transistors. And when the at least two PMOS (or NMOS) transistors have two threshold voltages of different sizes, the conductivity types of the plurality of transistors included in the semiconductor device are the same. In this case, the number of types of regions in the substrate is equal to the number of threshold voltages having different sizes, that is, the substrate has two types of regions (a first type region and a second type region). The number of the two types of regions provided in the substrate may be one or more.
In another example, in the case where the manufactured semiconductor device is a semiconductor device including at least three transistors having different threshold voltages and the conductivity types of the transistors are different, the number of types of regions that the substrate has may be set according to the threshold voltage of the transistor and the actual application scenario. For example: when the semiconductor device includes one PMOS transistor having an AV threshold voltage, three PMOS transistors having a BV threshold voltage, and five NMOS transistors having a CV threshold voltage, and a ≠ B ≠ C, the above-mentioned substrate has three types of regions. In addition, the number of each type of region may be set according to the number of transistors having a corresponding threshold voltage. For example: when the semiconductor device includes one PMOS transistor having an AV threshold voltage, three PMOS transistors having a BV threshold voltage, and five NMOS transistors having a CV threshold voltage, and a ≠ B ≠ C, the substrate may have one first-type region, three second-type regions, and five third-type regions.
As shown in fig. 2 to 25, at least the substrate 11 has partial regions, each having a recess 13, and a semiconductor material layer 171 of a corresponding material is formed in the recess 13 of each region, so that each region of the substrate 11 has a threshold adjusting region of a corresponding type.
The material of the semiconductor material layer may be silicon germanium, germanium tin or III-V material. The specific material of the semiconductor material layer formed in each type of region may be set according to the conductivity type of the corresponding transistor to be formed later and the requirement of the threshold voltage thereof, and is not limited specifically herein.
In addition, the number of the regions to be provided with the grooves can be set according to the conductivity types of transistors subsequently formed in different threshold control regions and the threshold voltages of different transistors. Specifically, the formation of the threshold control region can be classified into at least the following two types:
in one example, the substrate has an N-type region. Wherein N is a positive integer greater than or equal to 2. In addition, in the case that the conductivity types of the transistors located in the different types of threshold control regions are the same, the forming of the grooves in at least some of the types of regions of the substrate, and the forming of the semiconductor material layer of the corresponding material in the groove located in each type of region may include: at least N-1 type regions of the substrate are respectively provided with grooves, and semiconductor material layers made of corresponding materials are formed in the grooves in each type of regions. The material of the semiconductor material layer in the grooves of different types of areas is different. The specific value of N may be set according to an actual application scenario, and is not specifically limited herein.
It can be understood that when the transistors in the different threshold regions have the same conductivity type, the transistors in the different threshold regions need to have channel regions made of different materials, so as to realize the different threshold voltages of the transistors in the different threshold regions. Therefore, when the substrate is provided with N types of regions, and under the condition that the conduction types of the transistors in different types of threshold value regulation and control regions are the same, grooves are required to be formed in at least N-1 types of regions of the substrate respectively, and semiconductor material layers made of corresponding materials are formed in the grooves, so that after the substrate and the semiconductor material layers are etched in the various types of threshold value regulation and control regions, the materials of fin-shaped structures in the different types of threshold value regulation and control regions are not completely the same, and the transistors with different threshold voltage are formed in the different types of threshold value regulation and control regions.
In another example, the substrate has an M-class first region, and a P-class second region. The threshold modulation region corresponding to the first region is a first threshold modulation region. The threshold modulation region corresponding to the second region is a second threshold modulation region. The conductivity type of the transistor located in the first threshold adjustment region is different from the conductivity type of the transistor located in the second threshold adjustment region.
When M is 1 and P is a positive integer larger than or equal to 2, grooves are respectively formed in at least partial regions of the substrate, and semiconductor material layers of corresponding materials are formed in the grooves in each region, and the method comprises the following steps: at least the P-1 type second region of the substrate is provided with a groove, and at least the groove in each type of second region is provided with a semiconductor material layer made of corresponding material.
When M is a positive integer greater than or equal to 2 and P is 1, grooves are respectively formed in at least partial regions of the substrate, and semiconductor material layers of corresponding materials are formed in the grooves in each region, the method includes: grooves are formed in at least the M-1 type first regions of the substrate, and semiconductor material layers of corresponding materials are formed in at least the grooves in each type of first regions.
Under the condition that M and P are positive integers which are more than or equal to 2, grooves are respectively formed in at least partial classification regions of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in each classification region, the method comprises the following steps: at least the substrate is provided with M-1 type first areas and P-1 type second areas, grooves are formed in the M-1 type first areas and the P-1 type second areas, and semiconductor material layers made of corresponding materials are formed in the grooves in the M-1 type first areas and the P-1 type second areas.
It is understood that when the conductivity type of the transistor in the first threshold adjustment region is different from the conductivity type of the transistor in the second threshold adjustment region, the transistor in the first threshold adjustment region of each type is required to have a channel region made of a different material. Furthermore, the transistors in the various second threshold control regions are required to have channel regions made of different materials, so as to ensure that the transistors with different threshold voltages are formed in the different threshold control regions. The transistor in the first threshold control region and the transistor in the second threshold control region may have the same or different channel regions. Based on this, when M is 1 and P is a positive integer greater than or equal to 2, a recess is formed in at least the P-1 type second region of the substrate, and a semiconductor material layer of a corresponding material is formed therein (the material of the semiconductor material layer formed in the recess at least in the different type second region is different).
When M is a positive integer greater than or equal to 2 and P is 1, it is necessary to form a recess in at least the M-1 type first region of the substrate and form a semiconductor material layer of a corresponding material therein (the material of the semiconductor material layer formed in the recesses at least in the different types of first regions is different).
In the case where M and P are positive integers greater than or equal to 2, it is necessary to form grooves in at least the M-1 type first region and the P-1 type second region of the substrate, and form semiconductor material layers of corresponding materials therein (the material of the semiconductor material layers formed in the grooves in the different types of first regions and the different types of second regions may be the same or different).
When M and P are both equal to 1, a recess may be formed in the first region of the substrate, and a semiconductor material layer of a corresponding material may be formed in the recess in the first region. Alternatively, a groove may be formed in the second region of the substrate, and a semiconductor material layer of a corresponding material may be formed in the groove in the second region. Furthermore, grooves may be formed in the first region and the second region, respectively, and semiconductor material layers of corresponding materials may be formed in the grooves of the first region and the second region. Of course, if the substrate is directly etched, the transistors in the first region and the second region may have threshold voltages meeting the operation requirements, or no recess may be formed in the first region and the second region.
It should be noted that, no matter the conductivity types of the transistors in the different threshold control regions are the same or different, semiconductor material layers of corresponding materials are formed in the grooves in the different threshold control regions according to the conductivity types of the transistors as long as the threshold voltages of the different transistors meet the operating requirements. For example: under the condition that the transistor positioned in the first threshold regulation and control area is an NMOS transistor and the transistor positioned in the second threshold regulation and control area is a PMOS transistor, the material of the semiconductor material layer formed in the groove of the first area is strained silicon, germanium silicon with lower germanium content or III-V group material. The material of the semiconductor material layer formed in the groove of the second region is high-mobility material such as silicon germanium, germanium and the like. At this time, in addition to enabling the transistors located in the first region and the second region to have threshold voltages meeting the operation requirements, the mobility of carriers in the transistors located in the second threshold control region can be improved, and the operation performance of the manufactured semiconductor device is improved.
In an example, as shown in fig. 2 to 25, the step of forming the grooves 13 in at least some of the classification regions of the substrate 11 and forming the semiconductor material layer 171 of the corresponding material in the grooves 13 in each classification region may include the steps of:
as shown in fig. 2 and 23, a mask layer 12 is formed on a substrate 11 to expose a target class region that the substrate 11 has. The target type region may be any one of the plurality of types of regions of the substrate 11, in which the groove 13 is to be etched. For example: in the case where the manufactured semiconductor device is a CMOS device having one PMOS transistor and one NMOS transistor of different channel materials and threshold voltages, and the substrate 11 is a silicon substrate, if the substrate 11 has the first-type region 111 being a P-well region and the second-type region 112 being an N-well region, the target-type region may be the second-type region 112.
For example, a layer of masking material may be formed overlying the surface of the substrate by a chemical vapor deposition process or a physical vapor deposition process. The layer of masking material may then be etched using photolithography and etching processes to form the masking layer described above. The mask layer may be a single layer or a plurality of layers. Specifically, the structure of the mask layer may be set according to an actual application scenario, and is not specifically limited herein. For example: when the mask layer has a single-layer structure, the mask layer may be a silicon dioxide layer, a silicon nitride layer, a silicon carbide layer, or the like. Another example is: when the mask layer has a multilayer structure, the mask layer may have a multilayer structure of a silicon oxide layer/a silicon nitride layer, or may have a multilayer structure of a silicon oxide layer/a silicon nitride layer/a silicon oxide layer.
As shown in fig. 3, 4 and 24, a portion of the substrate 11 located in the target area is etched under the mask action of the mask layer 12 to form a groove 13 in the target area.
For example, a photolithography and an etching process may be used to etch a portion of the substrate located in the target region under the mask effect of the mask layer, so as to obtain the groove. The width of the groove may be equal to or slightly less than the width of the target class region. The depth of the recess may be set according to the height of the channel region of the transistor to be formed.
In an example, after the forming the groove in the target region, and before forming the semiconductor material layer of the corresponding material in the groove in the target region, the method for manufacturing the semiconductor device may further include: as shown in fig. 5 and 6, a sidewall protection layer 141 is formed to cover the sidewalls of the groove 13.
It will be appreciated that after the recess is formed, both the side walls and the base of the recess are exposed to the ambient environment. Based on this, as shown in fig. 6, before forming the semiconductor material layer, a sidewall protection layer 141 is formed on the sidewall of the groove 13, and the existence of the sidewall protection layer 141 can enable the semiconductor material for forming the semiconductor material layer to grow only from the bottom of the groove 13 and along a single direction from bottom to top, and limit the growth direction of the semiconductor material, thereby further reducing the defects formed in the semiconductor material layer and improving the yield of the manufactured semiconductor device.
Illustratively, as shown in fig. 5, a layer of protective material 14 may be formed overlying masking layer 12, and the sidewalls and bottom of recess 13, using chemical vapor deposition or physical vapor deposition. Next, as shown in fig. 6, a portion of the protective material layer on the mask layer 12 and the groove bottom of the groove 13 may be removed by a dry etching process or the like, so as to obtain a sidewall protection layer 141. The thickness and material of the sidewall protection layer 141 may be set according to practical application scenarios, and are not limited herein. For example: the sidewall protection layer 141 may be made of silicon dioxide, silicon nitride, silicon carbide, or the like.
In an example, after forming the groove in the target region, before forming the semiconductor material layer of the corresponding material in the groove located in the target region, the method for manufacturing the semiconductor device may further include: as shown in fig. 7 and 8, the groove 13 is oxidized to form an oxide layer 15 at least on the groove bottom of the groove 13. As shown in fig. 9 and 10, the oxide layer is removed.
It can be understood that after the etching process is used to etch the portion of the substrate located in the target region to form the groove, there is etching damage to the sidewall and the bottom of the groove. Based on the method, before the semiconductor material layer made of the corresponding material is formed in the groove, the etching damage existing on the side wall and the bottom of the groove can be repaired in a sacrificial oxidation mode, the epitaxial interface is improved, and the quality of the subsequently formed semiconductor material layer is improved.
Illustratively, the groove may be oxidized by a rapid thermal annealing treatment in an atmosphere of oxygen, ozone, or a mixture of oxygen and ozone to form an oxide layer on the sidewall and bottom of the groove. Wherein, the processing temperature of the rapid thermal annealing treatment can be 700-1050 ℃. The treatment time may be 1s to 1 min. The oxide layer may then be removed by a dilute hydrofluoric acid clean or an epitaxial in situ clean.
It should be noted that, if a sidewall protection layer is formed on the sidewall of the groove after the groove is formed in the target region, the etching damage existing at the bottom of the groove needs to be repaired by the sacrificial oxidation method after the sidewall protection layer is formed and before the semiconductor material layer of the corresponding material is formed in the groove located in the target region, so as to improve the interface for performing epitaxy.
In another embodiment, in addition to the above-mentioned sacrificial oxidation, the interface for epitaxy may be improved by forming an epitaxial layer. Specifically, after the groove is formed in the target region, before the semiconductor material layer of the corresponding material is formed in the groove located in the target region, the method for manufacturing the semiconductor device may further include: as shown in fig. 11 and 12, an epitaxial layer 16 is formed to cover at least the groove bottom of the groove 13.
Illustratively, an epitaxial growth process may be used to form an epitaxial layer overlying the sidewalls and bottom of the recess to improve the interface at which the epitaxy occurs. Specifically, the thickness and the material of the epitaxial layer may be set according to a practical application scenario, and are not specifically limited herein. For example: in the case where the substrate is a silicon-based substrate, the epitaxial layer may be made of silicon.
If the sidewall protection layer is formed on the sidewall of the groove after the groove is formed in the target region, the epitaxial layer covering the bottom of the groove needs to be formed in the above-mentioned manner to form the epitaxial layer after the sidewall protection layer is formed and before the semiconductor material layer of the corresponding material is formed in the groove located in the target region, so as to improve the interface for performing the epitaxial process.
In another embodiment, after the groove is formed in the target region (in the case of forming the sidewall protection layer, it is necessary to form the sidewall protection layer), before the semiconductor material layer of the corresponding material is formed in the groove located in the target region, at least the etching damage existing at the bottom of the groove may be repaired by using the above-mentioned sacrificial oxidation method. Then, an epitaxial layer is formed to cover at least the groove bottom of the groove, so as to further improve the epitaxial interface. Specifically, as shown in fig. 7 and 8, the groove 13 may be oxidized in the above-described manner to form the oxide layer 15 at least on the groove bottom of the groove 13. Next, the oxide layer is removed as shown in fig. 9 and 10. Finally, as shown in fig. 11 and 12, an epitaxial layer 16 is formed so as to cover at least the groove bottom of the groove 13.
As shown in fig. 13 to 22, a semiconductor material layer 171 of a corresponding material is formed in the recess located in the target region. Specifically, the semiconductor material layer 171 may be formed in at least the following three ways according to the removal order of the mask layer 12 formed on the substrate 11 and whether the mask layer 12 and the sidewall protection layer 141 are made of the same material:
in an example, in a case where the mask layer is removed after the semiconductor material layer of the corresponding material is formed in the groove, the forming of the semiconductor material layer of the corresponding material in the groove located in the target region may include the following steps:
as shown in fig. 13 and 14, a semiconductor material 17 of a corresponding material is epitaxially formed in the recess 13 of the target region. The top height of semiconductor material 17 is greater than the top height of mask layer 12.
Specifically, as shown in fig. 13, before forming the semiconductor material 17 in the recess 13, if an epitaxial layer is not formed in the recess 13, the semiconductor material 17 of a corresponding material needs to be epitaxially formed on the surface of the recess 13 exposed to the external environment. As shown in fig. 14, in the case where the epitaxial layer 16 is formed in the recess 13 before the semiconductor material 17 is formed in the recess 13, the semiconductor material 17 of a corresponding material needs to be epitaxially grown on the surface of the epitaxial layer 16 exposed to the external environment. In the case of forming the sidewall protection layer 141, the surface of the groove 13 exposed to the external environment is the surface of the groove bottom. The surface of the epitaxial layer 16 exposed to the external environment is the upper surface of the epitaxial layer 16 parallel to the substrate 11.
The material of the semiconductor material may be set with reference to the material of the semiconductor material layer described above. For example: in the case where the manufactured semiconductor device is a CMOS device having one PMOS transistor and one NMOS transistor with different channel materials and threshold voltages, if the target region is an N-well region, the material of the epitaxial semiconductor material may be high mobility material such as silicon germanium or germanium.
As shown in fig. 15 to 17, the semiconductor material 17 is sequentially subjected to a first planarization process and a first etching back process, so that the remaining semiconductor material 17 forms a semiconductor material layer 171. The top of the layer 171 of semiconductor material is flush with the surface of the substrate 11.
Specifically, since the top height of the formed semiconductor material is greater than the top height of the mask layer, the semiconductor material needs to be thinned in order to obtain the semiconductor material layer only in the groove. The first planarization treatment may be performed on the semiconductor material by using a chemical mechanical polishing process or the like. In addition, the etchant used for performing the first etching back process on the semiconductor material after the first planarization process may be set according to the material of the semiconductor material, and is not particularly limited herein.
As shown in fig. 18, the mask layer 12 is removed, and the portion of the sidewall protection layer 141 outside the recess 13 is removed.
Specifically, under the condition that the mask layer and the side wall protection layer are made of the same material, the mask layer can be removed, and meanwhile, the side wall protection layer is removed from the portion, located outside the groove, of the side wall protection layer. Under the condition that the materials of the two are different, the mask layer and the part of the side wall protection layer outside the groove can be removed in sequence by adopting corresponding etching agents.
In another example, in a case where the mask layer is removed before the semiconductor material layer of the corresponding material is formed in the groove, and the material of the mask layer is the same as that of the sidewall protection layer, the forming of the semiconductor material layer of the corresponding material in the groove in the target region may include:
as shown in fig. 13 and 14, a semiconductor material 17 of a corresponding material is epitaxially formed in the recess of the target region. The top height of semiconductor material 17 is greater than the top height of mask layer 12. Specifically, the formation, material, etc. of the semiconductor material 17 can be referred to the above, and will not be described herein again.
As shown in fig. 15 and 16, a first planarization process is performed on semiconductor material 17 so that the top of remaining semiconductor material 17 is flush with the top of mask layer 12. Illustratively, the semiconductor material 17 is subjected to a first planarization process using a chemical mechanical polishing process or the like.
As shown in fig. 19, the mask layer 12 is removed, and the portion of the sidewall protection layer 141 outside the groove is removed. Illustratively, since the mask layer 12 and the sidewall protection layer 141 are made of the same material, the same etchant may be used to simultaneously remove the mask layer 12 and the portion of the sidewall protection layer 141 outside the groove, thereby improving the manufacturing efficiency of the semiconductor device.
As shown in fig. 21, the remaining semiconductor material 17 is subjected to a second planarization process, and a layer of the semiconductor material 17 is obtained.
It will be appreciated that after the first planarization treatment, the top of the remaining semiconductor material is higher than the substrate surface, i.e. higher than the groove opening in the target type region, so that in order to obtain a semiconductor material layer only in the groove, a second planarization treatment is also required for the remaining semiconductor material. Wherein, the remaining semiconductor material may be subjected to a second planarization process by a process such as chemical mechanical polishing.
In another example, in a case where the mask layer is removed before the semiconductor material layer of the corresponding material is formed in the groove and the material of the mask layer is different from the material of the sidewall protection layer, the forming of the semiconductor material layer of the corresponding material in the groove located in the target region includes:
as shown in fig. 13 and 14, a semiconductor material 17 of a corresponding material is epitaxially formed in the recess of the target region. The top height of semiconductor material 17 is greater than the top height of mask layer 12. Specifically, the formation, material, etc. of the semiconductor material 17 can be referred to the above, and will not be described herein again.
As shown in fig. 15 and 16, a first planarization process is performed on semiconductor material 17 so that the top of remaining semiconductor material 17 is flush with the top of mask layer 12. Specifically, reference may be made to the foregoing for specific operations of performing the first planarization process on the semiconductor material 17, and details are not repeated here.
As shown in fig. 20, masking layer 12 is removed. Specifically, the etchant for removing the mask layer 12 may be set according to the material of the mask layer 12. For example: when the material of the mask layer 12 is silicon dioxide, diluted hydrofluoric acid may be used to remove the mask layer 12.
As shown in fig. 21, the sidewall protection layer 141 and the remaining semiconductor material are subjected to the second planarization process so that the tops of the remaining sidewall protection layer 141 and the remaining semiconductor material are both flush with the surface of the substrate 11. The remaining semiconductor material forms a layer 171 of semiconductor material. Specifically, the second planarization treatment may be performed on the sidewall protection layer 141 and the remaining semiconductor material by a chemical mechanical polishing process or the like.
As shown in fig. 22 to 25, the above steps are repeated until the grooves 13 are opened at least in the partial classification regions of the substrate 11, and the semiconductor material layer 171 of the corresponding material is formed in the grooves 13 in each classification region.
Specifically, in the case where the substrate has only two types of regions, and it is only necessary to form a groove in a portion of the substrate located in one of the types of regions and form the semiconductor material layer in the groove, after the formation operation of the semiconductor material layer is performed once, the subsequent operation can be performed. The substrate is provided with two types of areas, and grooves are required to be respectively formed in the parts of the substrate positioned in the two types of areas, and semiconductor material layers made of corresponding materials are formed; or, in the case that the substrate has at least three types of regions, and it is necessary to form the semiconductor material layer of the corresponding material by forming the recess in the portion of the substrate located in the at least two types of regions, after the formation operation of the semiconductor material layer is performed once, the operation needs to be repeated. The number of times of performing this operation may be set according to the number of types of grooves that the substrate has, the conductivity type of the transistor, and the threshold voltage.
For example: in the case where the substrate has three types of regions and it is necessary to form a groove in each of the portions of the substrate located in the second type of region and the third type of region and form a semiconductor material layer of a corresponding material, as shown in fig. 22 and 23, after forming a groove in the third type of region 113 of the substrate 11 and forming a semiconductor material layer 171 of a corresponding material in the groove, it is necessary to form the mask layer 12 on the substrate 11 so as to expose the target type of region (i.e., the second type of region 112) of the substrate 11. As shown in fig. 24, under the masking action of the masking layer 12, the portion of the substrate 11 located in the second-type region 112 is etched to form the recess 13 in the second-type region 112. As shown in fig. 25, a semiconductor material layer 171 of a corresponding material is formed in the recess located in the second-type region 112, so as to realize that the substrate 11 has three types of regions forming corresponding threshold-like control regions.
As shown in fig. 26 and 27, portions of the substrate 11 and the semiconductor material layer located in the various types of threshold adjustment regions are etched to form fin structures 18 extending in the first direction in each type of threshold adjustment region.
For example, the substrate and the semiconductor material layer may be etched from top to bottom in various threshold control regions by photolithography and etching processes, and fin structures extending along the first direction may be formed in each of the threshold control regions. The fin-shaped structure formed in the threshold value regulation and control region provided with the groove and formed with the semiconductor material layer made of the corresponding material comprises the semiconductor material layer and the rest part of the substrate after the substrate is positioned in the threshold value regulation and control region (when the epitaxial layer is formed in the groove, the epitaxial layer is also included). And the fin-shaped structure formed in the threshold value regulating and controlling region without the groove only comprises the part of the substrate which is positioned in the threshold value regulating and controlling region and is left after being etched. In addition, the first direction may be any direction parallel to the surface of the substrate. The etched depths of the substrate and the semiconductor material layer may be set with reference to the heights of the channel region and the shallow trench isolation.
Note that, as described above, in the case where an epitaxial layer and/or a sidewall protection layer is formed in the groove, the epitaxial layer and/or the sidewall protection layer need to be etched in addition to the semiconductor material layer and the substrate.
As shown in fig. 28 and 29, transistors (not shown) are formed in each type of threshold adjustment region on a per fin-shaped structure 18 basis, so that transistors located in different types of threshold adjustment regions have different threshold voltages.
In one example, the forming a transistor in each type of threshold adjustment region on a per fin structure basis may include:
as shown in fig. 28 and 29, shallow trench isolations 191 are formed on portions of the substrate 11 located between adjacent fin structures 18. The portion of fin structure 18 exposed outside shallow trench isolation 191 is fin 181. The fin 181 has a source/drain region formation region and a channel region.
Illustratively, the forming of the shallow trench isolation on the portion of the substrate between the adjacent fin structures may include:
as shown in fig. 28, an isolation material 19 is formed overlying substrate 11 and fin structures 18. And the third flattening process is performed on the spacer material 19.
For example, the isolation material may be formed by a chemical vapor deposition process or a physical vapor deposition process. The thickness and material of the isolation material can be set according to the actual application scenario. For example: the isolation material may be an insulating material such as silicon dioxide or silicon nitride. And then, third planarization treatment can be carried out on the isolation material, so that the tops of all areas of the rest isolation material are flush, shallow trench isolation with flush tops can be conveniently obtained among different fin-shaped structures, and the yield of the semiconductor device is improved.
The substrate with the fin structures and the remaining isolation material formed thereon is then annealed. Specifically, the treatment temperature and the treatment time of the annealing treatment may be set according to an actual application scenario, and are not specifically limited herein.
As shown in fig. 29, the remaining isolation material is subjected to a second etch back process to obtain shallow trench isolation 191. Specifically, the top height of the shallow trench isolation 191 may be less than or equal to the maximum top height of the remaining portion of the substrate 11 after etching. Alternatively, in the case where an epitaxial layer is formed in the recess, the top height of the shallow trench isolation 191 may be equal to or less than the top height of the remaining portion of the epitaxial layer after etching.
A sacrificial gate extending in a second direction is then formed at an outer periphery of the channel region. The second direction is different from the first direction. And then forming a source/drain region in the source/drain region forming region. And finally, removing the sacrificial gate, and forming a gate stack structure on the periphery of the channel region to obtain the transistor.
Illustratively, a gate material for forming the sacrificial gate may be deposited on the fin and the shallow trench isolation by chemical vapor deposition or the like. And then, etching the gate material by adopting a dry etching mode, and only keeping the part of the gate material, which is positioned at the periphery of the channel region, to obtain the sacrificial gate extending along the second direction. The gate material may be amorphous silicon, polysilicon, or other materials that are easily removed. The second direction may be any direction parallel to the surface of the substrate and different from the first direction. Preferably, the second direction is orthogonal to the first direction. In addition, after the sacrificial gate is formed, the side wall can be formed on the side wall of the sacrificial gate along the width direction by adopting the above mode. The width and the material of the side wall can be set according to practical application scenes. For example: the material of the side wall can be insulating materials such as silicon nitride.
And then, removing the part of the fin part, which is positioned in the source/drain region forming region, and then carrying out epitaxial growth on the source/drain region forming region to obtain the source/drain region meeting the requirement. The source/drain region may be made of a semiconductor material such as silicon, silicon germanium, or germanium. Then, a dielectric material covering the source/drain regions and the sacrificial gate may be formed by chemical vapor deposition or the like. The dielectric material may then be thinned by chemical mechanical polishing or the like until the top of the sacrificial gate is exposed. Accordingly, the remaining dielectric material only covers the source/drain regions, thereby obtaining a dielectric layer. The material and thickness of the dielectric layer may be set according to practical application scenarios, and are not specifically limited herein.
Finally, wet etching and other methods can be adopted,and selectively removing the sacrificial gate positioned at the periphery of the channel region. At this time, the portion of the fin located in the channel region is exposed. And then, a gate dielectric layer and a gate electrode which surround the periphery of the channel region can be sequentially formed by adopting processes such as atomic layer deposition and the like, so that a gate stack structure is obtained. Wherein, the gate dielectric layer may contain HfO2、ZrO2、TiO2Or Al2O3And materials with higher dielectric constants. The thickness of the gate dielectric layer may be set according to actual requirements, and is not specifically limited herein. The gate electrode may be made of conductive material such as TiN, TaN, or TiSiN. In addition, the transistors in different threshold control regions may have gate stack structures with different materials or thicknesses.
It should be noted that the above-mentioned sacrificial gate, source/drain region, dielectric layer and gate stack structure may be formed in various ways. How to form the above-described structure is not an essential feature of the embodiments of the present invention, and therefore, in the present specification, only a brief description thereof will be given so that a person having ordinary skill in the art can easily implement the embodiments provided by the present invention. It is fully contemplated by one of ordinary skill in the art that the above-described structures may be otherwise fabricated.
In addition, in order to simplify the drawings, fig. 17 to 29 only show the schematic structural diagrams after respective operations are performed without forming an epitaxial layer, and do not represent that these operations can be performed only without forming an epitaxial layer.
As can be seen from the foregoing, in the method for manufacturing a semiconductor device according to the embodiment of the present invention, the substrate provided has multiple types of regions. And grooves are respectively formed in at least part of the regions of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in each region, so that the threshold value regulating and controlling regions of corresponding types can be respectively formed in each region of the substrate. And etching the substrate and the part of the semiconductor material layer, which is positioned in each type of threshold regulating region, so as to form a fin-shaped structure in each type of threshold regulating region. Based on the above, the channel regions formed subsequently based on the fin structures formed in the different threshold control regions are also located in the different threshold control regions, so that transistors formed in the different threshold control regions in the manufactured semiconductor device have different threshold voltages. In addition, the semiconductor material layer is formed in grooves formed in different types of regions, and the fin-shaped structure located in each type of threshold value regulating region is formed by etching the semiconductor material layer and the part of the substrate located in the corresponding type of threshold value regulating region, so that the width of the semiconductor material layer is larger than that of the fin-shaped structure. Compared with the prior STI First scheme for forming the semiconductor material layer in the groove obtained by etching the fin-shaped structure, the semiconductor material layer is formed in the groove with larger width in the manufacturing method of the semiconductor device provided by the embodiment of the invention, so that the formed semiconductor material layer has good crystal quality, the quality of a channel region formed based on the semiconductor material layer can be improved, the defects of the channel region are reduced, and the working performance of the semiconductor device is improved.
In the above description, the technical details of patterning, etching, and the like of each layer are not described in detail. It will be appreciated by those skilled in the art that layers, regions, etc. of the desired shape may be formed by various technical means. In addition, in order to form the same structure, those skilled in the art can also design a method which is not exactly the same as the method described above. In addition, although the embodiments are described separately above, this does not mean that the measures in the embodiments cannot be used in advantageous combination.
The embodiments of the present disclosure have been described above. However, these examples are for illustrative purposes only and are not intended to limit the scope of the present disclosure. The scope of the disclosure is defined by the appended claims and equivalents thereof. Various alternatives and modifications can be devised by those skilled in the art without departing from the scope of the present disclosure, and such alternatives and modifications are intended to be within the scope of the present disclosure.

Claims (15)

1. A method of manufacturing a semiconductor device, comprising:
providing a substrate; the substrate has a plurality of types of regions;
respectively forming grooves in the regions of at least part of the regions of the substrate, and forming semiconductor material layers of corresponding materials in the grooves in the regions of each type, so that the regions of each type of the substrate respectively form threshold value regulating and controlling regions of corresponding types;
etching the substrate and the part of the semiconductor material layer, which is positioned in each type of the threshold regulating and controlling region, so as to form a fin-shaped structure extending along a first direction in each type of the threshold regulating and controlling region;
forming a transistor in each type of the threshold adjustment region based on each of the fin structures, such that transistors in different types of the threshold adjustment regions have different threshold voltages.
2. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate has N types of the regions; wherein N is a positive integer greater than or equal to 2;
under the condition that the conduction types of the transistors in the different threshold value regulation and control regions are the same, grooves are respectively formed in the regions of at least one part of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in the regions, and the method comprises the following steps:
respectively forming grooves in the N-1 regions of the substrate, and forming semiconductor material layers of corresponding materials in the grooves in each region; the semiconductor material layers in the grooves of the different regions are made of different materials.
3. The method for manufacturing a semiconductor device according to claim 1, wherein the substrate has an M-class first region, and a P-class second region; the threshold regulation and control region corresponding to the first region is a first threshold regulation and control region; the threshold regulation region corresponding to the second region is a second threshold regulation region; the conductivity type of the transistor positioned in the first threshold regulation region is different from that of the transistor positioned in the second threshold regulation region;
when M is 1 and P is a positive integer greater than or equal to 2, the substrate is provided with grooves in at least some of the regions, and semiconductor material layers of corresponding materials are formed in the grooves in the regions, and the method comprises the following steps: forming grooves in the P-1 type second regions of the substrate, and forming semiconductor material layers made of corresponding materials in the grooves in the second regions;
when M is a positive integer of 2 or more and P is 1; the method for forming the semiconductor material layer comprises the following steps of respectively forming grooves in the regions of at least part of the regions of the substrate, and forming the semiconductor material layer made of the corresponding material in the groove in each region, wherein the method comprises the following steps: forming grooves in the M-1 first regions of the substrate, and forming semiconductor material layers of corresponding materials in the grooves in the first regions;
under the condition that M and P are positive integers which are more than or equal to 2, grooves are respectively formed in the regions of at least part of the regions of the substrate, and semiconductor material layers made of corresponding materials are formed in the grooves in the regions of each type, the method comprises the following steps: and forming grooves in the first region of the M-1 type and the second region of the P-1 type of the substrate, and forming semiconductor material layers of corresponding materials in the grooves in the first region of each type and the second region of each type.
4. The method for manufacturing a semiconductor device according to claim 3, wherein M and P are both equal to 1;
the method for forming the semiconductor material layer comprises the following steps of respectively forming grooves in the regions of at least part of the regions of the substrate, and forming the semiconductor material layer made of the corresponding material in the groove in each region, wherein the method comprises the following steps:
forming a groove in the first region of the substrate, and forming a semiconductor material layer of a corresponding material in the groove in the first region; and/or the presence of a gas in the gas,
and forming a groove in the second area of the substrate, and forming a semiconductor material layer made of a corresponding material in the groove in the second area.
5. The method for manufacturing a semiconductor device according to claim 1, wherein the forming of the grooves in the regions of at least some of the regions of the substrate and the forming of the semiconductor material layer of the corresponding material in the grooves in each of the regions comprises:
forming a mask layer on the substrate to expose a target type area of the substrate;
etching the part of the substrate, which is positioned in the target area, under the mask action of the mask layer so as to form the groove in the target area of the substrate;
forming the semiconductor material layer made of corresponding materials in the groove positioned in the target type region;
and repeating the steps until grooves are respectively formed in the regions of at least part of the regions of the substrate, and forming semiconductor material layers of corresponding materials in the grooves in the regions of each type.
6. The method according to claim 5, wherein the etching of the portion of the substrate located in the target region under the mask action of the mask layer is performed to open the groove in the target region of the substrate, and before forming the semiconductor material layer of the corresponding material in the groove located in the target region, the method further comprises:
and forming a side wall protective layer covering the side wall of the groove.
7. The method according to claim 5 or 6, wherein the etching of the portion of the substrate located in the target region under the mask action of the mask layer is performed to open the groove in the target region of the substrate, and before forming the semiconductor material layer of the corresponding material in the groove located in the target region, the method further comprises:
oxidizing the groove to form an oxide layer at least on the groove bottom of the groove;
removing the oxide layer; and/or the presence of a gas in the gas,
an epitaxial layer is formed overlying at least the bottom of the recess.
8. The method for manufacturing a semiconductor device according to claim 7, wherein the substrate is a silicon-based substrate; the epitaxial layer is made of silicon.
9. The method as claimed in claim 5, wherein the forming of the semiconductor material layer of the corresponding material in the recess of the target region comprises:
extending the semiconductor material with corresponding material inside and outside the groove positioned in the target type area; the top height of the semiconductor material is greater than that of the mask layer;
sequentially carrying out first planarization treatment and first etching-back treatment on the semiconductor material so that the residual semiconductor material forms the semiconductor material layer; the top of the semiconductor material layer is flush with the surface of the substrate;
and removing the mask layer and removing the part of the side wall protection layer outside the groove.
10. The method according to claim 5, wherein removing the mask layer and removing the sidewall protection layer outside the recess when the mask layer is made of the same material as the sidewall protection layer comprises:
removing the side wall protection layer outside the groove while removing the mask layer; or the like, or, alternatively,
under the condition that the material of the mask layer is different from that of the side wall protection layer, removing the mask layer and removing the part of the side wall protection layer, which is positioned outside the groove, comprises the following steps:
and sequentially removing the mask layer and the part of the side wall protection layer outside the groove.
11. The method according to claim 5, wherein in a case where the material of the mask layer is the same as the material of the sidewall protection layer, the forming of the semiconductor material layer of a corresponding material in the recess in the target region comprises:
extending the semiconductor material with corresponding material inside and outside the groove positioned in the target type area; the top height of the semiconductor material is greater than that of the mask layer;
performing first planarization treatment on the semiconductor material to enable the top of the residual semiconductor material to be flush with the top of the mask layer;
removing the mask layer and the part of the side wall protection layer outside the groove;
and carrying out second planarization treatment on the rest of the semiconductor material to obtain the semiconductor material layer.
12. The method according to claim 5, wherein, in a case where a material of the mask layer is different from a material of the sidewall protection layer, the forming of the semiconductor material layer of a corresponding material in the recess in the target region comprises:
extending the semiconductor material with corresponding material inside and outside the groove positioned in the target type area; the top height of the semiconductor material is greater than that of the mask layer;
performing first planarization treatment on the semiconductor material to enable the top of the residual semiconductor material to be flush with the top of the mask layer;
removing the mask layer;
performing second planarization treatment on the side wall protection layer and the residual semiconductor material so that the tops of the residual side wall protection layer and the residual semiconductor material are flush with the surface of the substrate; the remaining semiconductor material forms the layer of semiconductor material.
13. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein the material of the semiconductor material layer is silicon germanium, germanium tin or a III-V material.
14. The method for manufacturing a semiconductor device according to any one of claims 1 to 6, wherein forming a transistor in each type of the threshold adjustment region on the basis of each of the fin-shaped structures includes:
forming shallow trench isolations on portions of the substrate between adjacent ones of the fin structures; the part of the fin-shaped structure exposed outside the shallow trench isolation is a fin part; the fin part is provided with a source/drain region forming region and a channel region;
forming a sacrificial gate extending in a second direction at the periphery of the channel region; the second direction is different from the first direction;
forming a source/drain region in the source/drain region forming region;
and removing the sacrificial gate, and forming a gate stack structure on the periphery of the channel region to obtain the transistor.
15. The method of manufacturing a semiconductor device according to claim 14, wherein the forming shallow trench isolation on a portion of the substrate between adjacent fin structures comprises:
forming an isolation material overlying the substrate and the fin structure; and carrying out third planarization treatment on the isolation material;
annealing the substrate formed with the fin structure and the remaining isolation material;
and carrying out second etching back treatment on the rest isolation material to obtain the shallow trench isolation.
CN202110350865.0A 2021-03-31 2021-03-31 Method for manufacturing semiconductor device Pending CN113130485A (en)

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