CN113128147B - Integrated circuit testability design method based on machine learning - Google Patents
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Abstract
The invention discloses a high-efficiency integrated circuit testability design method based on machine learning, which comprises the steps of configuring different parameters, inserting a scan chain by using a tool, generating an automatic test vector and analyzing power consumption, and collecting an operation result; reading the collection result into a set parameter in a prediction model based on machine learning to obtain a predicted value; and merging all the predicted values and the collected operation results to be stored as csv files, and starting a predicted optimal configuration model to obtain the optimal configuration of the design requirement. The method of the invention achieves the purposes of less operation time, low power consumption and low area overhead while ensuring high test coverage.
Description
Technical Field
The invention relates to the technical field of integrated circuit testability design, in particular to a high-efficiency integrated circuit testability design method based on machine learning.
Background
Microelectronic technology has been following moore's law for decades, i.e. integration level is doubled every 18 months, size is reduced 1000 times in 30 years, performance is improved 1 ten thousand times, mass production process of super large scale integrated circuit manufacturing technology has reached 7nm nowadays, and with the improvement of process, process is advancing to 5nm and 3 nm; the complexity of chips is higher and higher, the challenges of testing and diagnosis are increased continuously, the capability and level of integrated circuit testing are one of the key means for ensuring the performance and quality of integrated circuits, and further improvement of the test coverage and the test time on the traditional testability design flow becomes a problem to be solved urgently.
The ideal test target is low test cost and high fault coverage rate, and in the testability design, problems of overlong test time, reduced test coverage rate and the like of a chip can be caused by non-optimized configuration parameters, so that the yield of the chip is influenced, and the high efficiency and the reliability of the chip are adversely influenced; for example, the setting of the scan compression ratio in the design for testability is often determined according to the design experience of engineers or repeated debugging, the scan compression reduces the test time by increasing the number of scan chains by X times, and the number of required test vectors is increased due to the increase of the number of scan chains, which is called "test vector expansion" problem, that is, the probability of propagating an irrelevant value to an output port is increased, thereby masking a target fault. In other words, setting a larger compression ratio does not always reduce the test time, and therefore, how to set a suitable compression ratio is a matter of consideration.
Disclosure of Invention
This section is for the purpose of summarizing some aspects of embodiments of the invention and to briefly introduce some preferred embodiments. In this section, as well as in the abstract and the title of the invention of this application, simplifications or omissions may be made to avoid obscuring the purpose of the section, the abstract and the title, and such simplifications or omissions are not intended to limit the scope of the invention.
The present invention has been made in view of the above-mentioned conventional problems.
Therefore, the invention provides a high-efficiency integrated circuit testability design method based on machine learning, which can solve the problems of overlong test time, low test coverage, large area overhead and high power consumption caused by incapability of determining optimal parameter configuration in the traditional design process.
In order to solve the technical problems, the invention provides the following technical scheme: configuring different parameters, inserting a scan chain by using a tool, generating an automatic test vector and analyzing power consumption, and collecting an operation result; reading the collection result into a set parameter in a prediction model based on machine learning to obtain a predicted value; and merging all the predicted values and the collected operation results to be stored as csv files, and starting a predicted optimal configuration model to obtain the optimal configuration of the design requirement.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: reading a netlist file to be designed before collecting the operation result, and configuring the number of scan chains and the minimum proportion parameter of scan compression by using a Synopsys DFT Compiler tool before executing the insertion of the scan chains; for circuits with different configuration combinations, the Synopsys DFT Compiler tool is used for inserting a scan chain, the TetraMax tool is used for executing automatic test vector generation and PrimePower is used for power consumption analysis.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: collecting the operation result comprises replacing the number of the scan chains and the scan compression minimum proportion parameter by using a perl script; inserting scan chains into parameters with different configurations, generating automatic test vectors and analyzing power consumption; and collecting test coverage, automatic test vector generation time, test time, power consumption and area operation results.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: obtaining the predicted value comprises storing the collected operation result as the csv file, reading in the prediction model based on machine learning, wherein the prediction model adopts a gradient descent algorithm; wherein, the learning rate is 0.01, the iteration times is 600, the theta value which enables the function to be converged is obtained, and the parameter to be predicted is set to obtain the predicted value.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: the prediction model comprises a single-target parameter prediction model, before each operation, the number of scan chains to be predicted and the minimum proportion parameter of scan compression proportion are set according to requirements, the prediction model only predicts the single target parameter, if five configured target parameters, namely test coverage, automatic test vector generation time, test time, area and power consumption, need to be predicted, csv files containing different target parameters need to be read, the prediction model is executed for 5 times, and the function of the prediction model is as follows,
wherein x is the number of scan chains to be predicted and configured, which are set according to requirements, during each operation, and y is the scan compression minimum proportion parameter to be predicted and configured, which is set according to requirements before each operation.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: merging and storing all the predicted values and the collected operation results as the csv file, and starting a predicted optimal configuration model; and the prediction optimal configuration model is used for carrying out normalization processing on operation results obtained by different configuration of each parameter, calculating the error ratio of the operation results and the optimal value, and solving the sum of the operation results.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: the method also comprises the steps of requiring reverse order or positive order arrangement according to the single parameter optimal value of each parameter, and reserving the configuration of the first 20 percent; reserving the intersection of the first 20% optimal configuration of each parameter; and outputting each operation result and the sum of each operation result to obtain a prediction result of the optimal configuration of the single target parameter and a loss value of the multi-parameter balance, and outputting the optimal configuration.
As a preferred embodiment of the method for designing testability of high-efficiency integrated circuit based on machine learning according to the present invention, wherein: the predicted optimal configurationThe model comprises the steps of utilizing the test coverage rate, the automatic test vector generation time, the test time, the area and the power consumption to balance and predict the optimal configuration, and the running result and five target parameters data in the intersection of the optimal configuration of the first 20 percent of all parametersnewThe sum, as follows,
sum＝datanew1+datanew2+datanew3+datanew4+datanew5
wherein, the datanew1For testing coverage rate, datanew2Generating time, data for automatic test vectorsnew3For testing time, datanew4Is area, datanew5Is the power consumption.
The invention has the beneficial effects that: in the traditional testability design flow, parameters such as the number of scan chains and the minimum scan compression ratio are configured differently, and tools are used for collecting operation results such as test coverage rate, operation time, power consumption and area; reading the result into a prediction model based on machine learning, and setting parameters to be predicted to obtain a target parameter prediction value; and starting the optimal configuration prediction model for all the results to obtain the optimal configuration of the design, thereby achieving the purposes of ensuring high test coverage rate and simultaneously having less operation time, low power consumption and low area overhead.
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In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without inventive exercise. Wherein:
FIG. 1 is a flowchart illustrating a method for designing testability of an efficient IC based on machine learning according to an embodiment of the present invention;
FIG. 2 is a flow chart illustrating a data collection phase of a method for designing high efficiency integrated circuit testability based on machine learning according to an embodiment of the present invention;
FIG. 3 is a flow chart of a parameter prediction stage of a method for high efficiency design for integrated circuit testability based on machine learning according to an embodiment of the present invention;
FIG. 4 is a diagram illustrating cost variation with iteration number of a method for designing testability of a high-efficiency integrated circuit based on machine learning according to an embodiment of the present invention;
FIG. 5 is a flowchart illustrating an optimal configuration prediction phase of a method for high efficiency design for testability based on machine learning according to an embodiment of the present invention;
FIG. 6 is a diagram illustrating the output of the optimal configuration prediction stage of the method for designing high efficiency testability integrated circuits based on machine learning according to an embodiment of the present invention.
Detailed Description
In order to make the aforementioned objects, features and advantages of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below, and it is apparent that the described embodiments are a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be obtained by a person skilled in the art without making creative efforts based on the embodiments of the present invention, shall fall within the protection scope of the present invention.
In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present invention, but the present invention may be practiced in other ways than those specifically described and will be readily apparent to those of ordinary skill in the art without departing from the spirit of the present invention, and therefore the present invention is not limited to the specific embodiments disclosed below.
Furthermore, reference herein to "one embodiment" or "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one implementation of the invention. The appearances of the phrase "in one embodiment" in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments.
The present invention will be described in detail with reference to the drawings, wherein the cross-sectional views illustrating the structure of the device are not enlarged partially in general scale for convenience of illustration, and the drawings are only exemplary and should not be construed as limiting the scope of the present invention. In addition, the three-dimensional dimensions of length, width and depth should be included in the actual fabrication.
Meanwhile, in the description of the present invention, it should be noted that the terms "upper, lower, inner and outer" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the drawings, and are only for convenience of describing the present invention and simplifying the description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation and operate, and thus, cannot be construed as limiting the present invention. Furthermore, the terms first, second, or third are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
The terms "mounted, connected and connected" in the present invention are to be understood broadly, unless otherwise explicitly specified or limited, for example: can be fixedly connected, detachably connected or integrally connected; they may be mechanically, electrically, or directly connected, or indirectly connected through intervening media, or may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
Example 1
Referring to fig. 1, a first embodiment of the present invention provides a method for designing testability of an integrated circuit with high efficiency based on machine learning, which specifically includes:
s1: and configuring different parameters, inserting a scan chain by using a tool, generating an automatic test vector, analyzing power consumption and collecting an operation result. Referring to fig. 2, it should be noted that, before collecting the operation result, the following steps are included:
reading a netlist file to be designed, and configuring the number of scan chains and the minimum proportion parameter of scan compression by using a Synopsys DFT Compiler tool before executing the insertion of the scan chains;
configuring the number of scan chains by using a set _ scan _ configuration-chain _ count number command, wherein the scan chains are respectively configured to be 1, 2, 3, 4, 5, 6, 7, 8, 9 and 10 (total 10 different configurations);
configuring the scan compression minimum ratio parameter by using a set _ scan _ compression _ configuration-minimum _ compression number command, wherein the scan compression minimum ratio parameter is respectively configured to be 2, 3, 4, 5, 6 and 7 (totally 6 different configurations), so as to obtain 60 different configuration combinations;
the assigned value of the configuration can be defined by the circuit size and the user requirement (the scan compression minimum ratio parameter configuration allowable range can not be less than 2);
for circuits with different configuration combinations, a Synopsys DFT Compiler tool is used for inserting a scan chain, a TetraMax tool is used for performing automatic test vector generation and PrimePower is used for power consumption analysis.
Further, collecting the operation result comprises:
replacing the number of the scan chains and the minimum proportion parameter of scan compression by using a perl script;
inserting scan chains into parameters with different configurations, generating automatic test vectors and analyzing power consumption;
and collecting test coverage, automatic test vector generation time, test time, power consumption and area operation results.
S2: reading the collected results into a prediction model based on machine learning to set parameters, and obtaining a predicted value. It should be noted that, in this step, obtaining the predicted value includes:
storing the collected operation result as a csv file, reading in a prediction model based on machine learning, wherein the prediction model adopts a gradient descent algorithm;
the model is implemented by python programming, wherein the learning rate is 0.01 and the iteration number is 600;
after the program is executed, the parameters to be predicted (for example, 12 and 9 are input, namely the number of 12 scan chains is represented, and the minimum proportion parameter of scan compression is 9) are manually input, the prediction model obtains the theta value which enables the function to be converged through 600 iterations, and therefore the program automatically substitutes the set 12 and 9 into the function to obtain the predicted value.
Specifically, the prediction model includes:
the prediction model is a single-target parameter prediction model, before each operation, the number of scan chains to be predicted and the minimum proportion parameter of the scan compression ratio are set according to requirements, the prediction model only predicts the single target parameter, if five target parameters to be predicted and configured, namely test coverage, automatic test vector generation time, test time, area and power consumption, need to read in csv files containing different target parameters, execute the prediction model for 5 times, and the function of the prediction model is as follows,
wherein x is the number of scan chains to be predicted and configured, which are set according to requirements, during each operation, and y is the scan compression minimum proportion parameter to be predicted and configured, which is set according to requirements before each operation.
S3: and merging all predicted values and collecting operation results to be stored as csv files, and starting a predicted optimal configuration model to obtain the optimal configuration of the design requirement. Referring to fig. 5, it is also to be noted that:
merging and storing all predicted values and collected operation results into csv files, and starting a predicted optimal configuration model;
the optimal configuration predicting model can predict the configuration (the number of scan chains and the scan compression minimum proportion parameter) which is most suitable for the circuit, so that the circuit obtains better test coverage rate, automatic test vector generation time, test time, area and power consumption;
the prediction optimal configuration model carries out normalization processing on operation results obtained by different configuration of each parameter, and calculates the error ratio of the operation results and the optimal value to obtain the sum of the operation results;
the operation results obtained by different configuration of each parameter are 60 collected operation results with different configuration and 140 obtained predicted values, and the predicted values can be set into a plurality of groups of different configuration parameters according to the circuit size and the user requirements to obtain a plurality of groups of predicted values, wherein the total number of the operation results is 200 different configurations.
Specifically, the optimal value error ratio calculation process includes:
taking the target parameter of the automatic test vector generation time as an example, the optimal automatic test vector generation time in 200 different configurations is 1.61s (the optimal value is the minimum value), wherein the data is the automatic test vector generation time corresponding to each different configuration, and the data is the databestGenerating a time optimum (i.e., 1.61s) for the automatic test vectors;
the optimal value error proportion calculation formula of the test time, the area and the power consumption is the same as the optimal value error proportion calculation formula of the automatic test vector generation time, and the data in the optimal value error proportion calculation formula of the test coverage ratebestThe optimum value is the maximum value, as follows,
datanew＝|data-databest|/data
the configuration of the first 20 percent (the setting of the value can better select the optimal configuration of the single parameter and obtain the intersection of multi-parameter balance, if the setting is too low, the intersection is easy to be an empty set, and if the setting is too high, the poor configuration is reserved and displayed, thereby wasting computing resources) is reserved;
reserving the intersection of the first 20% optimal configuration of each parameter;
and outputting each operation result and the sum of each operation result to obtain a prediction result of the optimal configuration of the single target parameter and a loss value of the multi-parameter balance, and outputting the optimal configuration.
Further, predicting the optimal configuration model includes:
the optimal configuration is predicted in a balanced mode by utilizing five target parameters including test coverage, automatic test vector generation time, test time, area and power consumption, the operation result is summed with five target parameters data in the intersection of the optimal configuration of the first 20 percent of all the parametersnewThe sum, as follows,
sum＝datanew1+datanew2+datanew3+datanew4+datanew5
wherein, the datanew1For testing coverage rate, datanew2Generating time, data for automatic test vectorsnew3To test the time、datanew4Is area, datanew5Is the power consumption.
If the user's requirement is more focused on a certain target parameter, the formula can be multiplied by a weighting factor x, where x is set to 2, i.e. the ratio of a certain target parameter is doubled, for example, when it is more desirable that the circuit configuration has better test coverage, the formula is as follows:
example 2
This embodiment is explained separately from the following three phases (data collection phase, parameter prediction phase, and optimal configuration prediction phase) in order to facilitate understanding of the present invention by those skilled in the art, as follows:
(1) a data collection phase.
Referring to fig. 2, this stage is implemented as follows:
s1: preparing a needed library and a design netlist file, wherein the netlist file is obtained by RTL design through synthesis by using a Synopsys DC tool;
s2: reading a netlist file, performing design testability design by using a Synopsys DFT Compiler tool, configuring parameters such as the number of scan chains and the minimum compression ratio of scan compression, reporting area overhead after inserting the scan chains, and saving the design netlist;
s3: utilizing a TetraMax tool to automatically generate test vectors for the design inserted into the scan chain, and storing the generated test vector files;
s4: simulating the design and test vectors inserted into the scan chain by using a VCS tool to obtain a fsdb waveform file, and performing power consumption analysis by using PrimePower;
s5: storing the configured parameters (the number of scan chains and the minimum compression ratio of scan compression) and target parameters (test coverage rate, test time, area overhead and power consumption) in a csv file;
s6: and replacing the value of the configuration parameter by using a perl script, repeating the process for n times, wherein the value of n is determined by the size of the circuit, and the higher the value of n is, the smaller the error of the subsequent prediction model is.
(2) And a parameter prediction stage.
Referring to fig. 3, this stage is implemented as follows:
s1: reading in the csv file obtained in the data collection stage, and extracting the data;
s2: setting a linear regression function, and defining the learning rate to be 0.01 and the iteration number to be 600;
s3: carrying out mean value normalization operation on the extracted configuration parameters;
s4: using a gradient descent algorithm (the gradient descent algorithm continuously searches a theta set which enables the value of the cost function to be minimum, the cost function is used for calculating the error of the real data and the data in the hypothesis function), obtaining the theta value which enables the function to be converged, creating a matrix used for storing the theta of each iteration and a matrix used for storing the value of the cost function obtained by the theta, and performing 600 iterations;
s5: in the iteration process, the cost function value is calculated and output in each iteration, and referring to fig. 4, the cost function value is decreased, which shows that the theta value which enables the function to be converged can be found by the algorithm;
s6: and setting a configuration parameter value to be predicted so as to obtain a predicted value of the target parameter, and storing the result in the csv file.
(3) The optimal configuration prediction phase.
Referring to fig. 5, this stage is implemented as follows:
s1: merging and storing all the predicted data and the collected operation results into csv files, and starting a predicted optimal configuration model;
s2: carrying out normalization processing and single-parameter loss value calculation on target parameter values obtained by different configuration of each parameter, and solving the sum of the loss values of each target parameter;
s3: taking the test coverage rate parameter as an example, reserving the first 20% configuration of the reverse sequence arrangement, then reserving the first 20% configuration of the running time positive sequence arrangement, and similarly, performing the same treatment on the area and power consumption parameters, and reserving the intersection of the first 20% optimal configuration of each parameter;
s4: and displaying the target parameters and the sum of the target parameters of the intersection in a histogram mode, and outputting the loss value after multi-parameter balance by referring to fig. 6, thereby obtaining the optimal configuration prediction result, wherein the smaller the loss value, the less the configuration running time, the higher the test coverage rate, the low power consumption and the small area overhead are.
Example 3
In order to better verify and explain the technical effects adopted in the method of the present invention, the present embodiment selects to perform a comparison test with the conventional testability design flow and the method of the present invention, and compares the test results with a scientific demonstration means to verify the actual effects of the method of the present invention.
In a conventional testability design flow, for configuration of parameters such as the number of scan chains and the minimum scan compression ratio, the scan chains are configured arbitrarily according to experience of engineers, and realization of optimal configuration cannot be guaranteed. Compared with the traditional method, the method can obtain the optimal configuration, thereby achieving the purposes of ensuring high test coverage rate, and simultaneously having less automatic test vector generation time, less test time, low power consumption and low area overhead. In this embodiment, the test samples of the simulation platform are measured and compared in real time by using the conventional design flow for testability and the method of the present invention.
Table 1: and comparing the test data table.
Referring to table 1, configurations 1 to 4 are results obtained by empirically configuring the number of scan chains and the minimum scan compression ratio in a conventional design process for testability, and compared with the conventional design process for testability, for the circuit, the test coverage is higher than that of other four configurations, the automatic test vector generation time and the power consumption are lower than those of other four configurations, and for the test time, the test coverage is several times shorter than that of configurations 1 to 3, although the test time of configuration 4 is less than that of the configuration of the present invention, the test coverage is extremely low, and for the area, the configuration of the present invention is slightly higher than those of other four configurations, but considering that the other four target parameter values are superior, the area is more than that of other configurations and can be ignored.
It should be noted that the above-mentioned embodiments are only for illustrating the technical solutions of the present invention and not for limiting, and although the present invention has been described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions may be made on the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, which should be covered by the claims of the present invention.
Claims (4)
1. A high-efficiency integrated circuit testability design method based on machine learning is characterized in that: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
configuring different parameters, inserting a scan chain by using a tool, generating an automatic test vector and analyzing power consumption, and collecting an operation result;
reading the collection result into a set parameter in a prediction model based on machine learning to obtain a predicted value;
merging all the predicted values and the collected operation results to be stored as csv files, starting a predicted optimal configuration model to obtain the optimal configuration of the design requirement,
the collecting of the operation result comprises before,
reading a netlist file to be designed, and configuring the number of scan chains and the minimum proportion parameter of scan compression by using a Synopsys DFT Compiler tool before executing the insertion of the scan chains;
for circuits with different configuration combinations, the Synopsys DFT Compiler tool is used for inserting a scan chain, the TetraMax tool is used for executing automatic test vector generation and PrimePower is used for power consumption analysis,
collecting the results of the operation may include,
replacing the number of the scan chains and the scan compression minimum proportion parameter by using a perl script;
inserting scan chains into parameters with different configurations, generating automatic test vectors and analyzing power consumption;
collecting test coverage, automatic test vector generation time, test time, power consumption and area operation results,
the obtaining of the predicted value includes obtaining a predicted value,
storing the collected operation result as the csv file, reading in the prediction model based on machine learning, wherein the prediction model adopts a gradient descent algorithm;
wherein the learning rate is 0.01, the iteration times is 600, the theta value which enables the function to be converged is obtained, the parameter to be predicted is set, the predicted value is obtained,
the predictive model may include, for example,
the prediction model is a single-target parameter prediction model, before each operation, the number of scan chains to be predicted and the minimum proportion parameter of the scan compression proportion are set according to requirements, the prediction model only predicts the single target parameter, if five configured target parameters, namely test coverage, automatic test vector generation time, test time, area and power consumption, need to be predicted, csv files containing different target parameters need to be read, the prediction model is executed for 5 times, and the functions of the prediction model are as follows,
z＝thetaValue[0，0]+(thetaValue[0，1]*x)+(thetaValue[0，2]*y)
and x is the number of the scanning chains to be predicted and configured according to the requirement before each operation, and y is the scanning compression minimum proportion parameter to be predicted and configured according to the requirement before each operation.
2. The method of claim 1, wherein: comprises the steps of (a) preparing a mixture of a plurality of raw materials,
merging and storing all the predicted values and the collected operation results as the csv file, and starting a predicted optimal configuration model;
and the prediction optimal configuration model is used for carrying out normalization processing on operation results obtained by different configuration of each parameter, calculating the error ratio of the operation results and the optimal value, and solving the sum of the operation results.
3. The method of claim 2, wherein the method further comprises: also comprises the following steps of (1) preparing,
the single parameter optimal values of all the parameters require reverse order or positive order arrangement, and the first 20 percent of configuration is reserved;
reserving the intersection of the first 20% optimal configuration of each parameter;
and outputting each operation result and the sum of each operation result to obtain a prediction result of the optimal configuration of the single target parameter and a loss value of the multi-parameter balance, and outputting the optimal configuration.
4. The method of claim 3, wherein the design for testability of the IC is based on machine learning, and the method comprises: the model for predicting the optimal configuration includes,
and balancing and predicting the optimal configuration, the operation result and five target parameters data in the intersection of the optimal configuration of the parameters of the first 20 percent by using the test coverage, the automatic test vector generation time, the test time, the area and the power consumptionnewThe sum, as follows,
sum＝datanew1+datanew2+datanew3+datanew4+datanew5
wherein, the datanew1For testing coverage rate, datanew2Generating time, data for automatic test vectorsnew3For testing time, datanew4Is area, datanew5Is the power consumption.
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