CN1330972C - Quick integrated circuit testing process optimization method - Google Patents
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Abstract
The present invention relates to a quick optimization method for an integrated circuit test flow. The test time of failure chips is reduced through reordering test items. The method comprises the following steps; S10: test vectors and a test flow at a check analysis stage are confirmed; S20: the confirmed test vectors and the confirmed test flow are used for the check analysis of the chips, and an original pass / failure test information table is obtained; S30: a conversion program is called and converts the pass / failure test information table into a test item efficiency table; S40: an ordering method based on test efficiency coefficients is applied to the optimization of the test items so as to obtain an optimized test flow. The optimization method provided by the present invention has the characteristics of simplicity, easy realization and high optimization speed which enables the present invention to be particularly suitable for being applied to the conditions that modern SOC (system on chip) tests generally have plentiful test items.
Description
Technical field
The present invention relates to the TEST TECHNOLOGY OF LSI field, particularly a kind of flow optimization method of integrated circuit testing fast is a kind of method of integrated circuit (IC) chip being carried out failure analysis and reduction testing cost.
Background technology
The fast development of semiconductor technology promoted chip integration with the increasing sharply of frequency of operation.The increase of working frequency of chip not only can increase the chip design difficulty, and makes the later stage testing cost of chip also and then increase.The reason that causes the modern chips testing cost to increase has: 1) working frequency of chip increases rapidly, make the frequency of operation of the testing apparatus that the true speed test must be provided also corresponding raising will take place thereupon, yet the cost of high-frequency testing apparatus is very high.2) test duration long, long coming from the modern chips test of test duration, the quantity of module to be tested is very huge, these modules are comprehensively tested needs long time.3) amount of test data is bulky makes to the testing apparatus request memory of storing these data volumes greatlyyer, and the large storage capacity internal memory can increase the cost on the single passage of testing apparatus.4) pin of modern chips is many, these chips is tested the test channel that needs equal number.The increase of number of channels also can increase the cost of testing apparatus.
The test of chip mainly comprises three partial tests: functional test, structured testing and parameter testing.Functional test is to use the functional test vector set that produces according to the chip design standard that chip is tested.These vector sets carry out one by one test to the function of circuit under test.But functional test vector set cause chip design personnel provide or derive from the functional validation test vector that chip generates at Qualify Phase.Directly functions of use property testing vector carries out finished product test to chip two main problems (1) functional test vector is arranged is not very high to the physical imperfection coverage rate in the chip manufacturing.(2) functional test vector volume ratio is huger.In order to improve test coverage and to reduce testing cost, structural test is generally adopted.Structural test has comprised test frames such as common sweep test, logic built-in self-test, memory built in self test of sram, mimic channel built-in self-test, boundary scan, test resource division.Because structural test vector is to produce at the abstract fault model of actual physics defective, therefore for function vector, structural test vector to the coverage rate of the physical imperfection in the chip manufacturing proces than higher.Simultaneously, the mechanism that produces from top structural test vector as can be seen, structural test vector has very strong specific aim, this makes that the test vector volume ratio that produces is less.Parameter testing is the test that applies in order to guarantee chip parameter when working to meet the requirement of working environment, and parameter testing comprises the characterisitic parameter test of setting up retention time characteristic test, chip supply clock of dc parameter test, AC parameter test, bus etc.
The formation of having analyzed test event can be found a method that reduces testing cost: analyze by the coverage rate to test vector, delete as far as possible that some are lower or do not have a test vector of what covering power to the physical imperfection coverage rate in the reality test.Yet, reduce test vector and no doubt can reduce and apply these vectorial time, but the minimizing of test vector can influence the test coverage to chip.
The another one thinking that reduces the test duration is to reduce the test duration of chip failing.During chip testing, testing apparatus has two kinds of patterns to be provided with usually: " testing up to all items " pattern and " mistake-stop " pattern.The pattern that " tests up to all items " refers to all will test all test events, does not also stop when inconsistent even a chip in test, has run into real response and Expected Response on certain project, and all test items have been estimated in continuation." mistake-stop " pattern means if testing apparatus is found mistake, then stops test immediately, and chip is put in the corresponding failure modes box.Chip in order to collect fail data as far as possible, needs to adopt first kind of pattern in the stage of check analysis.When chip has been finished failure analysis, when carrying out volume production test in enormous quantities, all select " mistake-stop " pattern for use, because under this pattern, for a chip, in case find fault, test can stop immediately.Can save the test duration of chip failing like this.Like this, if testing apparatus adopts " mistake-stop " pattern, the test duration of chip failing is actually the found time of first fault of chip.Come the front of whole testing process if will find the more intense test vector of failure of removal ability, chip failing just can be eliminated at the test initial stage with big probability so, thereby has reduced the test duration and the cost of chip failing.Adopt this method, essence will be optimized testing process exactly.
Test event is to finish the combination of a series of test vectors of a test target.The division of test event is changeable, generally divides according to the object and the target of reality test.Suppose to have n test event, these test events are: I
1, I
2..., L
nTesting process FLOW is an ordered set of test event, FLOW={I
1, I
2..., I
n.The set of m chip failing to be measured is: D={D
1, D
2, D
3..., D
m, the test duration that obtains each chip failing according to testing process FLOW is: T={T
D1, T
D2, T
D3..., T
Dn, testing process optimization just changes into like this:
Seek a testing process FLOW={I
1, I
2..., I
n, make:
Dynamic programming algorithm can be used for addressing this problem.Dynamic programming algorithm adopts the multistep decision process.At first to set up an objective function, in the dynamic programming process, represent the multistep decision process with a non-directed graph, in this non-directed graph, each node is represented a test event, and line is represented this two test event consumed time between two continuous decision phase adjacent nodes.Each stage is calculated total testing cost by objective function.Make the search volume that needs in this way very big, suppose that testing process is made of n test event, so whole state search space is 2
n, on average the output variable of each state is: (n+1)/2, its computation complexity is O (dn2 just
n).The applied dynamic programming method can be with reference to following document to testing process optimization:
“Optimal ordering of analog integrated circuit test to minimize test time”，byS.D.Huss and R.S.Gyurcsik，Published in the Proceeding of IEEE DesignAutomation Conference，1991，494～499。
“Defect-Oriented Test Scheduling”，by W.Jiang，B.Vinnakota，Published inIEEE Transaction on Very Large Scale Integration(VLSI)Systems，Vol.9，No 3，JUNE2001，427～438”
Though use dynamic programming algorithm can guarantee to obtain optimum solution, yet the time complexity of its exponential increase makes it be difficult to be applicable in the test of modern SOC large project amount.
The present invention proposes a kind of new testing process optimization method based on failure analysis.This method adopts a new data structure-test validity table.Different with common dynamic programming algorithm, the present invention adopts the greedy algorithm based on heuristic information, though this greedy algorithm can not always guarantee to obtain optimum solution, yet, its fast optimal speed can make it in short time, produce an acceptable testing process optimization result.
Summary of the invention
The object of the present invention is to provide a kind of flow optimization method of integrated circuit testing fast.
The test duration that the present invention is directed to chip failing reduces, and has proposed a kind of sort method of testing process fast.The advantage that this method has simply, hangs down time complexity, is easy to realize.These advantages make it be particularly suitable for the many test environments of test event in the current SOC test.
One of the object of the invention provides the list structure-test validity table of a storage chip failure analysis result data.This list structure is simple, the space complexity of table be test event square.
Two of the object of the invention provides a kind of heuristic sort method based on the test validity table, this sort method is used to produce a testing process optimization result, this result can significantly reduce the test duration of chip failing, thus the testing cost when reducing the test of chip volume production.
The invention technical scheme
Failure analysis data when the test optimization method that the present invention proposes is based on chip carried out check analysis.
The integrated circuit testing flow optimization method is collected the data of the chip failing that obtains by handling Qualify Phase fast, and the test event in the testing process is sorted, and reaches the purpose that reduces the chip failing testing cost.
Be made of a series of test events of finishing the fc-specific test FC task, test event is arranged in order in the testing process.
Chip testing generally will divide two stages: chip checking analysis phase and chip volume production test phase.The task of chip checking analysis phase is to utilize test vector checking designer whether the expectation of chip is obtained embodying in chip.Simultaneously, also to classify and qualitative analysis to the inefficacy of chip, collect a large amount of failure analysis data, the basis that these data one can be optimized as testing process, the reference that two can feed back to the physical Design personnel when developing as redaction about chip.Physical Design personnel can adjust the design of domain according to the data of actual measurement, to optimize direct current and alternating-current parameter.
| Test | I 1 | I 2 | I 3 | I 4 | … | I i | … | I n |
| D 1 | F 11 | F 12 | F 13 | F 14 | … | F 1i | … | F 1n |
| D 2 | F 21 | F 22 | F 23 | F 24 | … | F 2i | … | F 2n |
| D 3 | F 31 | F 32 | F 33 | F 34 | … | F 3i | … | F 3n |
| D 4 | F 41 | F 42 | F 43 | F 44 | … | F 4i | … | F 4n |
| … | … | … | … | … | … | … | … | … |
| D i | F i1 | F i2 | F i3 | F i4 | … | F ii | … | F in |
| … | … | … | … | … | … | … | … | … |
| D n | F n1 | F n2 | F n3 | F m4 | … | F ni | … | F nn |
Chip is in check analysis, and testing apparatus need operate under " testing up to all items " pattern.All all test items can have been estimated for each chip like this, each chip just has a complete record.Suppose to have in the testing process n test event, these test events are: I
1, I
2..., I
nTesting process FLOW is an ordered set of test event, FLOW={I
1, I
2..., I
n.The set of m chip failing to be measured is: D={D
1, D
2, D
3..., D
m, the test duration that obtains each chip failing according to testing process FLOW is: T={T
D1, T
D2, T
D3..., T
Dn.Can obtain the failure analysis data of chip after the failure analysis, the data layout that draws from testing apparatus is generally by/failure testing information table.In this table, each row is represented an ineffective part, and each row is represented a test event.F
IjIt is the value that i is capable and j is listed as in the form.The page up form has been introduced one and has been passed through/failure testing information table example.F
IjRepresent the test result of i ineffective part for j test event.F
IjValue has two, and { 0, if 1} is F
Ij=1, represent that then i device can not pass through j test event test, otherwise, F
Ij=0, then represent i device can pass through j test event.
The failure analysis of front can help to know that those test vectors are effectively for the physical fault of chip, thereby guiding removes to select test vector.The data that failure analysis simultaneously draws can also help us to optimize testing process, thereby reduce the discovery time of chip failing.Testing process optimization at first needs its flow process is divided, and testing process is divided into several fine-grained test events.Each test event is the set of the vector of some similar performances.Define some notions at test event:
Definition 1: " coefficient of efficiency " Y (I) of test event I, wherein the chip failing number of samples that can find of Y (I)=test event I;
Definition 2: " feature coefficient of efficiency " E (I) of test event I, wherein the chip failing number of E (I)=have only test event I to find;
The present invention will propose a kind of new data structure one test event validity table.Suppose that a testing process Flow is a set that is made of as element n test event, Flow=＜I
1, I
2..., I
i..., I
N-1, I
n, test event is effectively shown as described below
In this table, each row and each row are all represented a test event, wherein, and Y (I
i, I
j) expression test event I
i, I
jAll detectable chip failing number of samples.Obviously, Y (I
i, I
i) be exactly test event I
iFeature coefficient of efficiency E (I
i), these are worth at last figure, mark with the shade grid.Certainly, for test event optimization, the test duration also is the factor that needs are considered, the test duration can be by a simple list storage.
| Test event | I 1 | I 2 | … | I i | … | I n-1 | I n |
| Expend time in | T(I 1) | T(I 2) | T(I 1) | T(I n-1) | T(I n) |
Compare test project validity table and by contained information in the/failure testing information table uses a simple script just passing through of obtaining from the testing apparatus collection/failure testing information table can be converted to the basis one test event validity table of the optimization method that proposes the present invention as can be seen.
In order to reduce the test duration of chip failing, need to consider the problem of two aspects: the coefficient of efficiency and the test event of test event expend time in.In " background technology " partial content of present disclosure, illustrated because the dynamic programming algorithm complexity is too big, be not suitable for being applied in the optimization of SOC testing process.Actual test needs a kind of efficient higher and optimize effect sort method preferably.In order to sort to testing process in polynomial time, the present invention adopts a kind of sort method based on heuristic information." efficiency factor " F (I) of definition test event I is:
Efficiency factor F (I)=Y (I)/T (I)
Wherein, Y (I) is the coefficient of efficiency of test event I, the test duration that T (I) expends for test event I.
F (I) is a parameter of taking into account test validity and test duration according to defining as can be seen.For a test event I, F (I) is bigger, illustrates that the efficient of this project discovery chip failing is high more.The efficiency factor of selecting test event is as heuristic search information, can help us to obtain local optimum solution, for whole testing process global optimization,, can find the approximate solution of relatively optimizing though utilize this heuristic search information not necessarily can find optimum solution.
Description of drawings
Fig. 1 is the sort method based on the test event efficiency factor that the present invention proposes.
Fig. 2 is the performing step block diagram of testing process optimization method of the present invention in the volume production test.
Content of the present invention has promptly provided a kind of test event sort method based on the test event efficiency factor.As described in the accompanying drawing 1, have following several steps its its concrete composition based on the sort method of test event efficiency factor:
Input: test event validity table and test event time consumption table;
Output: the testing process OPTIMIZED_FLOW after the optimization, test event is arranged in order among the OPTIMIZED_FLOW;
Step S1: beginning.Before using this method, need set up test event validity table according to previously described method.The validity situation that has comprised each test event in this table.Simultaneously, another precondition of this method is the test event timetable, and this table method for building up preamble is described.
Step S2: effectively choose a test event, the testing efficiency maximum of this project the table from test event.On the basis of test event validity table and test event timetable, can calculate the efficiency factor of all items according to the efficiency factor computing formula.Therefrom select the project of an efficiency factor maximum.
Step S3: test event selected among the step S2 is added optimization back flow process OPTIMIZED_FLOW.Under initial situation, OPTIMIZED_FLOW is an empty set.The project that adds among the OPTIMIZED_FLOW is to arrange according to the sequencing that adds.
Step S4: the row and column of the selected project representative of deletion step S2 from test event validity table.
Step S5: refresh test project validity table, recomputate in the test event validity value of surplus test event still.Because step S3 deletes the test event table, the last column " validity " in the effective table of test event need recomputate.
Step S6: judge whether all test events all join among the OPTIMIZED_FLOW.If do not add fully, then jump to step S2; If add fully, then jump to step S7.
Step S7: finish.
The output of method is one and has optimized flow process OPTIMIZED_FLOW through the test event after the ordering optimization.
Describe the sort method that accompanying drawing 1 is proposed in detail with an example below.
If in once testing, the sample of 5 prints as failure analysis arranged.From failure analysis, obtain pass through/the failure testing information table is:
| Test | I 1 | I 2 | I 3 | I 4 | I 5 | I 6 | I 7 |
| D 1 | 1 | 0 | 1 | 1 | 1 | 0 | 1 |
| D 2 | 1 | 1 | 0 | 0 | 0 | 1 | 1 |
| D 3 | 1 | 0 | 1 | 0 | 1 | 0 | 0 |
| D 4 | 1 | 1 | 1 | 1 | 1 | 1 | 1 |
| D 5 | 1 | 0 | 0 | 0 | 0 | 0 | 0 |
Simple analysis should be shown as can be seen test event I
1Be one to the relatively effective test event of chip failing sample, as long as this project of use just can judge that all chips lost efficacy.Can be easy to obtain test event validity table from this table:
| Test event | I 1 | I 2 | I 3 | I 4 | I 5 | I 6 | I 7 |
| I 1 | 1 | 2 | 3 | 2 | 3 | 2 | 3 |
| I 2 | 2 | 0 | 1 | 1 | 1 | 2 | 2 |
| I 3 | 3 | 1 | 0 | 2 | 3 | 1 | 2 |
| I 4 | 2 | 1 | 2 | 0 | 2 | 1 | 2 |
| I 5 | 3 | 1 | 3 | 2 | 0 | 1 | 2 |
| I 6 | 2 | 2 | 1 | 1 | 1 | 0 | 2 |
| I 7 | 3 | 2 | 2 | 2 | 2 | 2 | 0 |
| Validity | 16 | 9 | 12 | 10 | 12 | 9 | 13 |
| Test event | I 1 | I 2 | I 3 | I 4 | I 5 | I 6 | I 7 |
| Expend time in | 0.55 second | 1.34 second | 0.57 second | 0.58 second | 1.02 second | 0.63 second | 0.89 second |
Having obtained just can using behind the test event validity table the heuristic sort method that the present invention proposes is optimized.
For the first time carry out sort method: the method first step at first sorts according to efficiency factor to test event, obtains { I
1(29.09), I
3(21.05), I
4(17.24), I
7(14.61), I
6(14.29), I
2(6.72) }, I wherein
1(29.09) expression test event I
1Efficiency factor be 29.09.Choose I with maximal efficiency coefficient
1, add new technological process OPTIMIZED_FLOW={I
1.In second and third step of method, in test event validity table, delete I
1Row and I
1Row, and refresh test validity table gets:
Carry out for the first time the sort method result
| Test event | I 2 | I 3 | I 4 | I 5 | I 6 | I 7 |
| I 2 | 0 | 1 | 1 | 1 | 2 | 2 |
| I 3 | 1 | 0 | 2 | 3 | 1 | 2 |
| I 4 | 1 | 2 | 0 | 2 | 1 | 2 |
| I 5 | 1 | 3 | 2 | 0 | 1 | 2 |
| I 6 | 2 | 1 | 1 | 1 | 0 | 2 |
| I 7 | 2 | 2 | 2 | 2 | 2 | 0 |
| Validity | 7 | 9 | 8 | 9 | 7 | 10 |
For the second time carry out sort method: the method first step at first sorts according to efficiency factor to test event and obtains: { I
3(15.29), I
4(13.79), I
7(11.24), I
6(11.11), I
2(5.22) }, choose I with maximal efficiency coefficient
3Add new technological process OPTIMIZED_FLOW={I
1, I
3.In second and third step of method, in test event validity table, delete I
3Row and I
3Row, and refresh test validity table gets:
Carry out for the second time the sort method result
| Test event | I 2 | I 4 | I 5 | I 6 | I 7 |
| I 2 | 0 | 1 | 1 | 2 | 2 |
| I 4 | 1 | 0 | 2 | 1 | 2 |
| I 5 | 1 | 2 | 0 | 1 | 2 |
| I 6 | 2 | 1 | 1 | 0 | 2 |
| I 7 | 2 | 2 | 2 | 2 | 0 |
| |
6 | 6 | 6 | 6 | 8 |
Carry out sort method for the third time: the method first step at first sorts according to efficiency factor to test event and obtains: { I
4(10.34), I
6(9.52), I
7(8.99), I
5(5.88), I
2(4.78) }, choose I with maximal efficiency coefficient
4Add new technological process OPTIMIZED_FLOW={I
1, I
3, I
4.In second and third step of method, in test event validity table, delete I
4Row and I
4Row, and refresh test validity table gets:
Carry out the sort method result for the third time
| Test event | I 2 | I 5 | I 6 | I 7 |
| I 2 | 0 | 1 | 2 | 2 |
| I 5 | 1 | 0 | 1 | 2 |
| I 6 | 2 | 1 | 0 | 2 |
| I 7 | 2 | 2 | 2 | 0 |
| |
5 | 4 | 5 | 6 |
Carry out sort method the 4th time: the method first step at first sorts according to efficiency factor to test event and obtains: { I
6(7.94), I
7(6.74), I
2(3.92), I
5(3.92) }, choose I with maximal efficiency coefficient
6Add new technological process OPTIMIZED_FLOW={I
1, I
3, I
4, I
6.In second and third step of method, in test event validity table, delete I
6Row and I
6Row, and refresh test validity table:
Carry out the sort method result the 4th time
| Test event | I 2 | I 5 | I 7 |
| I 2 | 0 | 1 | 2 |
| I 5 | 1 | 0 | 2 |
| I 7 | 2 | 2 | 0 |
| |
3 | 3 | 4 |
Carry out sort method the 5th time: the method first step at first sorts according to efficiency factor to test event and obtains: { I
7(4.49), I
5(2.94), I
2(2.23) }, choose I with maximal efficiency coefficient
7Add new technological process OPTIMIZED_FLOW={I
1, I
3, I
4, I
6, I
7.In second and third step of method, in test event validity table, delete I
7Row and I
7Row, and refresh test validity table:
Carry out the sort method result the 5th time
| Test event | I 2 | I 5 |
| I 2 | 0 | 1 |
| I5 | 1 | 0 |
| Validity | 1 | 1 |
Carry out sort method the 6th time: the method first step at first sorts according to efficiency factor to test event and obtains: { I
5(0.98), I
2(0.75) }, chooses I with maximal efficiency coefficient
5Add new technological process OPTIMIZED_FLOW={I
1, I
3, I
4, I
6, I
7, I
5.In second and third step of method, in test event validity table, delete I
5Row and I
5Row.After six suboptimization, only remaining I
2Therefore a test event does not need to calculate once more, directly with I
2Join the optimization flow process.Can get like this and optimize flow process to the end:
OPTIMIZED_FLOW＝{I
1，I
3，I
4，I
6，I
7，I
5，I
2}。
Sort method time complexity of the present invention is analyzed: describe as can be seen from method, main time complexity is at 2 points: test event and the refresh test project validity table of seeking testing efficiency coefficient maximum.In the k step of method, still surplus n-k test event during test event is effectively shown, the test event time complexity of seeking the maximal efficiency coefficient in these test events is n-k, the complexity of the project of refresh test simultaneously validity table is (n-k) * (n-k).With regard to the entire method implementation, the complexity that searching has the peaked test event of efficiency factor is:
The refresh test project effectively complexity of table is:
The time complexity of entire method is O (dn just like this
3).
The testing process optimization method that the present invention proposes reaches the purpose that reduces the chip failing test duration by the test event in the testing process is reordered.This optimization method need be in conjunction with the failure analysis of chip finished product Qualify Phase, the data that draw in the failure analysis of optimization method.
Fig. 2 has described optimization method more needed step block diagrams in the volume production test process that the present invention proposes.For a collection of volume production chip, use the optimization method that the present invention proposes, need two megastages of experience: the optimization before the failure analysis of Qualify Phase and the volume production test.This two megastage specifically needs the following several steps of experience:
Step S10: determine check analysis stage test vector and testing process.Select to determine check analysis stage test vector, and be divided into test event, form the testing process in check analysis stage according to these test events.The step that following several serials are specifically arranged:
A) collect the test vector that all need be verified.
B) according to the test purpose of these test vectors, the test vector with identical purpose summed up becomes a test event.
C) according to test event establishment testing process.Test event order and not really important in the testing process of Qualify Phase.
Step S20: test vector and testing process that applying step S10 determines carry out check analysis and obtain original passing through/failure testing information table chip.In the volume production chip, choose a suitable number of samples D, analyze at the testing process of this D sample chip applying step S10 appointment.The record analysis data, generally the data that obtain from testing apparatus with by/the failure testing information table is similar, can directly transform to obtain by/failure testing information table.
In this step, it should be noted that:
What a) sample size was chosen is moderate.Sample size very little, then sample does not have representativeness, sample size is too big, it is oversize then to collect the time that data need, and makes whole optimization process cycle lengthening.Use the experience of optimization method of the present invention according to the inventor in several chips, it is proper in general choosing 1000 chip failing analyses.
B) need be set to " testing " at Qualify Phase testing apparatus test pattern up to all items.
Step S30: call converse routine and will be converted into test event validity table by/failure testing information table.This converse routine can be the automatic conversion software according to these two form characteristics establishments.
Step S40: use sort method, test event is optimized, obtain the testing process of an optimization based on the testing efficiency coefficient.According to the test event validity table that step S30 obtains, the heuristic formula sort method based on the test event efficiency factor of using accompanying drawing 1 proposition then sorts to test event, just can obtain the test event flow process of an optimization after the optimization sorting.Last volume production is that the testing process after adopting this to sort is tested chip when testing.
The present invention is directed to that testing process has proposed a kind of new optimization method in the chip volume production test, the target of optimization method is the discovery fault that makes that testing apparatus can be as early as possible when the test failure chip, and superseded these chip failings, thereby reduce the actual test duration of chip failing, reduce testing cost.The basis of optimization method is a test event validity table, and test event validity table content comes from the failure analysis data of chip, and it has comprehensively expressed the coverage condition of test event to chip failing.Utilize this table and use test project efficiency coefficient heuristic search information, can in short time, find separating of relatively optimizing as optimization method.
Testing process optimization method of the present invention.By test event is reordered, reduced the test duration of chip failing.Based on the fail data of chip checking analysis phase, the present invention proposes a kind of test validity table and be used to store fail data, the fail data that directly obtains from testing apparatus and the conversion of test validity table are simple, are easy to automatic realization.Based on the test validity table, it is the sort method of heuristic search information with the test event efficiency factor that the present invention has proposed a kind of again.Owing to adopted the heuristic search sort method,, can in a short relatively time, provide separating of relatively optimizing though optimization method of the present invention not necessarily can provide optimum solution.The optimization method that the present invention proposes has simply, be easy to realize and characteristics that optimal speed is fast.Optimal speed makes the present invention be particularly suitable for being applied to the general all many situations of test event in the modern SOC test soon.
Claims (5)
1. an integrated circuit testing flow optimization method fast is characterized in that, collects the data of the chip failing that obtains by handling Qualify Phase, the test event in the testing process is sorted,
Specifically may further comprise the steps:
Step S10: determine check analysis stage test vector and testing process;
Step S20: test vector and testing process that applying step S10 determines carry out check analysis and obtain original passing through/failure testing information table chip;
Step S30: call converse routine and will be converted into test event validity table by/failure testing information table;
Step S40: use sort method, test event is optimized, obtain the testing process of an optimization based on the testing efficiency coefficient.
2. the flow optimization method of integrated circuit testing fast according to claim 1 is characterized in that, is made of a series of test events of finishing the fc-specific test FC task, and test event is arranged in order in the testing process.
3. the flow optimization method of integrated circuit testing fast according to claim 1 is characterized in that, definite check analysis stage test vector and testing process among the step S10, and its step is as follows:
A) collect the test vector that all need be verified;
B) according to the test purpose of these test vectors, the test vector with identical purpose summed up becomes a test event;
C) according to test event establishment testing process.
4. the flow optimization method of integrated circuit testing fast according to claim 1 is characterized in that, the test event validity table among the step S30, and based on the fail data of the chip failing in check analysis stage, it is concrete composed as follows described:
A) test event of each line display of test event validity table;
B) test event is shown in each tabulation of test event validity table;
C) i and j test event all detectable chip failing number in a chip failing sample are shown in capable, the j of test event validity table the i tabulation.
5. the flow optimization method of integrated circuit testing fast according to claim 1, it is characterized in that, sort method among the step S40 based on the testing efficiency coefficient, based on test event validity table and test event efficiency factor, its sort method is concrete composed as follows described:
Input: test event validity table and test event time consumption table;
Output: the testing process after the optimization, wherein test event is arranged in order;
Step S1: beginning;
Step S2: effectively choose a test event, the efficiency factor maximum of this project the table from test event;
Step S3: test event selected among the step S2 is added testing process;
Step S4: the row and column of from test event validity table, leaving out the selected project representative of step S2;
Step S5: refresh test project validity table, recomputate in the test event validity value of surplus test event still;
Step S6: judge whether all test events all add in the testing process,, then jump to step S2 if also do not add fully; If add fully, then jump to step S7;
Step S7: finish.
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| CN102262207A (en) * | 2010-05-27 | 2011-11-30 | 上海华虹Nec电子有限公司 | Method for rapidly judging test result of SOC (System-On-a-Chip) chip |
| US9310437B2 (en) * | 2011-03-25 | 2016-04-12 | Taiwan Semiconductor Manufacturing Company, Ltd. | Adaptive test sequence for testing integrated circuits |
| CN102707225A (en) * | 2012-06-21 | 2012-10-03 | 上海华岭集成电路技术股份有限公司 | Integrated circuit testing optimizing method and testing device thereof |
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| CN108594106A (en) * | 2018-04-12 | 2018-09-28 | 中国电子产品可靠性与环境试验研究所（（工业和信息化部电子第五研究所）（中国赛宝实验室）） | System level chip assessment device and method |
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| CN109725249A (en) * | 2019-01-31 | 2019-05-07 | 安庆师范大学 | A kind of testing process dynamic adjusting method and adjustment system |
| CN111220900A (en) * | 2020-03-02 | 2020-06-02 | 南京英锐创电子科技有限公司 | Chip scan chain test method and system |
| CN113257330B (en) * | 2021-06-23 | 2021-10-01 | 北京智芯半导体科技有限公司 | Test method and test device for power-down protection of storage device and storage medium |
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