JP2003344511A - Apparatus for optimizing number of cycles of test pattern - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the test coverage from lowering when a test pattern satisfying the restriction of the number of test cycles by a tester is selected by applying an existing test pattern to the test pattern for fabricating an LSI. <P>SOLUTION: The existing test pattern is divided into minimum units capable of simulation and simulation is performed by measuring toggle information concerning to a plurality of minimum test patterns. At a moment in time when a toggle rate obtained through merge of toggle information concerning to individual minimum test pattern reaches the toggle rate of the existing test pattern, the entire minimum test patterns are employed as a test pattern set. Alternatively, the existing test pattern is divided into minimum units capable of simulation, the toggle information is outputted every time when each of the plurality of minimum test patterns is simulated and a minimum test pattern becoming a pattern set is selected based on the toggle information concerning to the entire minimum test patterns thus obtained. <P>COPYRIGHT: (C)2004,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an apparatus for optimizing the cycle number of a test pattern used in a LSI manufacturing test.

[0002]

2. Description of the Related Art In an LSI manufacturing test, a test is performed in which input data to the LSI for operating the LSI and expected value data regarding output data from the LSI for test pass / fail judgment are time-series. An LSI manufacturing test is carried out by this tester by preparing it as a pattern and reading this test pattern into an LSI manufacturing test device called a tester.

In this case, the size of the test pattern that the tester can read, that is, the number of test cycles is limited by the memory capacity of the tester, and the number of test cycles of the test pattern must be kept within this constraint.

On the other hand, in the logic design stage of LSI,
Although a large number of logic verification test patterns are created, this logic verification test pattern may be used as an LSI manufacturing test pattern.

However, in such a case, the total number of test cycles of the logic verification test pattern often exceeds the limitation of the tester. Therefore, an LSI manufacturing test pattern set is obtained by selecting logic verification test patterns in which the total number of test cycles falls within the limit of the tester.

[0006]

However, when selecting the logic verification test pattern, there is a problem that the test coverage of the obtained LSI test pattern may be reduced depending on the selection method. is there. This decrease in test coverage means, for example, a decrease in the test range in which the test can be performed due to selection of test patterns for logic verification, and in short, a decrease in the extent to which the test can be covered. Therefore, it is necessary to select the logic verification test patterns in such a manner as not to reduce the test coverage, and to create an LSI manufacturing test pattern set.

The present invention has been made in view of the above, and when an existing test pattern is diverted to a manufacturing test pattern of an LSI and a test pattern satisfying the constraint of the number of test cycles by a tester is selected, a test is performed. It is an object of the present invention to provide a cycle number optimization device that does not reduce coverage.

[0008]

To achieve the above object, a test pattern cycle number optimizing apparatus according to the present invention includes a test pattern for creating a set of test patterns used in a test performed during semiconductor manufacturing. The optimizing device is characterized in that the test patterns that do not contribute to the toggle rate in the existing test patterns are removed.

According to the present invention, in order to divert an existing test pattern to an LSI manufacturing test pattern, the test coverage is lowered when the test pattern is selected by the tester so as to satisfy the constraint of the number of test cycles. Without this, the test pattern can be optimized.

In the test pattern cycle number optimization apparatus according to the next invention, in the above invention, the method of removing the test pattern that does not contribute to the toggle rate is to divide the existing test pattern into the smallest units that can be simulated, When the toggle rate obtained by merging the toggle information about the individual minimum test patterns reaches the toggle rate of the existing test pattern,
It is characterized in that all minimum test patterns until reaching are used as a test pattern set.

According to the present invention, existing test patterns can be selected and an optimum test pattern set can be obtained by merging toggle information so that the number of test cycles satisfies the constraint depending on the tester.

In the test pattern cycle number optimizing apparatus according to the next invention, in the above invention, when the existing test pattern is divided into the minimum simulatable units, each of the minimum test patterns is a test target. It is characterized in that a plurality of functional blocks included in a certain LSI are shared and divided so as to be biased toward a specific function and operated.

According to the present invention, an optimum test pattern set can be obtained because the minimum test pattern shares the test with each functional block.

In the test pattern cycle number optimizing apparatus according to the next invention, in the above invention, the execution order for simulating a plurality of minimum test patterns is LS.
It is characterized in that the test is performed from the minimum test pattern in which the test degree of a limited arbitrary functional block in the plurality of functional blocks included in I is high.

According to the present invention, the optimum test pattern set can be obtained by performing the simulation in the order of high test level.

In the test pattern cycle number optimizing apparatus according to the next invention, in the above invention, the method of removing the test pattern that does not contribute to the toggle rate is to divide the existing test pattern into the smallest units that can be simulated, It is characterized in that the toggle information is output each time the minimum test pattern of (1) is simulated, and the minimum test pattern to be a pattern set is selected based on the obtained toggle information about all the minimum test patterns.

According to the present invention, even if the toggle rate of the test pattern is not known in advance, the existing test pattern can be used as the manufacturing test pattern of the LSI. When selecting, the test pattern can be optimized without degrading the test coverage.

A test pattern cycle number optimizing apparatus according to the next invention, in the above invention, selects a minimum test pattern to be a pattern set based on the obtained toggle information about all the minimum test patterns. First, the smallest test pattern 1 having the largest number of toggle operating nodes is selected, and then the smallest test pattern in which the most non-toggling non-toggling nodes of the smallest test pattern 1 among the remaining other smallest test patterns are toggled. Select 2 and then among the other remaining minimum test patterns,
The operation of selecting the minimum test pattern 3 which has the most non-toggling non-toggling nodes of the minimum test pattern 1 and the minimum test pattern 2 is the node whose toggle operating node number is toggled by all the minimum test patterns. Characterized by repeating until a number is reached.

According to the present invention, by selecting the minimum test pattern with reference to the toggle operation node, the minimum test pattern can be efficiently obtained and the test pattern can be optimized.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Referring to FIGS.
A preferred embodiment according to the present invention will be described in detail.

First, the toggle rate is taken into consideration as a standard when selecting test patterns for logic verification. This toggle rate indicates the ratio of the number of logic element nodes that can be actually operated and activated among all the logic element nodes included in the LSI to be tested, and improves the quality of the test pattern. It is a guide.

Therefore, when selecting the logic verification test pattern, the toggle rate is not reduced. That is, by removing the test pattern that does not contribute to the acquisition of the toggle rate from the plurality of logic verification test patterns, an LSI that satisfies the constraint of the number of test cycles
It is necessary to create a test pattern set for manufacturing from the above.

Here, in order to remove the test pattern that does not contribute to the acquisition of the toggle rate, a plurality of logic verification test patterns are simulated in a simulation environment built on CAD, and the toggle of each logic verification test pattern is performed. Measure information. At this time, each time the toggle rate of each logic verification test pattern is calculated, it is merged with the toggle rate measured up to the previous time. The logic verification test pattern simulation and the toggle rates are merged until the toggle rate obtained by the merge reaches the known toggle rate of all the logic verification test patterns.
The simulation is terminated when the toggle rate obtained by the merge reaches the known toggle rate of all the logic verification test patterns, and the logic verification test pattern subjected to this simulation is used as the LSI manufacturing test pattern set. To do.

The minimum test pattern, which is the unit for performing the simulation at this time, may be the unit of the test pattern existing as the logic verification pattern.
These test patterns may be divided into smaller simulatable units. This minimum test pattern is obtained by dividing the existing test pattern in order to make the amount and time of simulation compact.
When the logic verification pattern is divided into smaller units, the smallest test patterns formed by division are LS.
In order to share the plurality of functions included in I as much as possible, in other words, to divide the tests so that the tests do not overlap with each other, only the specific functions are operated for efficiency.

Further, regarding the order of the minimum test patterns when performing the simulation, some of the plurality of functional blocks included in the LSI are tested by the minimum test pattern, and the plurality of functional blocks to be tested are tested. The simulation is performed in order from the smallest test pattern with the highest test degree (test coverage).
This improves the efficiency and reliability of the test.

If the toggle rate of all logic verification test patterns is not known in advance, all minimum test patterns are simulated once, and at this time, toggle operation information is calculated for each minimum test pattern simulation.
Get toggle inactivity information. The toggle operation information is a list of logic element nodes that have operated (activated or changed) at the logic element nodes included in the LSI to be tested, and the toggle non-operation information is a list of logic element nodes that have not operated. is there.

From the toggle operation information / toggle non-operation information, a simulation is performed again on a set of minimum test patterns that minimizes the number of test cycles while maintaining the toggle rate of all logic verification test patterns. Without calculation, the test pattern set for LSI manufacturing is used.

As the calculation method, toggle operation information
By examining the toggle non-operation information, the minimum test pattern with the maximum number of toggled (activated or changed) nodes is selected and set as the minimum test pattern 1.

Next, among the remaining other minimum test patterns, the toggle non-operation information is checked to select the minimum test pattern that causes the most non-toggling nodes in the minimum test pattern 1 to toggle. This is called minimum test pattern 2.

Next, from among the remaining other minimum test patterns, the minimum test pattern in which the most non-toggling nodes are toggled even if the minimum test pattern 1 and the minimum test pattern 2 are combined is selected and selected. Is the minimum test pattern 3.

Such an operation is repeated until the number of toggled nodes reaches the number of nodes toggled by all the minimum test patterns, and the set of the selected minimum test patterns at the time of reaching is used for the LSI manufacturing. Use as a test pattern set.

Embodiment 1. 1 is a conceptual diagram for creating a test pattern set that satisfies the constraint of the number of test cycles according to the first embodiment of the present invention.

In FIG. 1, the existing test pattern set 11 is composed of a total of N test patterns in units that can be simulated. This existing test pattern set 1
Although 1 may or may not be a test pattern for logic verification, it is a test pattern for logic verification here.

A toggle rate of 12 when the test target LSI is tested by the existing test pattern set 11
Is a known value.

The existing test pattern set 11 and the known toggle rate 12 of the existing test pattern set 11 are input to the contribution rate determining means 13 for the toggle rate, and even if they are deleted as a result of the determination, the toggle rate does not change. Information 14 on the existing test pattern is required.

The information 14 of the existing test pattern, which does not change the toggle rate even if it is deleted, is input to the test pattern selection / selection means 15, and the test pattern selection / selection means 15 uses this information to set the existing test pattern set. 1
1 is selected, and as a result, an LSI manufacturing test pattern set 16 is obtained.

FIG. 2 shows the contribution rate determining means 13 in FIG. 1 in more detail, and is a conceptual diagram for determining whether or not the test pattern contributes to the toggle rate. Each test pattern included in the existing test pattern set 11 is divided into test patterns of the minimum unit that can be simulated. In this example, the existing test pattern 1 is divided into an existing test pattern 1-1 and an existing test pattern 1-2. If further division is impossible, it is used as it is without being divided.

The divided existing test pattern set 21 is sent to the simulation control means 22 and the simulation is executed. That is, each test pattern is a test pattern simulation means 23.
At, the simulation is executed, and the toggle information 24 of the test pattern is measured each time.

The toggle information 24 of this test pattern is sent to the toggle information merging means 25 and merged with the toggle information relating to all the test patterns executed up to the previous time stored in the toggle information storage means 26 to be obtained. The toggle rates of all the test patterns executed up to now are sent to the simulation control means 22. At this time, the toggle information of the executed test pattern is sent to and stored in the toggle information storage means 26.

The simulation control means 22 checks whether or not the toggle rates of all the executed test patterns sent from the toggle information merging means 25 have reached the known toggle rate 12 of the existing test pattern set, and if yes. If so, the simulation is completed, and the existing test pattern information 14 in which the toggle rate remains unchanged even if the test patterns remaining in the divided existing test pattern set 21 that have not been executed yet are deleted.
To output.

If the toggle rate of all executed test patterns sent from the toggle information merging means 25 has not reached the known toggle rate 12 of the existing test pattern set, the simulation remaining in the divided existing test pattern set 21 is performed. For the unexecuted test pattern of
Continue the simulation.

FIG. 3 is a conceptual diagram showing a case where a test pattern is divided in order to obtain the divided existing test pattern set shown in FIG. The test pattern obtained as a result of division does not uniformly test a plurality of functional blocks included in the LSI, but operates so as to concentrate on a specific function as described above, that is, mainly tests only an arbitrary functional block. Split as you would.

In FIG. 3, the test pattern 31 is divided into a test pattern 32 and a test pattern 33. The test pattern 31 is a functional block A included in the LSI,
It is a test pattern for uniformly testing B and C, and the state is shown at 34. Here, the shade of shade represents the test degree.

The divided test pattern 32 is a test pattern for mainly testing the functional block A among the functional blocks A, B and C included in the LSI.
This is illustrated in 35. Further, the test pattern 33 after the division is the functional block A included in the LSI,
A test pattern for testing mainly the functional block B of B and C is shown in 36.

As described above, in the division of the test pattern, the test pattern obtained as a result of division does not uniformly test the plurality of functional blocks included in the LSI, but mainly divides the test into only arbitrary functional blocks. .

FIG. 4 is an explanatory diagram regarding the order of simulation in the simulation control means 22 shown in FIG. 2 when executing simulation of a plurality of test patterns. For example, four test patterns 41, 42,
43 and 44 exist, and the test levels 45, 46, 47 and 48 for the functional blocks A, B and C included in the LSI are illustrated.

The test pattern having the highest test degree among the four test patterns is the test pattern 41 having the test degree 90 for the functional block A and the test pattern 4 having the test degree 90 for the functional block B.
It is 2. If the test levels are the same, the test levels for other functional blocks are also checked. Then, in the test pattern 41, the test degree for the functional block B is 50.
In the test pattern 42, the test degree for the functional block A is 30. Therefore, the test pattern 41 has priority. As a result, the execution order 1 is the test pattern 41, and the execution order 2 is the test pattern 4
It is 2.

Next, the function block C has the highest test degree.
Is a test pattern 43 whose test degree is 80. Therefore, the execution order 3 is the test pattern 43. The execution order 4 is the remaining test pattern 44. In this way, the simulation execution order is determined. By adopting such an order, the tests can be covered.

Embodiment 2. FIG. 5 shows an example in which the toggle rates of all the logic verification test patterns are not known in advance. From the toggle information including the toggle rates of all the test patterns, the test patterns to be the test pattern set for LSI manufacturing are set. It is the conceptual diagram which showed deciding.

The existing test pattern set 11 is divided into the minimum simulation units and becomes the divided existing test pattern set 21. These test patterns are simulated control means 22 and simulation means 23.
To obtain the toggle information 24 of the test pattern.

The contents of the toggle information 24 are toggle operation information.
This is toggle non-operation information. The toggle operation information is a list of logic element nodes that have operated (activated or changed) at the logic element nodes included in the LSI to be tested as described above, and the toggle non-operation information is the logic elements that have not operated. It is a list of nodes.

The simulation is performed for all test patterns, and as a result, toggle information 51 for all test patterns is obtained. Toggle information 5 for all test patterns
1 is sent to the test pattern selection means 52, and a test pattern is selected from the toggle information 51 of all test patterns,
An LSI manufacturing test pattern set 16 is obtained.

FIG. 6 mainly shows the test pattern selecting means 52 shown in FIG. 5, which is used for determining a test pattern to be an LSI manufacturing test pattern set from toggle information about all the test patterns. It is a conceptual diagram of the selection method of.

Of the toggle information 51 for all test patterns shown in FIG. 5, the toggle information 61 for all test patterns 1 to N in FIG.
It has a list of toggle inactive nodes.

Based on these lists, the overall control means 6
2 starts the operation. The check target toggle non-operation node list holding unit 66 holds the node list that is the toggle non-operation among all the logic element nodes to be checked. In the initial state, the check target toggle non-operation node list is a merge of the toggle operation node lists of all test patterns.

The check target toggle non-operating node list is sent to the maximum test pattern selecting means 63 for toggle operating nodes in the check target node, and the test pattern 64 which toggles the most toggle target non-operating nodes to be checked is selected. Pick out.

The test pattern 64 is held by the test pattern holding means 67 and is sent to the check target toggle non-operation node list calculation means 65, the next check target toggle non-operation node list is calculated, and the check target toggle non-operation node is calculated. It is held by the node list holding means 66.

If the result of the check target toggle non-operation node list calculation means 65 is "none", that is, the state is equivalent to that the nodes of the toggle operation node list of all the test patterns operate, the overall control means 62 determines The operation is terminated, and the test pattern held in the test pattern holding means 67 is output as the LSI manufacturing test pattern set 16.

[0059]

As described above, according to the present invention, in the test pattern optimizing apparatus for creating a set of test patterns used in a test performed during semiconductor manufacturing, the toggle rate in the existing test patterns is set. By removing the test patterns that do not contribute to the test pattern, the test coverage is reduced when the test patterns are selected by the tester so that the existing test patterns can be reused as the manufacturing test patterns of the LSI. The test pattern can be optimized without any problem.

According to the next invention, in the method of removing the test pattern that does not contribute to the toggle rate, the existing test pattern is divided into the smallest units that can be simulated, and the toggle information regarding the plurality of smallest test patterns is measured to perform the simulation. When the toggle rate obtained by executing and merging toggle information about each minimum test pattern reaches the toggle rate of the existing test pattern, the test pattern set is made up of all the minimum test patterns until it reaches the test rate. By merging the toggle information so that the number of test cycles satisfies the constraint, the existing test patterns can be selected and the optimum test pattern set can be obtained.

According to the next invention, when the existing test pattern is divided into the smallest units that can be simulated, each of the smallest test patterns is shared by a plurality of functional blocks included in the LSI to be tested. By dividing so that only a specific function operates so as to be biased, the minimum test pattern allocates test blocks to each functional block, so that an optimum test pattern set can be obtained.

According to the next invention, the execution order for simulating the plurality of minimum test patterns is such that the smallest test pattern having a high test degree of a limited arbitrary functional block among the plurality of functional blocks included in the LSI is executed. The optimum test pattern set can be obtained by performing the simulation in the order of high test level.

According to the next invention, in the method of removing the test pattern that does not contribute to the toggle rate, the existing test pattern is divided into the smallest units that can be simulated, and the toggle information is obtained each time the plurality of smallest test patterns are simulated. Even if the toggle rate of the test pattern is not known in advance, the existing test pattern of the LSI can be output by selecting the minimum test pattern that becomes the pattern set based on the output toggle information about all the minimum test patterns. When the test pattern is selected by the tester so as to be used for the manufacturing test pattern, the test pattern can be optimized without lowering the test coverage.

According to the next invention, when selecting the minimum test pattern to be the pattern set based on the obtained toggle information about all the minimum test patterns, first, the minimum test pattern 1 having the maximum number of toggle operation nodes is selected. And then among the remaining other minimum test patterns,
Toggle non-operation of minimum test pattern 1 Selects the minimum test pattern 2 which toggles the most nodes, and then selects the minimum non-toggle non-toggle of the minimum test pattern 1 and the minimum test pattern 2 among the remaining other minimum test patterns. By repeating the operation of selecting the minimum test pattern 3 that toggles the most operation nodes until the number of toggle operation nodes reaches the number of nodes that are toggled by all the minimum test patterns, the toggle operation nodes are selected. By selecting the minimum test pattern as a reference, the minimum test pattern can be efficiently obtained and the test pattern can be optimized.

[Brief description of drawings]

FIG. 1 is an operation conceptual diagram of deleting a test pattern that does not contribute to a toggle rate.

FIG. 2 is a conceptual diagram of an operation for determining contribution to a toggle rate.

FIG. 3 is a conceptual diagram of test pattern division.

FIG. 4 is a conceptual diagram of determining a simulation order.

FIG. 5 is a conceptual diagram for obtaining a test pattern set from toggle information of all test patterns.

FIG. 6 is an operation concept diagram for selecting a test pattern from toggle information of all test patterns.

[Explanation of symbols]

11 existing test pattern set, 12 known toggle rate of existing test pattern set, 13 contribution determination means to toggle rate, 14 existing test pattern information whose toggle rate does not change even if deleted, 15 test pattern selection / selection means, 16 LSI manufacturing test pattern set, 21
Divided existing test pattern set, 22 simulation control means, 23 test pattern simulation means, 24 test pattern toggle information, 25
Toggle information merge means, 26 toggle information storage means, 51 all test pattern toggle information, 52 test pattern selection means, 61 all test pattern toggle information, 62 overall control means, 63 total number of toggle operation nodes in the check target node Test pattern selection means, 64 selected test patterns, 65 check target toggle non-operation node list calculation means, 66 check target toggle non-operation node list holding means, 67 test pattern holding means.

Claims (6)

[Claims] 1. A test pattern optimizing apparatus that creates a test pattern set such that a test pattern used in a test performed during semiconductor manufacturing has a test cycle number satisfying a constraint depending on a tester. An apparatus for optimizing the cycle number of a test pattern, which removes a test pattern that does not contribute to the toggle rate. 2. A method of removing a test pattern that does not contribute to a toggle rate is to divide an existing test pattern into minimum simulatable units, measure toggle information about a plurality of minimum test patterns, execute simulation, and 2. The test pattern set according to claim 1, wherein when the toggle rate obtained by merging toggle information about the minimum test pattern reaches the toggle rate of the existing test pattern, all the minimum test patterns up to the toggle rate are set as the test pattern set. Test pattern cycle number optimization device. 3. When dividing an existing test pattern into minimum simulatable units, each of the minimum test patterns takes charge of a plurality of functional blocks included in an LSI to be tested and is assigned to a specific function. The device is divided so that it is operated in a biased manner.
The test pattern cycle number optimization device described in. 4. The execution order of simulating a plurality of minimum test patterns is performed from a minimum test pattern with a high test degree of a limited arbitrary functional block among a plurality of functional blocks included in an LSI. 2. The test pattern cycle number optimization device according to 2. 5. A method of removing a test pattern that does not contribute to a toggle rate is obtained by dividing an existing test pattern into minimum simulatable units and outputting toggle information each time a plurality of minimum test patterns are simulated. 2. The test pattern cycle number optimizing apparatus according to claim 1, wherein a minimum test pattern to be a pattern set is selected based on toggle information about all the minimum test patterns. 6. When selecting a minimum test pattern to be a pattern set based on the obtained toggle information about all minimum test patterns, first select the minimum test pattern 1 having the maximum number of toggle operation nodes, and then select Of the remaining other minimum test patterns, the smallest test pattern 2 that causes the most non-toggling toggle nodes of the smallest test pattern 1 to toggle is selected, and then among the remaining other smallest test patterns, the smallest Toggle the test pattern 1 and the minimum test pattern 2 to select the minimum test pattern 3 that toggles the most non-operating nodes.
6. The test pattern cycle number optimizing apparatus according to claim 5, wherein the operation is repeated until the number of toggle operation nodes reaches the number of nodes to be toggled by all the minimum test patterns.