CN113114246B

CN113114246B - High-precision micro-current linear calibration circuit

Info

Publication number: CN113114246B
Application number: CN202110387301.4A
Authority: CN
Inventors: 魏娟; 杨平; 杜金苹; 张靖; 齐旭; 岑远军
Original assignee: Chengdu Hua Microelectronics Technology Co ltd
Current assignee: Chengdu Hua Microelectronics Technology Co ltd
Priority date: 2021-04-09
Filing date: 2021-04-09
Publication date: 2023-05-30
Anticipated expiration: 2041-04-09
Also published as: CN113114246A

Abstract

The invention relates to a high-precision micro-current linear calibration circuit, which relates to the integrated circuit technology, and comprises a DAC circuit with an R-2R resistor network and a calibration circuit, wherein the calibration circuit comprises X calibration units, each calibration unit comprises a bidirectional transmission gate, a calibration current injection branch and a calibration current extraction branch, the calibration current injection branch and the calibration current extraction branch are connected to a first current end of the bidirectional transmission gate, and the calibration current injection branch and the calibration current extraction branch are both proportional shunt circuits; the control end of the bidirectional transmission gate is connected with the digital code input end of the DAC circuit, and the second current end of the bidirectional transmission gate is connected with a trimming tap point in the DAC circuit; in the DAC circuit, the tap point is arranged at the 1/N resistance value of the trimming resistor arm, and X is a preset value and equal to the trimming resistor arm in number. The invention has simple structure, obvious effect and high reliability.

Description

High-precision micro-current linear calibration circuit

Technical Field

The present invention relates to integrated circuit technology.

Background

The digital-to-analog converter is a key component for converting digital signals into analog signals, is an interface of an analog system and a digital system, is widely applied to the fields of radars, spectrum analyzers, aerospace, electronic countermeasure, high-speed imaging and the like, belongs to a high-performance chip, and has important significance for modernization of national defense weaponry in China in research and development design. The DAC is used as a conversion bridge from a digital domain to an analog domain, directly determines the accuracy of external data processing, and provides key and timely information for a control system. With the increasing performance of systems, the need for high precision DACs is increasing.

Because the high-precision DAC is limited by a process, the natural matching precision of the resistor is only about 10 bits, so that the DAC with more than 12 bits is usually required to be trimmed and calibrated in linearity, the resistor string DAC has process deviation in the production process, a chip can bear certain mechanical stress and even deform in post-process processing such as packaging patch and bonding, the risk of resistor mismatch exists in the DAC, and the mismatch of the resistor itself can generate differential nonlinearity and integral nonlinearity errors. To meet the accuracy requirements of the DAC, the chip must be trimmed.

The current main stream DAC products applied to industrial control are not high in design precision requirement due to larger output range or not high in trimming precision requirement on trimming position, and the influence of the small current errors in the calibration circuit on the overall trimming precision is not great; however, if the output range of the product is small and the conversion accuracy truly reaches 16 bits or more, the design of the minute current in the calibration circuit and the accuracy design of trimming become difficult. Most of the disclosed calibration techniques are digital calibration, and have large circuit scale and large area consumption.

Disclosure of Invention

The technical scheme adopted by the invention for solving the technical problems is that the calibration circuit realized by the analog circuit is provided, and the calibration circuit has the characteristics of small scale, easiness in realization and high reliability.

The technical proposal adopted by the invention for solving the technical problems is that the high-precision micro-current linear calibration circuit comprises a DAC circuit with an R-2R resistor network and a calibration circuit, and is characterized in that,

the calibration circuit comprises X calibration units, each calibration unit comprises a bidirectional transmission gate, a calibration current injection branch and a calibration current extraction branch, the calibration current injection branch and the calibration current extraction branch are connected to a first current end of the bidirectional transmission gate, and the calibration current injection branch and the calibration current extraction branch are both proportional shunt circuits and are used for shunting current passing through an external connection end;

the control end of the bidirectional transmission gate is connected with the digital code input end of the DAC circuit, and the second current end of the bidirectional transmission gate is connected with a trimming tap point in the DAC circuit;

in the DAC circuit, the tap point is arranged at the 1/N resistance value of the trimming resistor arm, namely, the resistance value between the tap point and the output end of the resistor network is (N-1) times of the resistance value between the tap point and the MOS connection point, and N is a preset integer;

and X is a preset numerical value and is equal to the number of trimming resistor arms.

The trimming resistor arm is a high-order converting resistor arm at a preset position.

The invention solves the problem of accurate trimming of tiny steps, realizes the design of a high-precision linear calibration circuit, can be widely applied to various linear calibration circuits, has simple structure, obvious effect and high reliability, and provides an effective method for trimming the linear errors of the subsequent high-precision low-voltage domain.

Drawings

FIG. 1 is a schematic diagram of an R-2R resistor ladder network.

Fig. 2 is a schematic diagram of a trimming point implementation of a prior art DAC network.

Fig. 3 is a schematic structural view of the present invention.

Fig. 4 is a schematic diagram of an implementation of a prior art resistive damping network.

FIG. 5 is a schematic diagram of a trimming resistor attenuation network implementation of the present invention. In fig. 5, a is a schematic diagram of a calibration unit connected to BIT12, b is a schematic diagram of a calibration unit connected to BIT13, c is a schematic diagram of a calibration unit connected to BIT14, d is a schematic diagram of a calibration unit connected to BIT15, and e is a schematic diagram of a calibration unit connected to BIT 16.

FIG. 6 is a diagram illustrating the step voltage trimming values of the highest data bits.

FIG. 7 is a schematic diagram of trimming accuracy of each data bit without synchronization.

Detailed Description

The invention realizes trimming of the weight current by a precise trimming technology of tiny current stepping, the weight trimming current is sent into an R-2R resistor ladder network of a DAC circuit (hereinafter referred to as DAC core) and enters an internal trimming point, thereby realizing the conversion from trimming current to trimming voltage. The invention is characterized in that:

firstly, amplifying the minimum trimming current under the unit step trimming voltage by flexibly designing the position of a calibration point, so as to improve the bias precision of the trimming current and the trimming accuracy;

secondly, independently designing a resistance attenuation network of each trimming bit so as to flexibly process the attenuation proportion and the unit resistance value of the attenuation network; the design of the gating switch is flexibly added on the attenuation network, so that the influence of the calibration network on the accuracy of the DAC in the non-trimming mode is solved; by skillfully designing the trimming points in the DAC and the resistor network structure in the calibration circuit, the influence of the quiescent current of the attenuation resistor network in the trimming mode on the trimming current is effectively solved.

The invention adds a flexible design suitable for high-precision trimming on the basis of the conventional mature trimming circuit, and the invention is explained in the circuit design as follows, unlike the calibration circuit structure in the conventional mature project:

firstly, on the trimming point position, the trimming points of the previous project are directly connected with the output end of the DAC, and the trimming point of the design directly trims the weight current on the resistor network node according to the trimming weight bit, and the unit stepping trimming current can be amplified by the flexible calibration mode, so that the trimming current precision is improved; assuming that one LSB current of the 16-bit DAC is 5nA, the current is too small, the leakage current of the trimming bias circuit reaches the nA level, accurate mirroring cannot be performed, and one LSB current is required to be amplified, so N trimming points are considered to be generated on a weight node of an R-2R network, if the LSB current is to be amplified by N times, the resistor on a resistor arm in the R-2R network is required to be divided into N sections, and the trimming point is taken from the resistor node closest to a conducting switch, so that the current for trimming one LSB is amplified to be N5 nA, and the bias accuracy of the trimming current can be greatly improved.

And secondly, each trimming bit adopts an independent resistance attenuation network structure so as to flexibly process attenuation multiples and the maximum trimming current capacity of each trimming bit. The flexible design of the attenuation network solves two key problems: firstly, the influence of the static current in the calibration circuit on the accuracy of DAC output in the non-trimming mode is solved. In the invention, when trimming position 1 and corresponding control fuse is set to 0, the output trimming current of the attenuation network can be connected to the trimming point of the DA core, otherwise, the on switch is turned offIn the state, the static current of the calibration circuit does not influence the normal output of the DAC, and the reliability of the design is improved. Secondly, the influence of the quiescent current of the attenuation resistor network in the calibration circuit on the trimming current in the trimming mode is solved. The invention skillfully designs the internal trimming point of the DAC and the attenuation resistor network structure in the calibration circuit, the position of the tap of the internal trimming point of the DAC is selected to be close to the reference voltage, and the reference voltage value processed by the DAC in the invention is

The calibrated trimming current is set at the midpoint of the attenuation resistor string, and the partial pressure of the middle point is +.>

The voltage of the trimming tap is basically consistent with the voltage of the trimming tap in the DAC, so that the balance of a static working point is well realized, the influence of static current on trimming current is reduced to the maximum extent, and the trimming current error is reduced. Finally, three design contradiction points of signal establishment time, trimming current precision and current capacity are effectively balanced by reasonably setting resistance values in an attenuation network.

Examples

Taking a trimming 16-bit voltage type DAC as an example, the following is described in detail:

the DAC core adopts a typical R-2R ladder resistor network structure, and as shown in figure 1, the upper 5 bits of the DA core are trimmed in the embodiment.

Fig. 2 is a trim point implementation of a conventional DAC network, with the output of the trim calibration circuit acting directly on the output of the DAC. In the present embodiment, assuming that the unit resistance of the resistor network is R, the equivalent resistance of the output is

Since the reference voltage VREF is halved and fed into the DA core in this embodiment, the DAC output fullness value is +.>

Thus the unit step trimming current +.>

Under the condition of lower reference voltage VREF, higher DAC precision and larger unit resistance, the unit step trimming current is only a few nA, and the current is too small, and the accurate mirror image cannot be realized by the existing technology, so that the correct trimming cannot be realized.

Fig. 3 is a schematic diagram of a trimming point implementation manner of the present invention, in which a trimming point of each trimming bit is independently led out by a trimming calibration circuit and is respectively connected to a resistor arm tap corresponding to each trimming bit in a DAC core, and a position of the tap point can be determined according to a magnification factor of a unit step trimming current. According to the process design experience, the stepping current is in the order of hundreds nA, and the bias current source can realize accurate mirror image, so the invention can divide the resistance of the resistance arm into N sections, for example, the resistance value of the resistance tap at the position closest to the reference (the connecting point of the MOS tube in the figure) is reduced to 1/N of the original resistance, the current required by synchronous voltage feeding during trimming is increased to the original N times, and the tiny nA current can be flexibly increased to hundreds nA, thereby greatly increasing the unit stepping trimming current value, improving the mirror image precision of the micro-current bias circuit and increasing the tolerance of mirror image mismatch.

FIG. 4 is a schematic diagram of a conventional implementation of a resistor attenuation network in a trimming calibration circuit, which is typically an R-2R resistor network structure when seen from node A to the left, wherein the trimming currents for the respective weight BITs are sequentially poured from node A, B, C, D, E from high to low, and if the contribution of the weighting current Iin_bit16 of BIT16 to the point A at the output end of the R-2R resistor network is I, the contribution of the weighting currents for the respective BITs of BIT15, BIT14, BIT13 and BIT12 to the point A can be obtained by using an equivalent circuit method

The trimming current proportion of each weight bit accords with the current contribution of the corresponding weight bit in the DA kernel. The attenuation network is seen from the right side of the A node, the weight current of the A node is attenuated correspondingly according to the resistance proportion, the equivalent resistance is R seen from the left side of the A node, the resistance seen from the right side of the A node is (M-1) R,the final weighted trimming current output of i_cal_out is 1/M I, M being the amplification factor of the microcurrent bias circuit. In this implementation, if an accurate attenuation ratio is to be achieved, the output terminal of i_cal_out must be grounded to the virtual ground potential, so the network is only suitable for current output mode DACs, and for voltage output DACs, constant grounding of the output terminal of i_cal_out cannot be achieved; secondly, the structure is not suitable for trimming of bidirectional current, only one-way trimming of current filling can be met, and for the condition of current pulling, the attenuation resistor network cannot be realized; finally, the output of the resistor attenuation network is directly connected with the output end of the DAC, so that the static current attenuated by the resistor attenuation network in the non-trimming mode flows into the DA core, and the normal conversion precision of the DAC is affected.

FIG. 5 is a schematic diagram of an implementation of an improved trimming resistor attenuation network, in which each BIT of weight trimming current is attenuated by an independent resistor attenuation network, and the attenuation ratios of BIT12, BIT13, BIT14, BIT15 and BIT16 are all attenuated according to 1/M. In order to realize bidirectional trimming and ensure accurate current attenuation proportion, the invention skillfully and flexibly adopts a bidirectional resistor network with a middle tap. When the trimming direction is the current, the trimming current I_CAL_BIT is fed through the upper group of attenuation networks to VREF, and the current is attenuated according to the corresponding proportion and then is output to the trimming point corresponding to the DA check according to the node current method, so that bidirectional trimming is realized. The design of the bidirectional resistance network with the middle tap also skillfully solves the influence of the quiescent current of the attenuation resistance network in the correction circuit on the trimming current during trimming, thereby achieving two purposes. In order to avoid the influence of the static current in the calibration circuit on the DAC output in the non-trimming mode, the calibration output end of the attenuation resistor network is provided with a complementary switch, and the control signal of the switch is generated by the trimming fuse control end and the corresponding trimming weight bit through combinational logic; when the weight trimming position 1 and any control fuse corresponding to the trimming position is set to 0, the complementary switch is turned on, the trimming point of the DA core can be accessed by the calibration current, otherwise, the complementary switch is in an off state, and the static current of the calibration circuit cannot flow into the DA core to influence the normal output of the DAC. Through the design of the switch in the attenuation resistor network, the DAC can be ensured to output correctly no matter in the starting or non-starting state of the calibration circuit. In actual design, the resistance value R in each resistance attenuation network can be specifically set by combining calculation and simulation, so that three design points of signal establishment time of trimming current, trimming current precision and attenuation resistance network perfusion capability are effectively balanced.

The invention realizes the high-precision micro-current linear trimming and calibrating. The linearity of the whole DAC system is determined by the high-order bits, so that the linearity of the DAC system plays a crucial role in monotonicity, and fine trimming of the high-order bits as much as possible is beneficial to ensuring good linearity performance under the condition of allowing layout area. In this patent, to 16 BIT DAC, DNL fuse trimming circuit has been designed to high 5 BITs, the reference voltage of DA core is 2.5V, consequently, the trimming voltage of a LSB is 38uV, the little electric current step trimming scope of every weight current source design is different, from low order to high order trimming precision increase in proper order, the highest BIT16 trimming 2LSB, 4LSB, 8LSB, 16LSB, 32LSB totally 5 step ranges, can see that the trimming scope of BIT16 is the finest, so the design of little electric current source appears vital.

The high-precision micro-current linear trimming and calibrating technology of the invention well realizes the fine trimming and calibrating of the highest position. According to calculation, the step voltage of trimming 2LSB is minimum, the theoretical voltage is 76uV, the actual trimming value is 63.5uV, the error is only 17%, the trimming is finer than that in the conventional normal-pressure DAC, the data conversion precision close to 15 bits can be basically ensured, the design precision is further improved on the premise of meeting the actual requirements of projects, and the invention is a calibration circuit with highest precision realized by using an analog mode at present, and fully verifies the feasibility of the patent.

To further verify the accuracy of the stepping relationship between trimming bits, the trimming accuracy of the high five-bit digital code at different trimming steps was simulated, see fig. 6 and 7.

In the trimming calibration design, the minimum trimming precision can be guaranteed to be 11 BITs, so that the calculation is carried out from the low level to the high level of trimming, the BIT12 trimming voltage is 2LSB, the BIT13 trimming voltage is 4LSB, the BIT14 trimming voltage is 8LSB, the BIT15 trimming voltage is 16LSB, the BIT16 trimming voltage is 32LSB, and the simulation result shows that the stepping trimming voltage value between the data BITs from low level to high level is consistent with the designed trimming voltage, meets the design requirement, and verifies the feasibility of the patent.

In conclusion, the invention effectively solves the problem of tiny step trimming of the DAC under high-precision normal pressure. The trimming current under unit stepping is amplified through flexible design of the calibration points in the DAC core, so that the bias precision of the trimming current is improved, and the influence of the quiescent current of the attenuation resistor network under the trimming mode on the trimming current is skillfully solved through the structural design of the trimming point selection and attenuation network of the DAC. The attenuation proportion of the current and the unit resistance value of the attenuation network are flexibly processed through independent design of the resistance attenuation network on each trimming bit, so that three design contradiction points of signal establishment time, trimming current precision and current filling and pulling capability are effectively balanced, the flexible design of a gating switch is assisted on the resistance attenuation network, the influence of the calibration network on the precision of a DAC in a non-trimming mode is effectively solved, and the flexible design of the trimming points in the DAC effectively solves the influence of the quiescent current of the attenuation resistance network in the trimming mode on the trimming current by skillfully designing the trimming points in the DAC and the resistance network structure in the calibration circuit. The trimming and calibrating circuit scheme can be widely applied to DAC linearity trimming under normal pressure, high-precision linearization calibration can be realized through fine trimming and adjusting of micro current, and the circuit has the advantages of simple structure, obvious effect and high reliability, and an effective method is provided for the subsequent linearity calibration of a high-precision low-voltage domain.

Claims

1. The high-precision micro-current linear calibration circuit comprises a DAC circuit with an R-2R resistor network and a calibration circuit, and is characterized in that,

a tap point is arranged at a 1/N resistance value of the trimming resistor arm in the DAC circuit, the resistance value between the tap point and the output end of the resistor network is (N-1) times of the resistance value between the tap point and the MOS connection point, and N is a preset integer;

each tap point is connected with a calibration unit, each calibration unit comprises a bidirectional transmission gate, a calibration current injection branch and a calibration current extraction branch, the calibration current injection branch and the calibration current extraction branch are connected to a first current end of the bidirectional transmission gate, the calibration current injection branch and the calibration current extraction branch are proportional shunt circuits and are used for shunting current passing through an external connection end, and all the calibration units jointly form a calibration circuit;

when the trimming direction is the pulling current, trimming current I_CAL_BIT_N is fed through the calibration current leading-out branch to the attenuation network of AGND; when the trimming direction is the filling current, trimming current I_CAL_BIT is fed through an attenuation network from the calibration current injection branch to VREF;