CN113114215A - Level conversion circuit - Google Patents

Abstract

The invention relates to a level conversion circuit, which comprises a first amplifier, a second amplifier, a third amplifier, a forward input signal I NP, a reverse input signal I NN, a forward output signal OUTP and a reverse output signal OUTN, wherein the first amplifier is an amplifier with differential input and differential output, the second amplifier and the third amplifier are amplifiers with differential input and single-ended output, the first amplifier, the second amplifier and the third amplifier are powered by a power supply VDD, the forward input signal INP is connected to the positive input end of the first amplifier, and the reverse input signal I NN is connected to the negative input end of the first amplifier. The invention relates to a level conversion circuit which can be used for high-speed signal transmission.

Description

Level conversion circuit

Technical Field

The present invention relates to the field of integrated circuit technologies, and in particular, to a level shifter circuit.

Background

The multi-power supply voltage domain technology is widely applied to a system on chip (SoC), and each module in the system works under a proper power supply voltage according to the time sequence requirement. Generally, a module which is critical to a time sequence usually works under a higher power supply voltage so as to meet the speed performance index of a chip; modules with low timing requirements are generally operated at a lower power supply voltage to reduce the power consumption of the chip.

In a chip applying a multi-power-supply voltage domain technology, a level conversion circuit is an important module, and provides an interactive way for modules working under different voltage domains, so that the correct transmission of signals among the voltage domains is ensured. When the signal is converted from the high-voltage domain to the low-voltage domain, the ordinary buffer can be used for realizing the trans-voltage domain transmission of the signal; when a signal is converted from a low voltage domain to a high voltage domain, a more complex level shift circuit is required.

Conventional level shifting circuits include cross-coupled level shifting circuits and current mirror based level shifting circuits. As shown in fig. 1, in the cross-coupled level shift circuit, when the input signal a changes from low to high, the change from the input signal a to the output signal Y is delayed by three inverters (MP1/MN1, MP2/MN2, MP22/MN22) and the turn-on delay of MN 12; when the input signal A changes from high to low, the change from the input signal A to the output signal Y passes through two inverters (MP1/MN1, MP22/MN22) for delay, the conduction delay of MN11 and the conduction delay of MP12, and the delay of the inverter (MP2/MN2) is much smaller than the conduction delay of MP12, so that the rising delay of the output signal is much faster than the falling delay, the output duty ratio of the level conversion circuit is unreasonable, and the overall performance of the system on chip is restricted. As shown in fig. 2, in the level shift circuit based on the current mirror, as in the cross-coupled level shift circuit, the input/output signal rise delay and fall delay of the circuit are greatly mismatched, and the influence on the high-speed signal is large. In addition, in the two level conversion circuits, the rising delay and the falling delay of the level converter are large, and the conversion time of the level conversion circuit is long, so that the level conversion circuit is not suitable for a high-speed high-performance chip-on-chip system. There is a great need for a level conversion circuit for high-speed signal transmission.

Disclosure of Invention

The invention provides a level conversion circuit, which aims to solve the problems that the conversion time of the existing level conversion circuit is long and the system performance is restricted.

In order to solve the above technical problem, the present invention provides a level shift circuit, including a first amplifier, a second amplifier, a third amplifier, a forward input signal, an inverted input signal, a forward output signal, and an inverted output signal, wherein the first amplifier is an amplifier with differential input and differential output, the second amplifier and the third amplifier are amplifiers with differential input and single-ended output, the first amplifier, the second amplifier, and the third amplifier are powered by a power supply, the forward input signal is input to a positive input terminal of the first amplifier, the inverted input signal is input to a negative input terminal of the first amplifier, a positive output terminal of the first amplifier is connected to a positive input terminal of the second amplifier and a negative input terminal of the third amplifier, a negative output terminal of the first amplifier is connected to a negative input terminal of the second amplifier and a positive input terminal of the third amplifier, the output end of the second amplifier outputs the forward output signal, and the output end of the third amplifier outputs the reverse output signal.

Preferably, the first amplifier includes a second NMOS transistor, a third NMOS transistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, and a sixth PMOS transistor, the first PMOS transistor and the second NMOS transistor are connected in series between the power supply and the ground terminal, the second PMOS transistor and the third NMOS transistor are connected in series between the power supply and the ground terminal, the first PMOS transistor and the third PMOS transistor are connected in parallel between the power supply and the negative output terminal of the first amplifier, the second PMOS transistor and the sixth PMOS transistor are connected in parallel between the power supply and the positive output terminal of the first amplifier, wherein the first PMOS transistor and the second PMOS transistor are cross-coupled to form a positive feedback structure.

Preferably, the first amplifier further includes an enable node and a first NMOS transistor connected in series between the enable node and a ground terminal, the first PMOS transistor and the second NMOS transistor are connected in series between the power supply and the enable node, and the second PMOS transistor and the third NMOS transistor are connected in series between the power supply and the enable node.

Preferably, the source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor, and the source electrode of the sixth PMOS transistor are connected to the power supply, the drain electrode of the first PMOS transistor, the gate electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor, the gate electrode of the third PMOS transistor, and the drain electrode of the second NMOS transistor are connected to the negative output end of the first amplifier, the drain electrode of the second PMOS transistor, the gate electrode of the first PMOS transistor, the drain electrode of the sixth PMOS transistor, the gate electrode of the sixth PMOS transistor, and the drain electrode of the third NMOS transistor are connected to the positive output end of the first amplifier, the source electrode of the second NMOS transistor, the source electrode of the third NMOS transistor, and the drain electrode of the first NMOS transistor are connected to the enable node, and the source electrode of the first NMOS transistor is connected to the ground terminal; the grid electrode of the second NMOS tube receives the forward input signal, the grid electrode of the third NMOS tube receives the reverse input signal, and the grid electrode of the first NMOS tube receives an enabling signal.

Preferably, the second amplifier includes a seventh PMOS transistor, an eighth PMOS transistor, a sixth NMOS transistor, and a seventh NMOS transistor, the seventh PMOS transistor and the sixth NMOS transistor are connected in series between the power supply and the ground terminal, the eighth PMOS transistor and the seventh NMOS transistor are connected in series between the power supply and the ground terminal, the source of the seventh PMOS transistor is connected to the power supply, the gate of the seventh PMOS transistor is connected to the positive output terminal of the first amplifier, the source of the eighth PMOS transistor is connected to the power supply, the gate of the eighth PMOS transistor is connected to the negative output terminal of the first amplifier, and the drain of the eighth PMOS transistor and the drain of the seventh NMOS transistor are connected to the output terminal of the second amplifier.

Preferably, the gate and the drain of the sixth NMOS transistor are short-circuited, the source of the sixth NMOS transistor and the source of the seventh NMOS transistor are connected to the ground terminal, and the gate of the sixth NMOS transistor is connected to the gate of the seventh NMOS transistor.

Preferably, the third amplifier includes a fifth PMOS transistor, a fourth PMOS transistor, a fifth NMOS transistor, and a fourth NMOS transistor, the fifth PMOS transistor and the fifth NMOS transistor are connected in series between the power supply and the ground terminal, the fourth PMOS transistor and the fourth NMOS transistor are connected in series between the power supply and the ground terminal, the source of the fourth PMOS transistor is connected to the power supply, the gate of the fourth PMOS transistor is connected to the negative output terminal of the first amplifier, the source of the fifth PMOS transistor is connected to the power supply, the gate of the fifth PMOS transistor is connected to the positive output terminal of the first amplifier, and the drain of the fifth PMOS transistor and the drain of the fifth NMOS transistor are connected to the output terminal of the third amplifier.

Preferably, the drain and the gate of the fourth NMOS transistor are short-circuited, the source of the fourth NMOS transistor and the source of the fifth NMOS transistor are connected to the ground terminal, and the gate of the fourth NMOS transistor is connected to the gate of the fifth NMOS transistor.

Preferably, the gain of the first amplifier is about Av1 ═ gmn2/gmp3, the gain of the second amplifier is about Av2 ═ gmp8 ═ rop8| | ron7, the gain of the third amplifier is about Av3 ═ gmp 5| (rop5| | ron5), where gmn2, gmp3, gmp8, gmp5 are transconductance of the second NMOS transistor, third PMOS transistor, eighth PMOS transistor, and fifth PMOS transistor, respectively, and ron7, ron5, rop8, rop5 are small-signal resistance of the seventh NMOS transistor, fifth NMOS transistor, eighth PMOS transistor, and fifth PMOS transistor, respectively.

Preferably, the voltage gain of the two-stage amplifier of the level shift circuit may be expressed as Av1 Av2 Av1 Av3 gmn2 gmp8 (rop8 ron7)/gmp 3.

Compared with the prior art, the level conversion circuit has the beneficial effects that:

(1) the level switching circuit shapes the input low swing logic level, makes the jumping edge steep and phase-splitting uniform, and outputs the logic level by a VDD full swing signal;

(2) the level conversion circuit is completely symmetrical, and the output differential signal almost has no phase error;

(3) the level conversion circuit of the invention adopts a two-stage amplifier structure, provides higher gain and improves the speed of level conversion.

Drawings

FIG. 1 is a cross-coupled level shifting circuit of the prior art;

FIG. 2 is a prior art current mirror based level shifting circuit;

FIG. 3 is an overall block diagram of a level shift circuit of the present invention;

FIG. 4 is a basic circuit diagram of a level shift circuit of the present invention;

fig. 5 is a transient simulation waveform of example 1 of a level shift circuit of the present invention.

Detailed Description

To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present. When an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

Referring to fig. 3, an overall structure diagram of a level shift circuit according to the present invention includes a first amplifier a1, a second amplifier a2, a third amplifier A3, a forward input signal INP, an inverted input signal INN, a forward output signal OUTP, and an inverted output signal OUTN, the first amplifier a1 is an amplifier with differential input and differential output, the second amplifier a2 and the third amplifier A3 are amplifiers with differential input and single-ended output, and the first amplifier a1, the second amplifier a2, and the third amplifier A3 are powered by a power supply VDD. The positive input signal INP is input to the positive input terminal of the first amplifier a1, the negative input signal INN is input to the negative input terminal of the first amplifier a1, the positive output terminal of the first amplifier a1 is connected to the positive input terminal of the second amplifier a2 and the negative input terminal of the third amplifier A3, the negative output terminal of the first amplifier a1 is connected to the negative input terminal of the second amplifier a2 and the positive input terminal of the third amplifier A3, the positive output signal OUTP is output from the output terminal of the second amplifier a2, and the negative output signal OUTN is output from the output terminal of the third amplifier A3.

Referring to fig. 4, in a basic circuit diagram of a level shift circuit according to the present invention, a first amplifier a1 includes three NMOS transistors and four PMOS transistors, the three NMOS transistors are a first NMOS transistor MN1, a second NMOS transistor MN2 and a third NMOS transistor MN3, and the four PMOS transistors are a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3 and a sixth PMOS transistor MP 6. The first PMOS tube MP1 and the second NMOS tube MN2 are connected in series between the power supply VDD and a ground terminal GND, the second PMOS tube MP2 and the third NMOS tube MN3 are connected in series between the power supply VDD and the ground terminal GND, the first PMOS tube MP1 and the third PMOS tube MP3 are connected in parallel between the power supply VDD and a negative output end of the first amplifier, the second PMOS tube MP2 and the sixth PMOS tube MP6 are connected in parallel between the power supply VDD and a positive output end of the first amplifier, wherein the first PMOS tube MP1 and the second PMOS tube MP2 are in cross-coupling connection to form a positive feedback structure.

The first amplifier a1 further includes an enable node E1 and a first NMOS transistor MN1 connected in series between the enable node E1 and a ground terminal GND, the first PMOS transistor MP1 and a second NMOS transistor MN2 are connected in series between the power supply VDD and an enable node E1, and the second PMOS transistor MP2 and a third NMOS transistor MN3 are connected in series between the power supply VDD and an enable node E1.

The first PMOS transistor MP1 and the second PMOS transistor MP2 are cross-coupled to form a positive feedback structure, so that the difference between the drain voltages of the second NMOS transistor MN2 and the third NMOS transistor MN3 can be amplified rapidly. The positive input signal INP is connected to the gate of the second NMOS transistor MN2, the negative input signal INN is connected to the gate of the third NMOS transistor MN3, EN is an enable signal of the first amplifier a1, EN is connected to the gate of the first NMOS transistor MN1, and when the enable signal EN is at a high level, the first NMOS transistor MN1 is turned on, and the level shift circuit is in a working state.

The source electrode of the first PMOS transistor, the source electrode of the second PMOS transistor, the source electrode of the third PMOS transistor, and the source electrode of the sixth PMOS transistor are connected to the power supply VDD, the drain electrode of the first PMOS transistor, the gate electrode of the second PMOS transistor, the drain electrode of the third PMOS transistor, the gate electrode of the third PMOS transistor, and the drain electrode of the second NMOS transistor are connected to the negative output terminal of the first amplifier, the drain electrode of the second PMOS transistor, the gate electrode of the first PMOS transistor, the drain electrode of the sixth PMOS transistor, the gate electrode of the sixth PMOS transistor, and the drain electrode of the third NMOS transistor are connected to the positive output terminal of the first amplifier, the source electrode of the second NMOS transistor, the source electrode of the third NMOS transistor, and the drain electrode of the first NMOS transistor are connected to the enable node E1, and the source electrode of the first NMOS transistor is connected to the ground terminal GND; the grid electrode of the second NMOS tube receives the forward input signal, the grid electrode of the third NMOS tube receives the reverse input signal, and the grid electrode of the first NMOS tube receives an enabling signal.

Specifically, the gate and the drain of the third PMOS transistor MP3 are shorted and are connected to the drain of the first PMOS transistor MP1 at the same time, the source of the third PMOS transistor MP3 is connected to the source of the first PMOS transistor MP1, the gate and the drain of the sixth PMOS transistor MP6 are shorted and are connected to the drain of the second PMOS transistor MP2 at the same time, the source of the sixth PMOS transistor MP6 is connected to the source of the second PMOS transistor MP2, the gate of the first PMOS transistor MP1 is connected to the drain of the second PMOS transistor MP2, and the gate of the second PMOS transistor MP2 is connected to the drain of the first PMOS transistor MP 1; the drain electrode of the second NMOS transistor MN2 is connected with the drain electrode of the first PMOS transistor MP1, the drain electrode of the third NMOS transistor MN3 is connected with the drain electrode of the second PMOS transistor MP2, the source electrode of the second NMOS transistor MN2 is connected with the source electrode of the third NMOS transistor MN3, the forward input signal INP is connected with the gate electrode of the second NMOS transistor MN2, and the reverse input signal INN is connected with the gate electrode of the third NMOS transistor MN 3; the drain of the first NMOS transistor MN1 is connected to the sources of the second NMOS transistor MN2 and the third NMOS transistor MN3, the source of the first NMOS transistor MN1 is grounded (connected to the ground GND), and the gate of the first NMOS transistor MN1 is connected to the enable signal EN.

The second amplifier A2 includes two NMOS tubes and two PMOS tubes, the two NMOS tubes are a sixth NMOS tube MN6 and a seventh NMOS tube MN7, and the two PMOS tubes are a seventh PMOS tube MP7 and an eighth PMOS tube MP 8. The seventh PMOS transistor MP7 and the sixth NMOS transistor MN6 are connected in series between the power supply VDD and the ground terminal GND, the eighth PMOS transistor MP8 and the seventh NMOS transistor MN7 are connected in series between the power supply VDD and the ground terminal GND, the source of the seventh PMOS transistor MP7 is connected to the power supply VDD, the gate thereof is connected to the positive output terminal of the first amplifier a1, the source of the eighth PMOS transistor MP8 is connected to the power supply VDD, the gate thereof is connected to the negative output terminal of the first amplifier a1, and the drain of the eighth PMOS transistor MP8 and the drain of the seventh NMOS transistor MN7 are connected to the output terminal of the second amplifier a 2.

The gate and the drain of the sixth NMOS transistor MN6 are shorted, the source of the sixth NMOS transistor MN6 and the source of the seventh NMOS transistor MN7 are connected to the ground GND, and the gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh NMOS transistor MN 7.

Specifically, the gate of the seventh PMOS transistor MP7 is connected to the gate of the sixth PMOS transistor MP6 in the first amplifier a1, the source of the seventh PMOS transistor MP7 is connected to the source of the eighth PMOS transistor MP8, the gate of the eighth PMOS transistor MP8 is connected to the drain of the first PMOS transistor MP1 in the first amplifier a1, the gate and the drain of the sixth NMOS transistor MN6 are shorted and simultaneously connected to the drain of the seventh PMOS transistor MP7, the source of the sixth NMOS transistor MN6 is connected to the source of the seventh NMOS transistor MN7 and simultaneously grounded, the gate of the sixth NMOS transistor MN6 is connected to the gate of the seventh NMOS transistor MN7, and the drain of the seventh NMOS transistor MN7 is connected to the forward output signal OUTP.

The third amplifier a3 includes two NMOS transistors and two PMOS transistors, the two NMOS transistors are a fourth NMOS transistor MN4 and a fifth NMOS transistor MN5, respectively, and the two PMOS transistors are a fourth PMOS transistor MP4 and a fifth PMOS transistor MP5, respectively. The fifth PMOS transistor MP5 and the fifth NMOS transistor MN5 are connected in series between the power supply VDD and the ground terminal GND, the fourth PMOS transistor MP4 and the fourth NMOS transistor MN4 are connected in series between the power supply VDD and the ground terminal GND, the source of the fourth PMOS transistor MP4 is connected to the power supply VDD, the gate thereof is connected to the negative output terminal of the first amplifier a1, the source of the fifth PMOS transistor MP5 is connected to the power supply VDD, the gate thereof is connected to the positive output terminal of the first amplifier a1, and the drain of the fifth PMOS transistor MP5 and the drain of the fifth NMOS transistor MN5 are connected to the output terminal of the third amplifier A3.

The drain and the gate of the fourth NMOS transistor MN4 are shorted, the source of the fourth NMOS transistor MN4 and the source of the fifth NMOS transistor MN5 are connected to the ground GND, and the gate of the fourth NMOS transistor MN4 is connected to the gate of the fifth NMOS transistor MN 5.

Specifically, a source of the fifth PMOS transistor MP5 is connected to a source of the fourth PMOS transistor MP4, a gate of the fifth PMOS transistor MP5 is connected to a drain of the second PMOS transistor MP2 in the first amplifier a1, a drain of the fifth PMOS transistor MP5 is connected to a drain of the fifth NMOS transistor MN5 and is simultaneously connected to the inverted output signal OUTN, a gate of the fourth PMOS transistor MP4 is connected to a gate of the third PMOS transistor MP3 in the first amplifier a1, a drain of the fourth PMOS transistor MP4 is connected to a drain of the fourth NMOS transistor MN4, a drain and a gate of the fourth NMOS transistor MN4 are shorted and are simultaneously connected to a gate of the fifth NMOS transistor MN5, and a source of the fourth NMOS transistor MN4 is connected to a source of the fifth NMOS transistor MN5 and is simultaneously connected to a ground terminal.

The drain of the third NMOS transistor MN3 is connected to the positive output terminal AP of the first amplifier a1, the drain of the second NMOS transistor MN2 is connected to the negative output signal AN of the negative output terminal of the first amplifier a1, the drain of the seventh NMOS transistor MN7 in the second amplifier a2 outputs the positive output signal OUTP of the level shifter, and the drain of the fifth NMOS transistor MN5 in the third amplifier A3 outputs the negative output signal OUTN of the level shifter.

If the bulk effect of the transistors is neglected, the gain of the first amplifier a1 is about Av1 ═ gmn2/gmp3, the gain of the second amplifier a2 is about Av2 ═ gmp 8| | ron7 (rop8| | | ron7), and the gain of the third amplifier A3 is about Av3 ═ gmp 5| | (rop5| | ron5), where gmn2, gmp3, gmp8, and gmp5 are transconductance of the second NMOS transistor MN2, the third PMOS transistor MP3, the eighth PMOS transistor MP8, and the fifth PMOS transistor MP5, and ron7, ron5, rop8, rop5 are small resistance signals of the seventh NMOS transistor MN7, the fifth NMOS transistor MN5, the eighth PMOS transistor MP8, and the fifth PMOS transistor MP5, respectively. The first amplifier a1 is a first-stage amplifier, the second amplifier a2 and the third amplifier A3 are second-stage amplifiers, the circuit structure and the device size of the second amplifier a2 and the third amplifier A3 are identical, except that the input and output signals are different, and the voltage gain of the two-stage amplifier of the level shift circuit can be expressed as Av1 Av2 Av1 Av3 gmn2 gmp8 (rop8 lron 7)/gmp3 because the structure of the level shift circuit is completely symmetrical and the sizes of the corresponding transistors are identical.

Example 1: the power supply voltage VDD is 1V, the enable signal EN is 1, the forward input signal INP and the reverse input signal INN are differential logic levels with a low swing, the high level is 0.5V, and the low level is 0V. When the forward input signal INP is changed from low to high and the reverse input signal INN is changed from high to low, the second NMOS transistor MN2 is turned on, the third NMOS transistor MN3 is turned off, the diode-connected sixth PMOS transistor MP6 provides a charging path for the positive output terminal AP of the first amplifier a1, so that the voltage of the forward output signal of the positive output terminal AP is increased until the first PMOS transistor MP1 is turned off, the voltage of the reverse output signal of the negative output terminal AN of the first amplifier a1 is decreased, so that the second PMOS transistor MP2 is turned on, and the positive feedback structure formed by the first PMOS transistor MP1 and the first PMOS transistor MP2 rapidly amplifies the output voltage difference of the first amplifier a1, so that the forward output voltage is increased and the reverse output voltage is decreased. Subsequently, the forward output signal OUTP output from the output terminal of the second amplifier a2 rises, the reverse output signal OUTN output from the output terminal of the third amplifier A3 falls, and finally the forward output signal OUTP of the level shifter circuit is 1V and the reverse output signal OUTN is 0V. When the forward input signal INP changes from high to low and the reverse input signal INN changes from low to high, the voltage signal at each node in the circuit changes in a reverse manner to the above, and the forward output signal OUTP of the level shifter circuit is 0V and the reverse output signal OUTN is 1V.

Referring to fig. 5, in the transient simulation waveform of example 1, the frequency of the forward input signal INP and the reverse input signal INN is 200MHz, the delay of the level transition is about 200ps, and the simulation result is basically consistent with the experimental principle.

Compared with the prior art, the level conversion circuit has the beneficial effects that:

(1) the level switching circuit shapes the input low swing logic level, makes the jumping edge steep and phase-splitting uniform, and outputs the logic level by a VDD full swing signal;

(2) the level conversion circuit is completely symmetrical, and the output differential signal almost has no phase error;

(3) the level conversion circuit of the invention adopts a two-stage amplifier structure, provides higher gain and improves the speed of level conversion.

The technical features of the above embodiments can be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the above embodiments are not described, but should be considered as the scope of the present specification as long as there is no contradiction between the combinations of the technical features.

The above examples only express preferred embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A level shift circuit, characterized by: the amplifier comprises a first amplifier, a second amplifier, a third amplifier, a forward input signal, an inverted input signal, a forward output signal and an inverted output signal, wherein the first amplifier is an amplifier with differential input and differential output, the second amplifier and the third amplifier are amplifiers with differential input and single-ended output, the first amplifier, the second amplifier and the third amplifier are powered by a power supply, the forward input signal is input into the positive input end of the first amplifier, the inverted input signal is input into the negative input end of the first amplifier, the positive output end of the first amplifier is connected to the positive input end of the second amplifier and the negative input end of the third amplifier, the negative output end of the first amplifier is connected to the negative input end of the second amplifier and the positive input end of the third amplifier, the output end of the second amplifier outputs the forward output signal, and the output end of the third amplifier outputs the reverse output signal.

2. A level conversion circuit as claimed in claim 1, wherein: the first amplifier comprises a second NMOS tube, a third NMOS tube, a first PMOS tube, a second PMOS tube, a third PMOS tube and a sixth PMOS tube, wherein the first PMOS tube and the second NMOS tube are connected in series between a power supply and a grounding end, the second PMOS tube and the third NMOS tube are connected in series between the power supply and the grounding end, the first PMOS tube and the third PMOS tube are connected in parallel between the power supply and the negative output end of the first amplifier, and the second PMOS tube and the sixth PMOS tube are connected in parallel between the power supply and the positive output end of the first amplifier, wherein the first PMOS tube and the second PMOS tube are in cross coupling connection to form a positive feedback structure.

3. A level conversion circuit as claimed in claim 2, wherein: the first amplifier further comprises an enabling node and a first NMOS (N-channel metal oxide semiconductor) tube connected between the enabling node and a grounding terminal in series, the first PMOS tube and the second NMOS tube are connected between the power supply and the enabling node in series, and the second PMOS tube and the third NMOS tube are connected between the power supply and the enabling node in series.

4. A level conversion circuit as claimed in claim 3, wherein: the source electrode of the first PMOS tube, the source electrode of the second PMOS tube, the source electrode of the third PMOS tube and the source electrode of the sixth PMOS tube are connected with the power supply, the drain electrode of the first PMOS tube, the gate electrode of the second PMOS tube, the drain electrode of the third PMOS tube, the gate electrode of the third PMOS tube and the drain electrode of the second NMOS tube are connected with the negative output end of the first amplifier, the drain electrode of the second PMOS tube, the gate electrode of the first PMOS tube, the drain electrode of the sixth PMOS tube, the gate electrode of the sixth PMOS tube and the drain electrode of the third NMOS tube are connected with the positive output end of the first amplifier, the source electrode of the second NMOS tube, the source electrode of the third NMOS tube and the drain electrode of the first NMOS tube are connected with the enable node, and the source electrode of the first NMOS tube is connected with the ground terminal; the grid electrode of the second NMOS tube receives the forward input signal, the grid electrode of the third NMOS tube receives the reverse input signal, and the grid electrode of the first NMOS tube receives an enabling signal.

5. A level conversion circuit as claimed in claim 4, wherein: the second amplifier comprises a seventh PMOS tube, an eighth PMOS tube, a sixth NMOS tube and a seventh NMOS tube, wherein the seventh PMOS tube and the sixth NMOS tube are connected in series between the power supply and the grounding terminal, the eighth PMOS tube and the seventh NMOS tube are connected in series between the power supply and the grounding terminal, the source electrode of the seventh PMOS tube is connected with the power supply, the grid electrode of the seventh PMOS tube is connected with the positive output end of the first amplifier, the source electrode of the eighth PMOS tube is connected with the power supply, the grid electrode of the eighth PMOS tube is connected with the negative output end of the first amplifier, and the drain electrode of the eighth PMOS tube and the drain electrode of the seventh NMOS tube are connected with the output end of the second amplifier.

6. A level conversion circuit as claimed in claim 5, wherein: the grid electrode and the drain electrode of the sixth NMOS tube are in short circuit, the source electrode of the sixth NMOS tube and the source electrode of the seventh NMOS tube are connected to the ground terminal, and the grid electrode of the sixth NMOS tube is connected with the grid electrode of the seventh NMOS tube.

7. A level conversion circuit as claimed in claim 6, wherein: the third amplifier comprises a fifth PMOS tube, a fourth PMOS tube, a fifth NMOS tube and a fourth NMOS tube, wherein the fifth PMOS tube and the fifth NMOS tube are connected in series between a power supply and a grounding end, the fourth PMOS tube and the fourth NMOS tube are connected in series between the power supply and the grounding end, a source electrode of the fourth PMOS tube is connected with the power supply, a grid electrode of the fourth PMOS tube is connected with the negative output end of the first amplifier, a source electrode of the fifth PMOS tube is connected with the power supply, the grid electrode of the fifth PMOS tube is connected with the positive output end of the first amplifier, and a drain electrode of the fifth PMOS tube and a drain electrode of the fifth NMOS tube are connected with the output end of the third amplifier.

8. A level conversion circuit as claimed in claim 7, wherein: the drain electrode of the fourth NMOS tube is in short circuit with the grid electrode, the source electrode of the fourth NMOS tube and the source electrode of the fifth NMOS tube are connected with the grounding end, and the grid electrode of the fourth NMOS tube is connected with the grid electrode of the fifth NMOS tube.

9. A level conversion circuit as claimed in claim 8, wherein: the gain of the first amplifier is about Av1 ═ gmn2/gmp3, the gain of the second amplifier is about Av2 ═ gmp8 ═ rop8| | ron7, the gain of the third amplifier is about Av3 ═ gmp 5| (rop5| | ron5), wherein gmn2, gmp3, gmp8, and gmp5 are transconductance of a second NMOS transistor, a third PMOS transistor, an eighth PMOS transistor, and a fifth PMOS transistor, respectively, and ron7, ron5, rop8, and rop5 are small-signal resistances of a seventh NMOS transistor, a fifth NMOS transistor, an eighth PMOS transistor, and a fifth PMOS transistor, respectively.

10. A level conversion circuit as claimed in claim 9, wherein: the voltage gain of the two-stage amplifier of the level shift circuit may be represented as Av1 Av2 Av1 Av3 gmn2 gmp8 (rop8 ron7)/gmp 3.

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