CN113113444A - Metal-based programmable logic circuit for in-memory computation and preparation method thereof - Google Patents

Metal-based programmable logic circuit for in-memory computation and preparation method thereof Download PDF

Info

Publication number
CN113113444A
CN113113444A CN202110650247.8A CN202110650247A CN113113444A CN 113113444 A CN113113444 A CN 113113444A CN 202110650247 A CN202110650247 A CN 202110650247A CN 113113444 A CN113113444 A CN 113113444A
Authority
CN
China
Prior art keywords
nanowire
programmable logic
magnetic
metal
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN202110650247.8A
Other languages
Chinese (zh)
Inventor
郑翔宇
李梓漪
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nanji Agricultural Machinery Research Institute Co ltd
Original Assignee
Nanji Agricultural Machinery Research Institute Co ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nanji Agricultural Machinery Research Institute Co ltd filed Critical Nanji Agricultural Machinery Research Institute Co ltd
Priority to CN202110650247.8A priority Critical patent/CN113113444A/en
Publication of CN113113444A publication Critical patent/CN113113444A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N59/00—Integrated devices, or assemblies of multiple devices, comprising at least one galvanomagnetic or Hall-effect element covered by groups H10N50/00 - H10N52/00
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y30/00—Nanotechnology for materials or surface science, e.g. nanocomposites
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y40/00—Manufacture or treatment of nanostructures
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/34—Circuit design for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G06F30/347—Physical level, e.g. placement or routing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B61/00—Magnetic memory devices, e.g. magnetoresistive RAM [MRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/01—Manufacture or treatment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/10—Magnetoresistive devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N50/00—Galvanomagnetic devices
    • H10N50/80—Constructional details
    • H10N50/85—Magnetic active materials

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Physics & Mathematics (AREA)
  • Nanotechnology (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Theoretical Computer Science (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • General Engineering & Computer Science (AREA)
  • Composite Materials (AREA)
  • Materials Engineering (AREA)
  • Geometry (AREA)
  • Evolutionary Computation (AREA)
  • Hall/Mr Elements (AREA)

Abstract

The invention relates to a metal-based programmable logic circuit for calculation in a memory and a preparation method thereof, belonging to the technical field of microelectronics, and comprising a programmable logic gate, wherein the programmable logic gate is composed of a magnetic material, the width of the magnetic material is the same everywhere, the programmable logic gate is a three-terminal device composed of two nanowires A with magnetic tips and a nanowire C, and one section of the two nanowires A with magnetic tips and one section of the nanowire C are superposed to form a single nanowire B with a magnetic easily reversible plate, so that the physical interval between storage and calculation can be eliminated, the limitation of a storage barrier is broken, the processing performance of a computer is greatly improved, various logic gates are integrated, the design of a magnetic programmable logic device is realized, and the scale of a complex logic gate of an integrated circuit can be greatly reduced in the future.

Description

Metal-based programmable logic circuit for in-memory computation and preparation method thereof
Technical Field
The invention belongs to the technical field of microelectronics, and particularly relates to a metal-based programmable logic circuit for in-memory computation and a preparation method thereof.
Background
In recent years, conventional large scale integrated circuits based on electronic charge have been very close to the theoretical limit of mole. However, the electron spin based memory cell or logic device has great potential and advantages to replace or combine with the existing integrated circuit to realize the next generation of non-volatile, low power consumption, high processing capability magnetoelectric memory or logic device. In recent years, in the next generation of memory technology, Magnetic Random Access Memory (MRAM) (magnetic random access memory), which has been a relatively mature technology in the field of magnetoresistive memory, has been proposed since the beginning to the recent introduction of commercial products several decades ago. In the research of magnetoresistive logic units, many researchers have proposed some successful logic structure design schemes, such as domain wall movement (domain wall movement), eddy current movement (vortex movement).
This is particularly important since logic gates are indispensable for all electronic products. However, the conventional logic gate needs to use a large number of transistors to implement a logic operation, which results in a complex computer structure design and occupies too much space in the central processing unit. Magnetic logic gates based on the movement of magnetic Domain walls (Domain-wall logic) are superior to conventional logic gates in many respects, most notably in terms of size, which can be as small as 20 nm, as determined by the width of the Domain wall. This means that the overall system is much smaller than a system built from conventional logic gates. Low power consumption and high efficiency are another advantage, where the resistance reduction is significant and transient. By introducing such a logic gate, costs can also be reduced. Furthermore, the alignment of the spin direction is independent of temperature variations, making the magnetic logic gate more stable than conventional semiconductor-based devices.
Currently, implementing In-memory computing (In-memory computing) based on magnetoelectric storage and logic devices of electron spin is a very popular research direction. The physical interval between storage and calculation can be eliminated by realizing logic calculation in the internal memory, so that the limitation of a storage barrier is broken, and the processing performance of the computer is greatly improved. The design similar to the operation mode of human brain neurons aims at subverting the traditional von Neumann type computer structure, and directly performs calculation in a computer memory to realize synchronous storage and calculation. With the advent of non-volatile computational memory, the feasibility of in-memory computation has increased dramatically and has a trend towards commercialization.
Most of the existing magnetic logic gates (Domain-wall logic) with magnetic Domain wall movement can only realize single logic operation, and the effective combination of storage and logic operation cannot be realized In design and application, so that the traditional magnetic logic gates (Domain-wall logic) with magnetic Domain wall movement lack feasibility In the field of In-memory computing.
Disclosure of Invention
Technical problem to be solved by the invention
The invention aims to solve the defects, designs a novel Domain-wall moving magnetic logic gate (Domain-wall logic) of a field effect transistor, and realizes a metal-based programmable logic unit for calculation in a memory by combining storage and logic operation into a whole.
Technical scheme
In order to achieve the purpose, the technical scheme provided by the invention is as follows:
the invention relates to a metal-based programmable logic circuit for calculation in a memory, which comprises a programmable logic gate, wherein the programmable logic gate is made of a magnetic material, the width of the magnetic material is the same everywhere, the programmable logic gate is a three-terminal device consisting of two nanowires A with magnetic tips and a nanowire C, and the two nanowires A with the magnetic tips and one section of the nanowire C are superposed to form a single nanowire B with a magnetic easily-reversible plate.
Preferably, the magnetic material is a soft magnetic amorphous alloy Fe40Co40B20。
Preferably, the programmable logic gate receives different external magnetic field input logics to obtain different output logics, including OR logic, NAND logic and XOR logic.
Preferably, the nanowire A, the nanowire B and the nanowire C form an included angle of 120 degrees, the length of the nanowire A is the same as that of the nanowire C, and the length of the nanowire B is larger than that of the nanowire A.
Preferably, domain wall movement, domain capture, and domain wall resistance change between the input and output of the programmable logic gate using external magnetic field guidance will be read by magnetic tunnel junctions integrated on nanowires a, B, and C.
A method for preparing metal-based programmable logic circuit for in-memory computation includes using electron beam to etch nano wire A, nano wire B, nano wire C and reversible plate, and using photo etching method to generate magnetic tunnel junction on nano wire A, nano wire B and nano wire C.
Preferably, the material used for the nanowires A, B and C is soft magnetic amorphous alloy Fe40Co40B20The preparation method adopts a vacuum magnetron sputtering method.
Preferably, soft magnetic amorphous alloy Fe40Co40B20With Ta capping layer, Fe40Co40B20Is 10nm and the thickness of the Ta capping layer is 10 nm.
Preferably, the length-width ratio of the nanowire A to the nanowire C is 20:1, and the length-width ratio of the nanowire B is 30: 1.
Preferably, the magnetic tunnel junctions are a common structure, with a single magnetic tunnel junction connecting multiple programmable logic gates.
Advantageous effects
Compared with the prior art, the technical scheme provided by the invention has the following beneficial effects:
(1) according to the calculated metal base class field effect tube magnetic domain wall movable logic unit in the memory, under the condition of external magnetic field input, the nanowire magnetization process presents asymmetric magnetization, and the on-off between the source electrode and the drain electrode of the field effect tube controlled by the grid electrode is reflected.
(2) The metal-based programmable logic circuit for in-memory calculation can eliminate the physical interval between storage and calculation, thereby breaking the limitation of storage barriers and greatly improving the processing performance of a computer. Various logic gates are integrated, the design of the magnetic programmable logic device is realized, and the scale of the complex logic gates of the integrated circuit can be greatly reduced in the future.
(3) The invention relates to a metal-based programmable logic circuit for in-memory computation, wherein a magnetic material is soft magnetic amorphous alloy Fe40Co40B20By utilizing the property that the coercive force (coercivity) of the FeNi alloy is much smaller, the magnitude of the write magnetic field can be greatly reduced.
(4) The invention relates to a metal-based programmable logic circuit for in-memory computation, wherein a magnetic material is soft magnetic amorphous alloy Fe40Co40B20By utilizing its lower magnetic damping characteristics, the critical current required for reading can be reduced.
(5) The metal-based programmable logic circuit for in-memory computation realizes the electrical reading based on the magnetic tunnel junction structure and is easier to combine with the existing integrated circuit.
(6) The metal-based programmable logic circuit for in-memory calculation is not limited by size, and has low energy consumption and high efficiency.
Drawings
FIG. 1 is a schematic diagram of an in-memory metal-based programmable logic circuit according to the present invention;
FIG. 2 is a diagram of magnetic field inputs for an in-memory computational metal-based programmable logic circuit in accordance with the present invention;
FIG. 3 is a graph of magnetization at the + Y input of an in-memory computational metal-based programmable logic circuit in accordance with the present invention;
FIG. 4 is a graph of magnetization at the-Y input of an in-memory computational metal-based programmable logic circuit in accordance with the present invention;
FIG. 5 is a block diagram of a dual-layer programmable logic gate of an in-memory metal-based programmable logic circuit according to the present invention;
FIG. 6 is a block diagram of a combinational programmable logic gate of an in-memory computational metal-based programmable logic circuit in accordance with the present invention;
FIG. 7 is a flowchart illustrating the operation of a combinational programmable logic gate of an in-memory metal-based programmable logic circuit according to the present invention when the X reset magnetic field is + 1;
FIG. 8 is a flow chart of the operation of a combinational programmable logic gate of an in-memory metal-based programmable logic circuit according to the present invention when the X reset field is-1.
The reference numerals in the schematic drawings illustrate:
100. a nanowire A; 110. a magnetic tip;
200. a nanowire C;
300. a nanowire B;
400. a reversible plate;
500. a magnetic tunnel junction.
Detailed Description
In order to facilitate an understanding of the invention, the invention will now be described more fully hereinafter with reference to the accompanying drawings, in which several embodiments of the invention are shown, but which may be embodied in many different forms and are not limited to the embodiments described herein, but rather are provided for the purpose of providing a more thorough disclosure of the invention.
It will be understood that when an element is referred to as being "secured to" another element, it can be directly on the other element or intervening elements may also be present; when an element is referred to as being "connected" to another element, it can be directly connected to the other element or intervening elements may also be present; the terms "vertical," "horizontal," "left," "right," and the like as used herein are for illustrative purposes only.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs; the terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention; as used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
Example 1
Referring to fig. 1 to 8, a metal-based programmable logic circuit for in-memory computation of this embodiment includes a programmable logic gate, where the programmable logic gate is made of a magnetic material, the width of the magnetic material is the same everywhere, the programmable logic gate is a three-terminal device composed of two nanowires a100 and C200 with magnetic tips 110, and a segment of the two nanowires a100 and C200 with magnetic tips 110 is overlapped to form a single nanowire B300 of a magnetically reversible plate 400.
The magnetic material of this example is soft magnetic amorphous alloy Fe40Co40B20The magnetic material being a soft magnetic amorphous alloy such as Fe40Co40B20To reduce the critical current.
The programmable logic gate of the embodiment receives different external magnetic field input logics to obtain different output logics, including OR logic, NAND logic and XOR logic.
Two of the nanowires a100, B300, and C200 in this embodiment form an included angle of 120 °, the length of the nanowire a100 is the same as that of the nanowire C200, the length of the nanowire B300 is greater than that of the nanowire a100, and the specific included angle design enables the nanowires to maintain a symmetrical structure under logic external magnetic field input, and any two nanowires are under the same action under logic input.
Domain wall movement, magnetic domain capture and domain wall resistance change guided by an external magnetic field are adopted between the input and the output of the programmable logic gate of the embodiment to be read by the magnetic tunnel junction 500 integrated on the nanowire A100, the nanowire B300 and the nanowire C200, after the input operation of the external magnetic field, a logic calculation result is directly stored in the magnetic nano structure, and the magnetic tunnel junction 500 electrically reads magnetic information on the magnetic nanowire through an STT effect; the magnetic domain directions of the nanowire A100 and the nanowire B300 can be compared to output to the next stage of transportation or obtain the final result.
The specific contents are as follows:
as shown in fig. 2-4, the Y input serves as the nanowire C200 magnetization state initialization condition. Under the + Y input initialization condition, fig. 3 extracts the magnetization process of the nanowire a100 and the nanowire B300 under the X input scanning magnetic field, which exhibits the asymmetric magnetization phenomenon. under-Y input initialization conditions, figure 4 extracts the magnetization process of nanowire a100 and nanowire B300 under the X input scanning magnetic field, which exhibits an asymmetric magnetization phenomenon opposite to that before. This phenomenon shows that the magnetization process of nanowires a100 and B300 at X input is determined by the magnetization state of nanowire C200, reflecting the on/off between the source and drain of the fet-like transistor controlled by the gate.
Example 2
Referring to fig. 1-2, in the method for manufacturing a metal-based programmable logic circuit in a memory according to this embodiment, the nanowire a100, the nanowire B300, the nanowire C200, and the reversible plate 400 are etched by using an electron beam, and a magnetic tunnel junction 500 is formed on each of the nanowire a100, the nanowire B300, and the nanowire C200 by using a photolithography method.
The material soft magnetic amorphous alloy Fe used for the nanowire A100, the nanowire B300 and the nanowire C200 of the embodiment40Co40B20The preparation method adopts a metal deposition method.
Soft magnetic amorphous alloy Fe of the present example40Co40B20With Ta capping layer, Fe40Co40B20Is 10nm and the thickness of the Ta capping layer is 10 nm.
In this embodiment, the length-width ratio of the nanowire a100 to the nanowire C200 is 20:1, the length-width ratio of the nanowire B300 is 30:1, the specific values of the length-width are not fixed, and the magnetic domain logic gate can be amplified or reduced in an equal ratio.
The magnetic tunnel junction 500 of this embodiment is a shared structure, and a single magnetic tunnel junction 500 is connected to a plurality of programmable logic gates.
The programmable logic gate of the design comprises two situations, which are respectively as follows:
1. as shown in fig. 5, the two-layer programmable logic gate includes a bottom layer logic gate and a top layer logic gate, both of which are configured as described above, wherein the bottom layer logic gate and the top layer logic gate share a magnetic tunnel junction 500.
2. As shown in fig. 6, the combinational programmable logic gate includes a positive logic gate and a negative logic gate, and the nanowire C200 on the positive logic gate and the negative logic gate share the same magnetic tunnel junction 500.
The specific contents are as follows:
wherein, "+/-1" indicates the direction and magnitude of the external initial magnetic field or magnetic domain and the output high and low magnetic resistance, and, "+/-1/2" indicates the direction and magnitude of the external operating magnetic field.
As shown in fig. 1-2, the magnetic field Y input is parallel to the nanowire C200 and its magnetization direction is manipulated to control pinning or de-pinning of the domain wall at the nanowire a100, nanowire B300 junction. Different X reset magnetic fields are selected as triggering conditions for switching of the logic gate, so that programmable logic gate control is realized. The magnetic tunnel junction 500 is integrated on the programmable logic gate to read magnetic calculation information of the nanowires a100, B300, and C200 under external magnetic field input operation in different directions, so as to implement in-memory calculation.
As shown in Table 1, an X reset field of +1 is selected and the nanostructure is OR-gated. Under the external magnetic field X input and Y input conditions corresponding to the magnitude and the direction, the final truth table gives an OR logic output result. As shown in the following table, the specific operation and results of the programmable logic gate of the present embodiment are shown in practical application conditions.
The results are as follows:
Figure 357693DEST_PATH_IMAGE001
TABLE 1
As shown in Table 2, the X reset field is selected to be-1, and the nanostructure is subjected to NAND logic gate operation, i.e., high input and low output.
The results are as follows:
Figure 304527DEST_PATH_IMAGE002
TABLE 2
As shown in table 3: when the X reset field is selected as-1 and then +1, the nano structure is operated by an exclusive OR logic gate, and particularly, the sign of the X reset field is opposite to that of the Y input logic, and the final truth table accords with the designed logic operation result.
The results are as follows:
Figure 349843DEST_PATH_IMAGE003
TABLE 3
As shown in fig. 6, the magnetic field Y input is parallel to the nanowire C200 and its magnetization direction is manipulated to control pinning or unpinning of the domain walls at the nanowire a100, B junction. Different X reset magnetic fields are selected as triggering conditions for switching of the logic gate, so that programmable logic gate control is realized. The magnetic tunnel junction 500 is integrated on the programmable logic gate, and the nanowires C200 share the same magnetic tunnel junction 500 to read magnetic computation information to implement in-memory computation.
7-8 are flow diagrams of the operation of the combinational programmable logic gate, which can implement a logic OR gate operation and an input common low output low when the X reset field is + 1. When the X reset magnetic field is-1, the combinational programmable logic gate can realize the operation of a logic NAND gate and the input is the same as high and the output is low.
The above-mentioned embodiments only express a certain implementation mode of the present invention, and the description thereof is specific and detailed, but not construed as limiting the scope of the present invention; it should be noted that, for those skilled in the art, without departing from the concept of the present invention, several variations and modifications can be made, which are within the protection scope of the present invention; therefore, the protection scope of the present patent shall be subject to the appended claims.

Claims (10)

1. A metal-based programmable logic circuit for in-memory computation, comprising: the programmable logic gate is a three-terminal device consisting of two nanowires A (100) and C (200) with magnetic tips (110), wherein the two nanowires A (100) and C (200) with magnetic tips (110) are superposed to form a single nanowire B (300) of a magnetically reversible plate (400).
2. The in-memory computational metal-based programmable logic circuit of claim 1, wherein: the magnetic material is soft magnetic amorphous alloy Fe40Co40B20。
3. The in-memory computational metal-based programmable logic circuit of claim 1, wherein: the programmable logic gate receives different external magnetic field input logics to obtain different output logics including OR logic, NAND logic and XOR logic.
4. The in-memory computational metal-based programmable logic circuit of claim 1, wherein: two included angles of 120 degrees are formed among the nanowire A (100), the nanowire B (300) and the nanowire C (200), the length of the nanowire A (100) is the same as that of the nanowire C (200), and the length of the nanowire B (300) is larger than that of the nanowire A (100).
5. The in-memory computational metal-based programmable logic circuit of claim 3, wherein: domain wall motion, domain trapping, and domain wall resistance change between the input and output of the programmable logic gate using external magnetic field guidance will be read by magnetic tunnel junctions (500) integrated on nanowires a (100), B (300), and C (200).
6. A method for preparing a metal-based programmable logic circuit for in-memory computation is characterized in that: the nanowire A (100), the nanowire B (300), the nanowire C (200) and the reversible plate (400) are etched by adopting an electron beam, and a magnetic tunnel junction (500) is generated on the nanowire A (100), the nanowire B (300) and the nanowire C (200) by using a mask and photoetching method.
7. The method of claim 6, wherein the method comprises: the materials of the nanowire A (100), the nanowire B (300) and the nanowire C (200) are soft magnetic amorphous alloy Fe40Co40B20The preparation method adopts a vacuum magnetron sputtering method.
8. The method of claim 6, wherein the method comprises: the soft magnetic amorphous alloy Fe40Co40B20Growing on MgO substrate with Ta capping layer, the Fe40Co40B20Is 10nm, and the thickness of the Ta capping layer is 10 nm.
9. The method of claim 7, wherein the method comprises: the length-width ratio of the nanowire A (100) to the nanowire C (200) is 20:1, and the length-width ratio of the nanowire B (300) is 30: 1.
10. The method of claim 6, wherein the method comprises: the magnetic tunnel junctions (500) are of a common structure, and a single magnetic tunnel junction (500) is connected with a plurality of programmable logic gates.
CN202110650247.8A 2021-06-11 2021-06-11 Metal-based programmable logic circuit for in-memory computation and preparation method thereof Pending CN113113444A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110650247.8A CN113113444A (en) 2021-06-11 2021-06-11 Metal-based programmable logic circuit for in-memory computation and preparation method thereof

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110650247.8A CN113113444A (en) 2021-06-11 2021-06-11 Metal-based programmable logic circuit for in-memory computation and preparation method thereof

Publications (1)

Publication Number Publication Date
CN113113444A true CN113113444A (en) 2021-07-13

Family

ID=76723464

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110650247.8A Pending CN113113444A (en) 2021-06-11 2021-06-11 Metal-based programmable logic circuit for in-memory computation and preparation method thereof

Country Status (1)

Country Link
CN (1) CN113113444A (en)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8772889B2 (en) * 2012-11-20 2014-07-08 International Business Machines Corporation Magnetic domain wall shift register memory device readout
CN107408627A (en) * 2015-04-10 2017-11-28 美光科技公司 Used method and the method for forming MTJ when MTJ, formation MTJ
CN108008326A (en) * 2016-10-31 2018-05-08 南京大学 A kind of method of regulation and control MRAM material damping factors
CN110071213A (en) * 2019-04-08 2019-07-30 三峡大学 Logical device based on neticdomain wall pinning Yu de- nail behavior

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8772889B2 (en) * 2012-11-20 2014-07-08 International Business Machines Corporation Magnetic domain wall shift register memory device readout
CN107408627A (en) * 2015-04-10 2017-11-28 美光科技公司 Used method and the method for forming MTJ when MTJ, formation MTJ
CN108008326A (en) * 2016-10-31 2018-05-08 南京大学 A kind of method of regulation and control MRAM material damping factors
CN110071213A (en) * 2019-04-08 2019-07-30 三峡大学 Logical device based on neticdomain wall pinning Yu de- nail behavior

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
XIANGYU ZHENG等: "Paradigm of Magnetic Domain Wall-Based In-Memory Computing", 《ACS APPL. ELECTRON MATER》 *

Similar Documents

Publication Publication Date Title
US8063460B2 (en) Spin torque magnetic integrated circuits and devices therefor
JP5648940B2 (en) Apparatus, method and memory cell for controlling a magnetic field in a magnetic tunnel junction
US7969762B2 (en) Spintronic device with control by domain wall displacement induced by a current of spin-polarized carriers
CN107732005B (en) Spin multi-gate device and logic circuit
US20130070513A1 (en) Method and apparatus for direct backup of memory circuits
CN111953312B (en) NOT gate based on topological magnetic structure and control method thereof
JP7563851B2 (en) Method and device for controlling switching orbit in spin-orbit torque device
Hong et al. 3D multilevel spin transfer torque devices
TWI235371B (en) Magnetic random access memory, magnetic cell therein, and associated method therefor
US7212026B2 (en) Spin-orbital quantum cellular automata logic devices and systems
CN116403624B (en) Track transfer torque magnetic random storage device and implementation method thereof
TW201310449A (en) Spin-torque transfer memory cell structures with symmetric switching and single direction programming
CN111933789A (en) Multi-state memory, preparation method and storage method thereof, and artificial synapse device
CN113113444A (en) Metal-based programmable logic circuit for in-memory computation and preparation method thereof
JP3566148B2 (en) Spin-dependent switching element
WO2023005970A1 (en) Magnetic random access memory and apparatus
CN111697130B (en) Magnetic memory cell and logic device having horizontally asymmetric magnetic free layer
CN113450849B (en) Magnetic storage unit, data writing method, memory and equipment
CN116096212A (en) Method for manufacturing multi-bit magnetic memory cell and memory cell
CN113764459A (en) Low-temperature magnetic superconducting hybrid storage unit and memory
WO2022036623A1 (en) Non-external magnetic field oriented spin flip sot-mram and array
CN117979808A (en) Double-pinning layer memory unit, preparation method thereof, memory and electronic equipment
CN118042915A (en) Ring gate type magnetic memory device and preparation method thereof
Kasatkin et al. Elements of spin logic
KR20210119941A (en) Magnetic domain wall logic element and manufacturing method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
RJ01 Rejection of invention patent application after publication

Application publication date: 20210713

RJ01 Rejection of invention patent application after publication