CN113113349A - Method for forming semiconductor structure - Google Patents
Method for forming semiconductor structure Download PDFInfo
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- CN113113349A CN113113349A CN202010026387.3A CN202010026387A CN113113349A CN 113113349 A CN113113349 A CN 113113349A CN 202010026387 A CN202010026387 A CN 202010026387A CN 113113349 A CN113113349 A CN 113113349A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76816—Aspects relating to the layout of the pattern or to the size of vias or trenches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/10—Applying interconnections to be used for carrying current between separate components within a device
- H01L2221/1005—Formation and after-treatment of dielectrics
- H01L2221/101—Forming openings in dielectrics
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- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
A method for forming a semiconductor structure, the method comprising: providing a substrate; forming a pattern material layer on a substrate; performing a plurality of groove forming steps on the pattern material layer, sequentially forming grooves at a plurality of positions of the pattern material layer, and using the remaining pattern material layer as the pattern layer, wherein the groove forming step comprises: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer positioned on the top surface of the pattern material layer is used as a protective layer; removing the second mask layer; after the pattern layer is formed, the protective layer is removed. According to the embodiment of the invention, after the pattern layer is formed, the protective layer is removed, so that the material of the top surface of the pattern layer and the boundary area of all the side walls of the groove is only damaged once, and therefore, the chamfer angle at the top of the side wall of the groove is smaller, and the optimization of the electrical performance of the semiconductor structure is facilitated.
Description
Technical Field
The embodiment of the invention relates to the field of semiconductor manufacturing, in particular to a method for forming a semiconductor structure.
Background
As semiconductor manufacturing technology becomes more sophisticated, integrated circuits have also undergone significant changes, and the number of components integrated on the same chip has increased from the first tens, hundreds to the present millions. In order to meet the circuit density requirements, the fabrication process of semiconductor integrated circuit chips utilizes batch processing techniques to form various types of complex devices on a substrate and interconnect them for complete electronic functionality, mostly using ultra-low k interlevel dielectric layers between conductive lines as the dielectric material for isolating the metal interconnects, and interconnect structures for providing wiring between the devices on the IC chip and the entire package. In this technique, devices such as Field Effect Transistors (FETs) are first formed on the surface of a semiconductor substrate, and then interconnect structures are formed in Back End of Line (BEOL) fabrication processes for integrated circuits.
As moore's law predicts, the shrinking dimensions of semiconductor substrates and the formation of more transistors on semiconductor substrates to improve device performance, the use of interconnect structures to connect the transistors is a necessary option. However, compared with the miniaturization and the increase of the integration of components, the number of conductor connecting lines in the circuit is continuously increased, the forming quality of the interconnection structure has great influence on the reliability of circuit connection, and the normal operation of the semiconductor device can be seriously influenced.
Disclosure of Invention
The embodiment of the invention solves the problem of providing a method for forming a semiconductor structure, and improving the electrical performance of a device.
To solve the above problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a pattern material layer on the substrate; performing a plurality of groove forming steps on the pattern material layer, sequentially forming grooves at a plurality of positions of the pattern material layer, and using the remaining pattern material layer as the pattern layer, wherein the groove forming step comprises: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer positioned on the top surface of the pattern material layer is used as a protective layer; removing the second mask layer; and after the pattern layer is formed, removing the protective layer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
in the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of forming the groove, a mask layer is formed on the pattern material layer, the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, the second mask layer is provided with an opening, the pattern material layer is etched by taking the second mask layer as a mask, a groove is formed in the pattern material layer, the first mask layer positioned on the top surface of the pattern material layer is taken as a protective layer, so that the top surface of the pattern material layer covered by the protective layer is not exposed in the process of forming the groove, and the material of the corresponding junction area between the top surface of the pattern material layer and the side wall of the groove is not easily damaged; after the pattern layer is formed, the protective layer is removed, so that materials of the top surface of the pattern layer and the junction area of all groove side walls are damaged only once, the chamfer angle of the top of the groove side wall is small, gaps are not prone to exist at the top of a top mask layer formed in the groove subsequently, the pattern layer is removed, the top mask layer is used as a mask to etch the substrate, a residual substrate and an isolation layer located on the residual substrate are formed, gaps are not prone to exist at the top of the isolation layer, a conducting layer is formed on the residual substrate between the isolation layers, conducting materials forming the conducting layer are not prone to being deposited at the top of the isolation layer, the probability of conducting layer leakage current is favorably reduced, and the electrical performance of a semiconductor structure is.
Drawings
Fig. 1 to 10 are schematic structural diagrams corresponding to steps in a method for forming a semiconductor structure;
fig. 11 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Detailed Description
The devices formed at present still have the problem of poor performance. The reason for the poor performance of the device is analyzed in combination with a method for forming a semiconductor structure.
Fig. 1 to 10 are schematic structural diagrams corresponding to respective steps in a method for forming a semiconductor structure.
As shown in fig. 1 and 2, fig. 2 is a cross-sectional view in the direction AA of fig. 1, and provides a base including a substrate 1 and a pattern material layer 2 on the substrate 1.
As shown in fig. 3, a first mask layer 3 is formed to cover the patterning material layer 2 and the substrate 1, wherein the first mask layer 3 includes a first organic material layer 31, a first anti-reflective coating 32 on the first organic material layer 31, and a first photoresist layer 33 on the first anti-reflective coating 32, and the first photoresist layer has an opening 4 therein.
As shown in fig. 4, the first mask layer 3 is used as a mask to etch the pattern material layer 2, and a first groove 5 is formed in the pattern material layer 2; after the first groove 5 is formed, the first mask layer 3 is removed.
As shown in fig. 5, after removing the first masking layer 3, a second masking layer 6 is formed to cover the pattern material layer 2 and the substrate 1, where the second masking layer 6 includes a second organic material layer 61, a second anti-reflection coating 62 on the second organic material layer 61, and a second photoresist layer 63 on the second anti-reflection coating 62, and the second photoresist layer 63 has an opening 7 therein.
As shown in fig. 6 and 7, fig. 7 is a view of fig. 6 in a direction B, the pattern material layer 2 is etched by using the second mask layer 6 as a mask, and a second groove 8 is formed in the pattern material layer 2; after the second groove 8 is formed, the second mask layer 6 is removed.
As shown in fig. 8 and 9, a masking material layer 11 is conformally coated on the patterned material layer 2 and the substrate 1 between the patterned material layer 2; removing the mask material layer 11 higher than the pattern material layer 2, and taking the residual mask material layer 11 as a mask layer 9; after the mask layer 9 is formed, the pattern material layer 2 is removed.
As shown in fig. 10, the substrate 1 is etched by using the mask layer 9 as a mask to form a remaining substrate 12 and a separating layer 13 located on the remaining substrate 12, a conductive material layer (not shown in the figure) is formed on the remaining substrate 12 exposed by the separating layer 13, the conductive material layer higher than the separating layer 13 is removed, and the remaining conductive material layer is used as a conductive layer 10.
With the continuous improvement of the integration of integrated circuits, the size of the semiconductor structure is smaller and smaller, and the distance between the first groove 105 and the second groove 108 in the corresponding pattern material layer 102 is smaller and smaller, because the resolving capability of the current lithography machine is not enough, a mask layer for forming the first groove 105 and the second groove 108 cannot be generated by one exposure, in the method for forming the semiconductor structure, the first groove 105 and the second groove 108 need to be formed through the cooperation of the first mask layer 3 and the second mask layer 6. After the first groove 5 is formed, in the step of removing the first mask layer 3, the top of the side wall of the first groove 5 is damaged in the area where the pattern material layer 2 is jointed; after the second groove 8 is formed, in the step of removing the second mask layer 6, the region where the top of the side wall of the first groove 5 is connected with the pattern material layer 2 is damaged again, and the region where the top of the side wall of the second groove 8 is connected with the pattern material layer 2 is damaged only once, so that the chamfer angle of the top of the first groove 5 is larger than the chamfer angle of the top of the second groove 8. In the process of forming the mask material layer 11, the top of the first groove 5 is not easily filled, a gap (team) a (as shown in fig. 8) easily exists, correspondingly, a gap easily exists at the top of the mask layer 9, in the process of forming the separation layer 13 by using the mask layer 9 as a mask, the gap can be transferred to the separation layer 13, in the process of forming the conductive layer 10, a conductive material layer easily exists in the gap of the separation layer 13, and when the semiconductor structure works, the conductive layer 10 is easily subjected to a leakage condition, so that the electrical performance of the semiconductor structure is poor.
In order to solve the technical problem, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate; forming a pattern material layer on the substrate; performing a plurality of groove forming steps on the pattern material layer, sequentially forming grooves at a plurality of positions of the pattern material layer, and using the remaining pattern material layer as the pattern layer, wherein the groove forming step comprises: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer positioned on the top surface of the pattern material layer is used as a protective layer; removing the second mask layer; and after the pattern layer is formed, removing the protective layer.
In the method for forming a semiconductor structure provided by the embodiment of the invention, in the step of forming the groove, a mask layer is formed on the pattern material layer, the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, the second mask layer is provided with an opening, the pattern material layer is etched by taking the second mask layer as a mask, a groove is formed in the pattern material layer, the first mask layer positioned on the top surface of the pattern material layer is taken as a protective layer, so that the top surface of the pattern material layer covered by the protective layer is not exposed in the process of forming the groove, and the material of the corresponding junction area between the top surface of the pattern material layer and the side wall of the groove is not easily damaged; after the pattern layer is formed, the protective layer is removed, so that materials of the top surface of the pattern layer and the junction area of all groove side walls are damaged only once, the chamfer angle of the top of the groove side wall is small, gaps are not prone to exist at the top of a top mask layer formed in the groove subsequently, the pattern layer is removed, the top mask layer is used as a mask to etch the substrate, a residual substrate and an isolation layer located on the residual substrate are formed, gaps are not prone to exist at the top of the isolation layer, a conducting layer is formed on the residual substrate between the isolation layers, conducting materials forming the conducting layer are not prone to being deposited at the top of the isolation layer, the probability of conducting layer leakage current is favorably reduced, and the electrical performance of a semiconductor structure is.
In order to make the aforementioned objects, features and advantages of the embodiments of the present invention comprehensible, specific embodiments accompanied with figures are described in detail below.
Fig. 11 to 21 are schematic structural diagrams corresponding to steps in an embodiment of a method for forming a semiconductor structure of the present invention.
Referring to fig. 11, a substrate is provided.
The substrate provides a process foundation for the subsequent formation of the conductive layer.
In this embodiment, the material of the substrate includes a dielectric layer 100, a first buffer material layer 101 located on the dielectric layer 100, a hard mask layer 102 located on the first buffer material layer 101, and a second buffer material layer 103 located on the hard mask layer 102.
And subsequently etching the dielectric layer 100 to form a residual substrate and isolation layers on the residual substrate, wherein a conductive layer is formed on the residual substrate between the isolation layers, and the dielectric layer 100 is used for electrically isolating the conductive layer.
In this embodiment, the dielectric layer 100 is made of a low-k dielectric material, which is beneficial to reducing the parasitic capacitance between the conductive layers, and further beneficial to reducing the RC delay of the rear section.
Specifically, the material of the dielectric layer 100 includes SiCOH.
The first buffer material layer 101 is used for reducing stress between the hard mask layer 102 and the dielectric layer 100, and avoids overlarge stress caused by direct contact between the hard mask layer 102 and the dielectric layer 100, so that the hard mask layer 102 is not easy to crack or fall off.
In the present embodiment, the material of the first buffer material layer 101 includes SiOC. In other embodiments, the material of the first buffer material layer may further include silicon oxide.
The hard mask layer 102 is used to prepare the dielectric layer 100 for subsequent etching. The hard mask layer 102 is made of a material having a high etching resistance, and the dielectric layer 100 and the hard mask layer 102 are made of a material having a high etching selectivity ratio in the subsequent etching process of the dielectric layer 100.
Specifically, the hard mask layer 102 is made of TiN or TiO2、HfN、ZrO2And Al2O3One ofOne or more of them. In this embodiment, the material of the hard mask layer 102 includes TiN.
And forming a pattern material layer 104 on the hard mask layer 102, wherein the second buffer material layer 103 is used for reducing the stress between the hard mask layer 102 and the pattern material layer 104, and avoiding overlarge stress caused by direct contact between the pattern material layer 104 and the hard mask layer 102, so that the pattern material layer 104 is not easy to crack or fall off.
In this embodiment, the material of the second buffer material layer 103 includes TEOS (tetraethyl orthosilicate, also called ethyl silicate). In other embodiments, the material of the second buffer material layer may further include silicon oxide.
It should be noted that the substrate further includes a gate structure, and source and drain doped regions located at two sides of the gate structure, and a contact hole plug (not shown in the figure) contacting the source and drain doped regions is further formed in the substrate.
Referring to fig. 12 in conjunction with fig. 11, fig. 12 is a view of fig. 11 in the direction C, with a patterned material layer 104 formed on the substrate.
The patterned material layer 104 provides for the subsequent formation of a patterned layer.
In this embodiment, the material of the graphic material layer 104 includes: silicon. In other embodiments, the material of the graphic material layer may further include: silicon oxide, silicon nitride, or silicon oxynitride.
In this embodiment, the step of forming the pattern material layer 104 includes: forming a film of a pattern material (not shown in the figure) on the substrate; forming a mask layer (not shown in the figure) on the pattern material film; and etching the pattern material film by taking the mask layer as a mask, wherein the residual pattern material film is taken as a pattern material layer 104.
In other embodiments, the pattern material layer may be formed by Self-Aligned Double Patterning (SADP) or Self-Aligned quadruple Patterning (SAQP).
Referring to fig. 13 to 18, the pattern material layer 104 is subjected to a plurality of groove forming steps to form grooves 105 at a plurality of positions of the pattern material layer 104 in sequence, and the remaining pattern material layer 104 serves as a pattern layer 112, the groove forming steps including: forming a mask layer 106 on the pattern material layer 104, wherein the mask layer 106 comprises a first mask layer 108 and a second mask layer 109 located on the first mask layer 108, and the second mask layer 109 has an opening 107; etching the pattern material layer 104 by using the second mask layer 109 as a mask, forming a groove 105 in the pattern material layer 104, and using the remaining first mask layer 108 on the top surface of the pattern material layer 104 as a protective layer 111; the second mask layer 109 is removed.
In the step of forming the groove, a mask layer 106 is formed on the pattern material layer 104, the mask layer 106 includes a first mask layer 108 and a second mask layer 109 located on the first mask layer 108, the second mask layer 109 has an opening 107, the pattern material layer 104 is etched by using the second mask layer 109 as a mask, a groove 105 is formed in the pattern material layer 104, the first mask layer 108 located on the top surface of the pattern material layer 104 is used as a protection layer 111, so that the top surface of the pattern material layer 104 covered by the protection layer 111 is not exposed in the process of forming the groove 105, and the material of the corresponding boundary area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is not easily damaged; after the pattern layer 112 is formed, the protective layer 111 is removed, so that materials of the top surface of the pattern layer 112 and the boundary area of all the side walls of the groove 105 are damaged only once, the chamfer angle of the top of the side wall of the groove 105 is small, gaps are not prone to exist at the top of a top mask layer formed in the groove 105 subsequently, the pattern layer 112 is removed, the top mask layer is used as a mask to etch the substrate, a residual substrate and an isolation layer located on the residual substrate are formed, gaps are not prone to exist at the top of the isolation layer, a conducting layer is formed on the residual substrate between the isolation layers, conducting materials forming the conducting layer are not prone to be deposited at the top of the isolation layer, the probability of conducting layer leakage current is favorably reduced, and the electrical performance.
Specifically, the groove forming step includes:
as shown in fig. 13, a mask layer 106 is formed on the pattern material layer 104, where the mask layer 106 includes a first mask layer 108 and a second mask layer 109 on the first mask layer 108, and the second mask layer 109 has an opening 107.
In the subsequent process, the mask layer 106 is used as a mask to etch the pattern material layer 102, so as to form a pattern layer.
In this embodiment, a first mask layer 108 is disposed in the mask layer 106 and in contact with the pattern material layer 102, and the material of the first mask layer 108 includes an organic material layer.
The material of the first mask layer 108 includes an organic material layer. After the pattern layer is formed subsequently, in the process of removing the mask layer 106 on the pattern layer, the damage to the pattern layer is small.
Specifically, the organic material layer includes: SOC (spin on carbon) material or SOH (spin on hard mask) material. In other embodiments, the organic material layer may further include one or more of an ODL (organic dielectric layer) material, a DUO (Deep UV Light Absorbing Oxide) material, and an APF (Advanced Patterning Film) material.
In other embodiments, the first mask layer may also be other materials that can act as a mask and are easy to remove, so that damage to the patterned material layer is reduced when the mask layer is subsequently removed, for example: one or more of silicon oxycarbide, tetraethylorthosilicate, polycrystalline silicon, and oxygen-doped silicon carbide.
In this embodiment, the first mask layer 108 is formed by a spin-on process. The surface flatness of the first mask layer 108 is high.
In this embodiment, the second mask layer 109 includes a bottom anti-reflective coating (BARC) layer 1091 and a photoresist layer 1092 on the BARC layer 1091.
Specifically, the opening 107 is located in the photoresist layer 1092.
The step of forming the opening 107 includes: forming a photoresist material layer (not shown) on the BARC 1091; and exposing the photoresist material layer, forming an opening 107 in the photoresist material layer, and using the residual photoresist material layer as a photoresist layer 1092.
As shown in fig. 14 to 16, the second mask layer 109 is used as a mask to etch the pattern material layer 104, a groove 105 is formed in the pattern material layer 104, and the first mask layer 108 on the top surface of the pattern material layer 104 is used as a protection layer 111.
In this embodiment, the pattern material layer 104 is etched by a dry etching process, and a groove 105 is formed in the pattern material layer 104. The dry etching process has anisotropic etching characteristics and better etching profile controllability, is beneficial to enabling the appearance of the groove 105 to meet the process requirements, and can etch the bottom anti-reflection coating 1091 and the pattern material layer 104 in the same etching equipment by replacing etching gas, thereby simplifying the process steps. In addition, in the etching process, the top of the substrate can be used as an etching stop position, and damage to other film layer structures is reduced.
Specifically, the mask layer 106 is used as a mask, and the pattern material layer 104 is etched by using an anisotropic Reactive Ion Etching (RIE) process, so as to form the groove 105 in the pattern material layer 104. In the process of the anisotropic reactive ion etching process, a large number of chemically active gas ions exist in plasma generated by gas discharge, and the ions interact with the surface of a material to cause surface atoms to generate chemical reaction, so that the etching effect is achieved. The reactive ion etching process is beneficial to reducing the damage to the top of the substrate in the process of etching and forming the groove 105.
It should be noted that, in this embodiment, in the step of etching the pattern material layer 104 and forming the groove 105 in the pattern material layer 104, the second mask layer 109 is removed.
As shown in fig. 15 and 16, fig. 16 is a cross-sectional view of fig. 15 in the direction DD, and in this embodiment, the step of forming the protective layer 111 further includes: after the groove 105 is formed, the first mask layer 108 with a partial thickness on the top surface of the pattern material layer 104 is etched, and the remaining first mask layer 108 on the top surface of the pattern material layer 104 serves as a protection layer 111. In other embodiments, after the forming of the groove, the thickness of the first mask layer on the top surface of the pattern material layer is smaller, and the first mask layer with a partial thickness on the top surface of the pattern material layer may not be etched.
After the groove 105 is formed, the first mask layer 108 with the partial thickness of the top surface of the pattern material layer 104 is etched, so that the first mask layer 108 on the top surface of the pattern material layer 104 is not too thick, that is, the protective layer 111 on the top surface of the pattern material layer 104 is not too thick, and in the groove forming step performed at the next time, the film layer structure on the pattern material layer 104 is not too thick, so that the pattern material layer 104 is not easy to deform or bend.
In this embodiment, the material of the first mask layer 108 includes an organic material layer. Correspondingly, the first mask layer 108 is etched by an ashing process to form the protection layer 111.
The process parameters for etching a portion of the thickness of the first mask layer 108 by using an ashing process include: the reaction gas comprises O2And N2The carrier gas includes one or both of Ar and He.
In the step of forming the protective layer 111 by etching a part of the first mask layer 108 by using an ashing process, the flow rate of the reaction gas should not be too large or too small. If the flow of the reaction gas is too large, the pressure in the reaction chamber is easily caused to be too large, the etching rate of the first mask layer 108 on the top surface of the pattern material layer 104 is too fast, the process controllability and the reaction rate uniformity of etching are reduced, and the top surface of the pattern material layer 104 is easily damaged, so that the boundary area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is easily damaged, the chamfer angle of the boundary area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is easily enlarged, a gap is easily formed at the top of the top mask layer formed in the groove 105 subsequently, the pattern layer is removed, the top mask layer is used as a mask to etch the substrate to form a residual substrate and an isolation layer located on the residual substrate, the gap is easily formed at the top of the isolation layer, a conductive layer is formed on the residual substrate between the isolation layers, and the conductive, it is not favorable to reduce the probability of the leakage current of the conductive layer. The flow of the reaction gas is too small, which easily causes the pressure in the reaction chamber to be too small, and the etching rate of the first mask layer 108 for etching the top surface of the pattern material layer 104 is too slow, which is not favorable for increasing the formation rate of the protection layer 111. In this embodiment, in the step of forming the protection layer 111 by etching a part of the first mask layer 108 by using an ashing process, the flow rate of the reaction gas is 50 seem to 300 seem.
In the step of forming the protective layer 111 by etching a part of the first mask layer 108 by using an ashing process, the chamber pressure should not be too high or too low. If the chamber pressure is too high, the decomposition rate of the by-product generated by etching the first mask layer 108 on the top surface of the pattern material layer 104 is too slow, correspondingly, the rate of the by-product discharged from the chamber is too slow, and the chamber pressure is too high, which also easily causes the high etching rate of the carrier 200 exposed by the etching gas etching the second mask layer 205, reduces the process controllability and the reaction rate uniformity of the etching, and easily causes damage to the top surface of the pattern material layer 104, so that the boundary area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is easily damaged, the chamfer angle of the boundary area between the top surface of the pattern material layer 104 and the side wall of the groove 105 is easily increased, a gap is easily formed at the top of the top mask layer formed in the groove 105 subsequently, the pattern layer is removed, the top mask layer is used as a mask etching substrate, and a residual substrate and, gaps are easy to exist at the tops of the isolation layers, a conducting layer is formed on the residual substrate between the isolation layers, and conducting materials for forming the conducting layer are easy to deposit at the tops of the isolation layers, so that the probability of current leakage of the conducting layer is not reduced. If the chamber pressure is too low, the plasma density of the etching gas in the chamber is low, which easily results in a low etching rate of the first mask layer 108 on the top surface of the pattern material layer 104, and is not favorable for increasing the formation rate of the protective layer 111. In this embodiment, in the step of forming the protection layer 111 by etching a part of the first mask layer 108 with a thickness by using an ashing process, the chamber pressure is 5mTorr to 30 mTorr.
In other embodiments, in the step of forming the groove in the pattern material layer by an etching process, the second mask layer may also have a residue. Correspondingly, in the step of etching the first mask layer with the thickness of the part of the top surface of the pattern material layer, the second mask layer is removed.
In other embodiments, when the material of the first mask layer includes one or more of silicon oxycarbide, tetraethoxysilane, polysilicon and oxygen-doped silicon carbide, the first mask layer is etched by a dry etching process to a thickness of a top surface portion of the pattern material layer, so as to form the protective layer.
As shown in fig. 17 and 18, fig. 18 is a cross-sectional view in the EE direction of fig. 17, and the pattern material layer 102 is subjected to a groove forming step a plurality of times, and grooves 105 are formed in a plurality of positions of the pattern material layer 102 in sequence, and the remaining pattern material layer 104 serves as a pattern layer 112.
The recess 105 provides for a subsequent formation of a top mask layer on the substrate between the patterned layers 112.
It should be noted that, in the step of forming the groove, the protective layer 111 on the top surface of the pattern material layer 104 is not too thick or too thin. In the next step of forming the groove, a mask layer is formed on the pattern material layer 104, if the protective layer 111 on the top surface of the pattern material layer 104 is too thick, the mask layer is formed on the protective layer 111, then the film layer on the top surface of the pattern material layer 104 is too thick, the pattern material layer 104 is easy to bend or incline, so that the forming quality of the groove 105 is poor, the appearance quality of the top mask layer correspondingly filled in the groove 105 is poor, after the pattern layer 104 is subsequently removed, the quality of an isolation layer formed by etching the substrate by taking the top mask layer as a mask is poor, and the isolation layer cannot well play a role of electrically isolating the conducting layer. If the protective layer 111 on the top surface of the pattern material layer 104 is too thin, the protective layer 111 is formed by etching the first mask layer 108 to a certain thicknessThe top of the pattern material layer 104 is easily damaged, so that the forming quality of the groove 105 is poor, after the pattern layer 104 is removed subsequently, the quality of an isolation layer formed by etching the substrate by taking the top mask layer as a mask is poor, and the isolation layer cannot well play a role in electrically isolating the conducting layer. In this embodiment, in the step of forming the groove, the thickness of the protective layer 111 on the top surface of the pattern material layer 104 is
To
Referring to fig. 19, after the pattern layer 112 is formed, the protective layer 111 is removed.
After the pattern layer 112 is formed, the protective layer 111 is removed, so that materials of the top surface of the pattern layer 112 and the boundary area of all the side walls of the groove 105 are damaged only once, the chamfer angle of the top of the side wall of the groove 105 is small, gaps are not prone to exist at the top of a top mask layer formed in the groove 105 subsequently, the pattern layer 112 is removed, the top mask layer is used as a mask to etch the substrate, a residual substrate and an isolation layer located on the residual substrate are formed, gaps are not prone to exist at the top of the isolation layer, a conducting layer is formed on the residual substrate between the isolation layers, conducting materials forming the conducting layer are not prone to be deposited at the top of the isolation layer, the probability of conducting layer leakage current is favorably reduced, and the electrical performance.
The protective layer 111 is removed to provide a space for forming a top mask layer on the substrate between the pattern layers 112.
In this embodiment, the material of the protection layer 111 includes an organic material layer, and the protection layer 111 is removed by an ashing process. In other embodiments, the protective layer may be removed by a dry etching process.
In the step of removing the protective layer 111 by using an ashing process, the pattern layer 112 is less damaged.
Referring to fig. 20, the method for forming the semiconductor structure further includes: after removing the protection layer 111, a top mask layer 113 is formed in the groove 105.
The top mask layer 113 serves as an etch mask for subsequent etching of the substrate.
In this embodiment, the material of the top mask layer 113 includes silicon nitride. Silicon nitride has higher process compatibility and is a material which is commonly used in the process and has lower cost.
The step of forming a top mask layer 113 in the recess 105 comprises: conformally covering the pattern layer 112 and a top masking material layer (not shown) on the substrate between the pattern layer 112; and removing the top mask material layer higher than the pattern layer 112, wherein the top mask material layer remaining in the groove 105 is used as a top mask layer 113.
In this embodiment, the top mask material layer is formed by an Atomic Layer Deposition (ALD) process. The atomic layer deposition process comprises multiple atomic layer deposition cycles, which is beneficial to improving the thickness uniformity of the top mask material layer and enables the thickness of the top mask material layer to be accurately controlled; in addition, the gap filling performance and the step coverage of the atomic layer deposition process are good, the probability of the occurrence of a cavity in the top mask material layer is reduced, and the forming quality of the top mask layer 113 is correspondingly improved. In other embodiments, the top mask material layer may be formed by a Chemical Vapor Deposition (CVD) process.
In this embodiment, a Chemical Mechanical Polishing (CMP) process is used to remove the top mask material layer above the pattern layer 112. The cmp process is a global surface planarization technique that can accurately and uniformly remove the top mask material layer above the pattern layer 112.
It should be noted that the top of the sidewall of the groove 105 is chamfered less, so that the top of the top mask layer 113 is not prone to have a gap (team).
Referring to fig. 21, the method of forming the semiconductor structure further includes: removing the pattern layer 112, and etching the substrate by using the top mask layer 113 as a mask to form a residual substrate 115 and an isolation layer 116 located on the residual substrate 115; a conductive layer 114 is formed in the remaining substrate 115 between the isolation layers 116.
The top of the top mask layer 113 is not prone to having a gap, so that in the process of etching the substrate by using the top mask layer 113 as a mask, the top of the formed isolation layer 116 is not prone to having a gap, and correspondingly, in the process of forming the conductive layer 114, the top of the isolation layer 116 is not prone to forming a conductive material, so that the probability of leakage current of the conductive layer 114 is favorably reduced, and the electrical performance of the semiconductor structure is improved.
Specifically, the remaining substrate 115 and the isolation layer 116 are formed by etching the dielectric layer 100.
The dielectric layer 100 is a low-K dielectric material, and correspondingly, the isolation layer 116 is also a low-K dielectric material.
The isolation layer 116 serves to electrically isolate the conductive layers 114 and can reduce capacitive coupling effects between the conductive layers 114.
The conductive layer 114 is used as an interconnect structure.
In this embodiment, the material of the conductive layer 114 is Cu. In other embodiments, the conductive layer may be made of conductive material such as TaN, TiN, or Co.
The step of forming the conductive layer 114 includes: forming a layer of conductive material on the spacer layer 116 and the remaining substrate 115 between the spacer layer 116; the conductive material layer above the isolation layer 116 is removed, and the remaining conductive material layer serves as a conductive layer 114.
In this embodiment, the conductive material layer is formed by an electrochemical plating process. The electrochemical plating process has the advantages of simple operation, high deposition speed, low price and the like.
In this embodiment, a wet etching process is used to remove the pattern layer 112, so as to form a trench surrounded by the top mask layer 113 and the substrate. The wet etching process has the advantages of high etching rate, simple operation and low process cost.
The material of the pattern layer 112 comprises silicon, and the material of the second buffer material layer 103 on top of the substrate comprises TEOS. Accordingly, the etching solution used in the wet etching process includes a tetramethylammonium hydroxide (TMAH) solution. The etching rate of the tetramethylammonium hydroxide solution to Si is greater than that to TEOS material.
The method for forming the semiconductor structure further includes: after the remaining substrate 115 and the isolation layer 116 are formed, and before the conductive material layer is formed, the remaining first buffer material layer 101, the hard mask layer 102, and the second mask layer 103 are removed.
Accordingly, with continued reference to fig. 21, an embodiment of the invention further provides a transistor formed by the foregoing formation method.
The transistor includes: the remaining substrate 115; an isolation layer 116 separated from the remaining substrate 115; a conductive layer 114 on the remaining substrate 115 between the isolation layers 116.
In the transistor, a gap is not easy to exist at the top of the isolation layer 116, and in the corresponding process of forming the conductive layer 114, a conductive material is not easy to form at the top of the isolation layer 116, so that the probability of leakage current of the conductive layer 114 is reduced, and the electrical performance of the transistor is improved.
The isolation layer 116 serves to electrically isolate the conductive layer 114.
In this embodiment, the isolation layer 116 is made of a low-k dielectric material, which is beneficial to reducing the parasitic capacitance between the conductive layers 114, and further beneficial to reducing the rear-stage RC delay.
Specifically, the material of the isolation layer 116 includes SiCOH.
It should be noted that the bottom of the remaining substrate further includes a gate structure and source-drain doped regions located at two sides of the gate structure, and a contact hole plug (not shown in the figure) contacting the source-drain doped regions is further formed in the substrate.
The conductive layer 114 is used as an interconnect structure.
In this embodiment, the material of the conductive layer 114 is Cu. In other embodiments, the conductive layer may be made of conductive material such as TaN, TiN, or Co.
The semiconductor structure of this embodiment may be formed by the formation method described in the foregoing embodiment, or may be formed by other formation methods. For a detailed description of the semiconductor structure in this embodiment, reference may be made to the corresponding description in the foregoing embodiments, and details of this embodiment are not repeated herein.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be effected therein by one skilled in the art without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (15)
1. A method of forming a semiconductor structure, comprising:
providing a substrate;
forming a pattern material layer on the substrate;
performing a plurality of groove forming steps on the pattern material layer, sequentially forming grooves at a plurality of positions of the pattern material layer, and using the remaining pattern material layer as the pattern layer, wherein the groove forming step comprises: forming a mask layer on the pattern material layer, wherein the mask layer comprises a first mask layer and a second mask layer positioned on the first mask layer, and the second mask layer is provided with an opening; etching the pattern material layer by taking the second mask layer as a mask, and forming a groove in the pattern material layer; the first mask layer positioned on the top surface of the pattern material layer is used as a protective layer; removing the second mask layer;
and after the pattern layer is formed, removing the protective layer.
2. The method of forming a semiconductor structure of claim 1, wherein in the step of forming the recess, the protective layer on the top surface of the patterned material layer has a thickness of
To
3. The method for forming a semiconductor structure according to claim 1, wherein in the step of forming the recess, the second mask layer is removed;
the step of forming the protective layer further comprises: and etching the first mask layer with partial thickness on the top surface of the pattern material layer after the groove is formed, wherein the first mask layer which is positioned on the top surface of the pattern material layer and is left serves as a protective layer.
4. The method of forming a semiconductor structure of claim 1, wherein forming the protective layer further comprises: after the groove is formed, etching the first mask layer with partial thickness on the top surface of the pattern material layer, wherein the first mask layer which is remained on the top surface of the pattern material layer is used as a protective layer;
and in the step of etching the first mask layer with the partial thickness of the top surface of the pattern material layer, removing the second mask layer.
5. The method as claimed in claim 3 or 4, wherein the protective layer is formed by etching the first mask layer with a thickness of a portion of the top surface of the pattern material layer by an ashing process.
6. The method of claim 5, wherein the process parameters for etching a portion of the thickness of the first mask layer using an ashing process comprise: the reaction gas comprises O2And N2The carrier gas comprises one or two of Ar and He, the flow rate of the reaction gas is 50sccm to 300sccm, and the pressure of the chamber is 5mTorr to 30 mTorr.
7. The method for forming a semiconductor structure according to claim 3 or 4, wherein a material of the protective layer includes an organic material layer.
8. The method of forming a semiconductor structure of claim 7, wherein the material of the organic material layer comprises: one or more of SOC materials, SOH materials, ODL materials, DUO materials, and APF materials.
9. The method according to claim 3 or 4, wherein the material of the first mask layer comprises one or more of silicon oxycarbide, tetraethoxysilane, polysilicon and oxygen-doped silicon carbide.
10. The method for forming a semiconductor structure according to claim 9, wherein the protective layer is formed by etching the first mask layer with a thickness of a portion of the top surface of the pattern material layer by a dry etching process.
11. The method of claim 1, wherein the first mask layer comprises a bottom anti-reflective coating and a photoresist layer on the bottom anti-reflective coating.
12. The method of forming a semiconductor structure of claim 11, wherein the opening is in the photoresist layer.
13. The method for forming a semiconductor structure according to claim 1, wherein the mask layer is used as a mask, and the pattern material layer is etched by an anisotropic reactive ion etching process to form the recess in the pattern material layer.
14. The method of forming a semiconductor structure of claim 1, further comprising: after the protective layer is removed, a top mask layer is formed in the groove;
removing the pattern layer, and etching the substrate by taking the top mask layer as a mask to form a residual substrate and an isolation layer positioned on the residual substrate;
and forming a conductive layer on the residual substrate between the isolation layers.
15. The method of forming a semiconductor structure of claim 1, wherein the substrate comprises a dielectric layer.
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| CN104124137A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN105719956A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN108470678A (en) * | 2018-03-29 | 2018-08-31 | 德淮半导体有限公司 | Semiconductor structure and forming method thereof |
| CN109585279A (en) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | A kind of forming method of autoregistration bilayer figure |
| CN109755175A (en) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | interconnection structure and forming method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124137A (en) * | 2013-04-28 | 2014-10-29 | 中芯国际集成电路制造(上海)有限公司 | Semiconductor device forming method |
| CN105719956A (en) * | 2014-12-04 | 2016-06-29 | 中芯国际集成电路制造(上海)有限公司 | Formation method of semiconductor structure |
| CN109755175A (en) * | 2017-11-03 | 2019-05-14 | 中芯国际集成电路制造(上海)有限公司 | interconnection structure and forming method thereof |
| CN108470678A (en) * | 2018-03-29 | 2018-08-31 | 德淮半导体有限公司 | Semiconductor structure and forming method thereof |
| CN109585279A (en) * | 2018-11-30 | 2019-04-05 | 上海华力微电子有限公司 | A kind of forming method of autoregistration bilayer figure |
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