CN113110858B - FPGA system online upgrading method based on PCRAM - Google Patents

Abstract

The application relates to the technical field of electronic information, in particular to a FPGA system online upgrading method based on PCRAM. The traditional FPGA configuration updating method has the problems of slow writing speed and short service life due to the adoption of a nonvolatile memory FLASH. The application uses the nonvolatile phase change memory (PCRAM) to replace FLASH, and since the PCRAM has the characteristics of random read-write capability, high read-write speed and long service life compared with FLASH, the calculation and storage can be directly carried out in the PCRAM. The FPGA system based on the PCRAM is upgraded on line, so that the upgrading speed can be increased, the upgrading power consumption can be reduced, and the upgrading times can be increased. The method and the device are applied to the on-line upgrading of the FPGA system, have the good technical effects of high speed, low energy consumption and prolonged service life of equipment, are concise and optimized in the upgrading process, and are suitable for popularization and application in the technical field of telecommunication.

Description

FPGA system online upgrading method based on PCRAM

Technical Field

The application relates to the technical field of electronic information, in particular to an FPGA system online upgrading method based on PCRAM.

Background

In recent years, with the increasing complexity of the operation content of electronic products, the real-time requirement of the operation is also increasing, and more systems use the FPGA to perform the operation processing. In the hybrid operation of a complex system, the FPGA needs to process various algorithms and functions after scheduling. For example, in a road monitoring system, when a vehicle traffic violation is found, an FPGA system is required to be called to execute a license plate recognition function; when the road is found to be lost, the FPGA system is required to be called to complete the function of identifying the lost object. Thus requiring the FPGA to adapt to the processing requirements of different algorithms through online configuration updates. In addition, the complex neural network model needs to be optimized through continuous iterative computation, so that after receiving an initial neural network model configuration, the MCU needs to perform iterative computation optimization first and then perform configuration updating on the FPGA.

In the prior art, the configuration updating method of the FPGA is mainly divided into two modes, namely active configuration and passive configuration:

1. in the active configuration mode, the configuration file is stored in a nonvolatile memory, usually FLASH. The FPGA actively reads the configuration file in the nonvolatile memory to complete the updating of the configuration;

2. and the configuration file in the passive configuration mode is still stored in the nonvolatile memory, the central processing unit reads the file in the nonvolatile memory, and then the central processing unit sends the configuration file to the FPGA from the configuration pins in a mode of meeting the time sequence of the FPGA to complete the updating of the configuration.

The two configuration modes are both used for the nonvolatile memory, and the traditional nonvolatile memory FLASH has the problems that only the whole sector can be erased and written, the writing speed is low, and the service life is short. This will directly impact the speed, power consumption and lifetime of an FPGA upgrade. Some complex neural network models require the controller to continuously update parameters in the model in the process of calling the operation model for calculation, but because FLASH cannot support real-time updating, the initial model in FLASH can only be read into RAM under normal conditions, the controller performs iterative calculation from the RAM, and writes back the FLASH after the model converges, and then performs configuration updating on FPGA. The method needs the RAM to store more than FLASH, but when the complex calculation model is large in size, the cost is increased by using the SRAM, and the power consumption is greatly increased by using the DRAM.

Disclosure of Invention

The application provides an FPGA system online upgrading method based on PCRAM, which aims to solve the problems of low speed, high power consumption and short service life of equipment in the current FPGA configuration updating and upgrading method.

The technical scheme adopted by the application is as follows:

an FPGA system online upgrading method based on PCRAM comprises the following steps:

judging whether the FPGA system is in an MCU operation state or not;

if yes, then:

s101, updating a configuration file of the FPGA;

s102, the MCU reads a pre-stored FPGA configuration file from the PCRAM or receives the FPGA configuration file from an external interface;

s103, writing the FPGA configuration file into an FPGA configuration updating area of the PCRAM by the MCU, and releasing the bus control right by the MCU after the completion;

s104, the MCU pulls down the FPGA reset pin and then pulls up the pin to reset the FPGA, and the FPGA configuration file is automatically read from the FPGA configuration update area of the PCRAM and the configuration is updated after the FPGA is reset;

s105, judging whether an error occurs in the FPGA updating configuration process, if no error occurs, completing online upgrade, if the configuration is wrong, pulling down an FPGA reset pin by the MCU, then pulling up the reset pin to reset the FPGA, then performing updating configuration again, and confirming that the FPGA updating configuration is completed by the MCU through the configuration completion pin;

if not, then:

s201, the MCU is powered on firstly, the reset pin of the FPGA is controlled to be at a low level, the bus control right is obtained, and the PCRAM is initialized;

s202, the initialization of the PCRAM is completed, and the MCU releases the bus control right after reading the starting data from the PCRAM;

s203, the MCU controls the reset pin of the FPGA to be at a high level;

s204, the FPGA acquires the bus control right, and automatically reads and updates the configuration from the PCRAM;

s205, judging whether an error occurs in the FPGA updating configuration process, and if no error occurs, finishing online upgrading; if the configuration is wrong, the MCU pulls down the FPGA reset pin and then pulls up the pin to reset the FPGA, and then the configuration is updated again.

Optionally, in step S103, the method includes:

and the MCU writes the FPGA configuration file into an FPGA configuration updating area of the PCRAM, directly calculates in the PCRAM if local iterative calculation optimization is required, and releases the bus control right after calculation.

Optionally, in step S105, it is determined whether there is an error in the FPGA configuration updating process, and if there is no error, the bus control right is released after the configuration is completed, and the MCU is notified through the configuration completion pin, so that the online upgrade is completed.

Optionally, after step S105, the method further includes:

and the MCU acquires the bus control right after confirming that the FPGA finishes updating configuration through the configuration finishing pin.

Optionally, after step S205, the method further includes:

and the MCU acquires the bus control right after confirming that the FPGA finishes updating configuration through the configuration finishing pin.

Optionally, in the step S205, the method includes:

and judging whether an error occurs in the FPGA updating configuration process, if no error occurs, releasing the bus control right after the configuration is finished, and informing the MCU through a configuration finishing pin to finish the online upgrade.

The technical scheme of the application has the following beneficial effects:

the application uses the nonvolatile phase change memory (PCRAM) to replace FLASH, and the PCRAM has the obvious advantages of random reading and writing, high reading and writing speed and long service life compared with FLASH, so that the application becomes a research hotspot and can be directly calculated and stored in the PCRAM. The PCRAM is adopted to support the FPGA system for online upgrading, so that the upgrading speed can be obviously improved, the upgrading power consumption is reduced, and the upgrading times are increased. In the face of complex neural network model configuration requiring MCU to perform local optimization, iterative computation can be directly performed in PCRAM to optimize the model configuration. And after the model is optimized, the FPGA directly loads the configuration from the PCRAM. The method and the device are applied to the on-line upgrading of the FPGA system, have the good technical effects of high speed, low energy consumption and prolonged service life of equipment, are concise and optimized in the upgrading process, and are suitable for popularization and application in the technical field of telecommunication.

Drawings

In order to more clearly explain the technical solution of the present application, the drawings needed to be used in the embodiments will be briefly described below, and it is obvious to those skilled in the art that other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a block flow diagram of one embodiment of the present application;

FIG. 2 is a configuration diagram of a BPI Master configuration MODE MODE [ 2;

FIG. 3 is a schematic diagram of an FPGA system online upgrade architecture according to an embodiment of the present application;

fig. 4 is a block flow diagram of another embodiment of the present application.

Detailed Description

Reference will now be made in detail to embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following examples do not represent all embodiments consistent with the present application. But merely as examples of systems and methods consistent with certain aspects of the application, as detailed in the claims.

Referring to fig. 1, a flow chart of an embodiment of the present application is shown to facilitate understanding of the essence of the following embodiment.

The application provides an FPGA system online upgrading method based on PCRAM, which comprises the following steps:

judging whether the FPGA system is in an MCU operation state or not;

if yes, then:

s101, updating a configuration file of the FPGA;

s102, the MCU reads a pre-stored FPGA configuration file from the PCRAM or receives the FPGA configuration file from an external interface;

s103, the MCU writes the FPGA configuration file into an FPGA configuration updating area of the PCRAM, and releases the bus control right after the completion;

s104, the MCU pulls down the FPGA reset pin and then pulls up the pin to reset the FPGA, and the FPGA automatically reads the FPGA configuration file from the FPGA configuration update area of the PCRAM and updates the configuration after the FPGA is reset;

s105, judging whether an error occurs in the FPGA updating configuration process, if no error occurs, completing online upgrade, if the configuration is wrong, pulling down an FPGA reset pin by the MCU, then pulling up the FPGA reset pin to reset the FPGA, then performing updating configuration again, and confirming that the FPGA updating configuration is completed by the MCU through the configuration completion pin;

if not, then:

s201, the MCU is powered on first, the reset pin of the FPGA is controlled to be at a low level, a bus control right is obtained, and the PCRAM is initialized;

s202, the initialization of the PCRAM is completed, and the MCU releases the bus control right after reading the starting data from the PCRAM;

s203, the MCU controls the reset pin of the FPGA to be at a high level;

s204, the FPGA acquires the bus control right, and automatically reads and updates the configuration from the PCRAM;

s205, judging whether an error occurs in the FPGA updating configuration process, and if no error occurs, finishing online upgrading; if the configuration is wrong, the MCU pulls down the FPGA reset pin and then pulls up the pin to reset the FPGA, and then the configuration is updated again.

Optionally, in step S103, the method includes:

and the MCU writes the FPGA configuration file into an FPGA configuration updating area of the PCRAM, directly calculates in the PCRAM if local iterative calculation optimization is required, and releases the bus control right after calculation.

Optionally, in step S105, it is determined whether there is an error in the FPGA configuration updating process, and if there is no error, the bus control right is released after the configuration is completed, and the MCU is notified through the configuration completion pin, so that the online upgrade is completed.

Optionally, after step S105, the method further includes:

and the MCU acquires the bus control right after confirming that the FPGA finishes updating configuration through the configuration finishing pin.

Optionally, after step S205, the method further includes:

and the MCU acquires the bus control right after confirming that the FPGA finishes updating configuration through the configuration finishing pin.

Optionally, in the step S205, the method includes:

and judging whether an error occurs in the FPGA updating configuration process, if no error occurs, releasing the bus control right after the configuration is finished, and informing the MCU through a configuration finishing pin to finish the online upgrade.

Specific test examples:

the PGL22G6CMBG32 model FPGA created by purple light is explained in detail, and referring to table 1, the FPGA hardware control pins are as follows:

TABLE 1 BPI Master interface Signal description of FPGA

1. Set MODE [ 2.

2. The MCU controls the FPGA to reset and update the configuration by controlling the RST _ N pin.

3. After the FPGA is configured, the MCU judges whether configuration errors occur or not by reading INIT _ FLAG _ N pin level.

4. The MCU confirms whether the FPGA configuration is finished or not by reading the CFG _ DONE pin level.

Fig. 3 is an online upgrade architecture diagram of the FPGA system of this embodiment, where the entire system mainly includes an MCU, a PCRAM, and an FPGA, and an interface supports an external RAM.

Fig. 4 is a flowchart of an on-line upgrade process of the FPGA system, and the specific process is as follows:

1. and powering on the MCU, enabling the RST _ N pin to be at a low level, and initializing and reading the PCRAM after the MCU is powered on.

2. After the MCU finishes operating the PCRAM, controlling the RST _ N pin to be at a high level, resetting the FPGA, reading and updating configuration from a corresponding space of the PCRAM, if the INIT _ FLAG _ N pin is at a low level in the configuration process, making configuration errors, pulling down the RST _ N pin again by the MCU, and then pulling up the RST _ N pin again, so that the FPGA is configured after resetting again; and if the INIT _ FLAG _ N pin is always in a high level in the configuration process, the FPGA configuration is finished and the running state is entered until the CFG _ DONE pin is in the high level.

3. And after the FPGA enters the running state, waiting for the MCU to give data, and if the MCU gives the calculation data, calculating by the FPGA according to the updated configuration and then transmitting the data back to the MCU.

4. And if the MCU needs to update the FPGA configuration in the running process of the FPGA, the MCU writes the FPGA configuration to be updated into a corresponding area of the PCRAM.

5. The MCU pulls down and then pulls up the RST _ N pin again to reset the FPGA, reads and updates the configuration from the corresponding space of the PCRAM, makes configuration errors if the INIT _ FLAG _ N pin is in a low level in the configuration process, and pulls down and then pulls up the RST _ N pin again to reset and then configures the FPGA; if the INIT _ FLAG _ N pin is always in a high level in the configuration process, the FPGA configuration is finished until the CFG _ DONE pin is in the high level, and the running state is entered again.

The application uses the nonvolatile phase change memory (PCRAM) to replace FLASH, and the PCRAM has the obvious advantages of random reading and writing, high reading and writing speed and long service life compared with FLASH, so that the application becomes a research hotspot and can be directly calculated and stored in the PCRAM. The PCRAM is adopted to support the FPGA system for online upgrading, so that the upgrading speed can be obviously improved, the upgrading power consumption is reduced, and the upgrading times are increased. In the face of complex neural network model configuration requiring MCU to perform local optimization, iterative computation can be directly performed in PCRAM to optimize the model configuration. And after the model is optimized, directly carrying out configuration loading from the PCRAM by the FPGA. The method and the device are applied to the on-line upgrading of the FPGA system, have the good technical effects of high speed, low energy consumption and prolonged service life of equipment, are concise and optimized in the upgrading process, and are suitable for popularization and application in the technical field of telecommunication.

The embodiments provided in the present application are only a few examples of the general concept of the present application, and do not limit the scope of the present application. Any other embodiments that can be extended by the solution according to the present application without inventive efforts will be within the scope of protection of the present application for a person skilled in the art.

Claims (6)

1. An FPGA system online upgrading method based on PCRAM is characterized by comprising the following steps:

judging whether the FPGA system is in an MCU operation state or not;

if yes, then:

s101, updating a configuration file of the FPGA;

s102, the MCU reads a pre-stored FPGA configuration file from the PCRAM or receives the FPGA configuration file from an external interface;

s103, the MCU writes the FPGA configuration file into an FPGA configuration updating area of the PCRAM, and releases the bus control right after the completion;

s104, the MCU pulls down the FPGA reset pin and then pulls up the pin to reset the FPGA, and the FPGA configuration file is automatically read from the FPGA configuration update area of the PCRAM and the configuration is updated after the FPGA is reset;

s105, judging whether an error occurs in the FPGA updating configuration process, if no error occurs, completing online upgrade, if the configuration is wrong, pulling down an FPGA reset pin by the MCU, then pulling up the FPGA reset pin to reset the FPGA, then performing updating configuration again, and confirming that the FPGA updating configuration is completed by the MCU through the configuration completion pin;

if not, then:

s201, the MCU is powered on firstly, the reset pin of the FPGA is controlled to be at a low level, the bus control right is obtained, and the PCRAM is initialized;

s202, the initialization of the PCRAM is completed, and the MCU releases the bus control right after reading the starting data from the PCRAM;

s203, the MCU controls the reset pin of the FPGA to be at a high level;

s204, the FPGA acquires the bus control right, and automatically reads and updates the configuration from the PCRAM;

s205, judging whether an error occurs in the FPGA updating configuration process, and if no error occurs, finishing online upgrading; if the configuration is wrong, the MCU pulls down the FPGA reset pin and then pulls up the pin to reset the FPGA, and then the configuration is updated again.

2. The method for upgrading a FPGA system on line based on PCRAM according to claim 1, wherein in the step S103, the method comprises:

and the MCU writes the FPGA configuration file into an FPGA configuration updating area of the PCRAM, directly calculates in the PCRAM if local iterative calculation optimization is required, and releases the bus control right after calculation.

3. The method for upgrading a FPGA system on line based on PCRAM according to claim 1, wherein in step S105, it is determined whether there is an error in the FPGA configuration updating process, and if there is no error, the bus control right is released after the configuration is completed, and the MCU is notified through a configuration completion pin, so that the online upgrade is completed.

4. The online upgrading method for FPGA system based on PCRAM according to claim 1, further comprising, after the step S105:

and the MCU acquires the bus control right after confirming that the FPGA finishes updating configuration through the configuration finishing pin.

5. The online upgrading method of the FPGA system based on PCRAM according to claim 1,

after the step S205, the method further includes:

and the MCU acquires the bus control right after confirming that the FPGA finishes updating configuration through the configuration finishing pin.

6. The online upgrading method for the FPGA system based on PCRAM according to claim 1, wherein in the step S205, the method comprises:

and judging whether an error occurs in the FPGA updating configuration process, if no error occurs, releasing the bus control right after the configuration is finished, and informing the MCU through a configuration finishing pin to finish the online upgrade.

Images