CN113098537B - Automatic gain control receiver for time division digital communication system - Google Patents
Automatic gain control receiver for time division digital communication system Download PDFInfo
- Publication number
- CN113098537B CN113098537B CN202110368757.6A CN202110368757A CN113098537B CN 113098537 B CN113098537 B CN 113098537B CN 202110368757 A CN202110368757 A CN 202110368757A CN 113098537 B CN113098537 B CN 113098537B
- Authority
- CN
- China
- Prior art keywords
- resistor
- signal
- module
- output
- submodule
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
- H04B1/1027—Means associated with receiver for limiting or suppressing noise or interference assessing signal quality or detecting noise/interference for the received signal
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Circuits Of Receivers In General (AREA)
- Control Of Amplification And Gain Control (AREA)
Abstract
The invention discloses an automatic gain control receiver for time division digital communication system, comprising: the device comprises a preprocessing module, an AGC module and an output module; the preprocessing module is used for receiving external signals, filtering interference and amplifying signals; the AGC module is used for receiving the signal output by the band-pass filter and adjusting the signal dynamic in real time so as to reduce the signal dynamic; the output module is used for receiving the signal output by the AGC module, amplifying the signal, filtering harmonic clutter and outputting the amplified signal. Because the detector is used for detecting the signal and the hysteresis comparator is used for judging the power signal, the hysteresis comparator has two reference voltages, namely one lower reference voltage and one higher reference voltage, the anti-interference performance of the receiver is enhanced, an AGC module can not deteriorate the vector amplitude error of the signal, the contradiction of an AGC time constant is reduced, and a reset signal is not needed; the AGC module of the invention adopts a cascading mode to ensure that the large dynamic of the input end can be converted into the small dynamic of the output end.
Description
Technical Field
The invention belongs to the technical field of receivers, and particularly relates to an automatic gain control receiver for a time division digital communication system.
Background
Automatic gain control circuits are an important part of large dynamic receivers and are widely applied in the aspects of communication, navigation and radar.
In an actual wireless communication system, due to the influences of the strength of a transmitted signal, the distance, the earth curvature and the like, the size difference of signals received by a receiver is large, and the structural complexity and the power consumption of a large dynamic ADC (analog to digital converter) are high, so an Automatic Gain Control (AGC) technology is generally adopted, and an EVM (evolution-gain modulation) is considered in a time division digital communication circuit, on one hand, an AGC time constant is far larger than a signal maximum envelope variation period T1, for example, the AGC time constant can be 20 times or more than T1; on the other hand, because the time between adjacent time slots is short, and because the power difference of signals of adjacent time slots may be large, the AGC needs to react in time, and it is also required that the AGC time constant should be smaller than a certain value T2, otherwise, the signals will be deteriorated, and data loss will result. When T2 is less than 20 times T1, then it is difficult for conventional AGC designs to compromise the two requirements; on the other hand, the input signal with larger dynamic is converted into the output signal with smaller dynamic, and the contradiction between the lost data rate and the inverse modulation is more difficult to balance because of the need of multi-stage AGC.
Disclosure of Invention
The technical purpose of the present invention is to provide an automatic gain control receiver for a time division digital communication system to achieve the technical effect of converting an input signal with a large dynamic into an output signal with a small dynamic.
In order to solve the problems, the technical scheme of the invention is as follows:
an automatic gain control receiver for a time division digital communication system, comprising: the device comprises a preprocessing module, an AGC module and an output module;
the preprocessing module is used for receiving external signals, amplifying the signals and filtering interference;
the AGC module is used for receiving the signals output by the band-pass filter and adjusting the signal dynamic in real time so as to reduce the signal dynamic;
the output module is used for receiving the signal output by the AGC module, amplifying and filtering harmonic waves and then outputting the amplified signal;
wherein, the AGC module includes: the power divider, the detection submodule, the first low-frequency amplification submodule, the hysteresis comparison submodule, the second low-frequency amplification submodule and the voltage-controlled attenuator;
the power divider is used for receiving the signal output by the band-pass filter, dividing the signal into two paths of signals and outputting the two paths of signals;
the detection submodule is used for receiving the first path of signal output by the power divider and detecting the first path of signal to obtain a power voltage signal;
the first low-frequency amplification sub-module is used for receiving the power voltage signal and amplifying the signal;
the hysteresis comparison submodule is used for receiving the power voltage signal output by the first low-frequency amplification submodule and converting the power voltage signal into a high-low level signal;
the second low-frequency amplification submodule is used for receiving the high-low level signal and amplifying the signal to obtain a control voltage signal;
the voltage-controlled attenuator is used for adjusting the signal dynamic of the second path of signal output by the power divider in real time according to the control voltage signal.
Specifically, the preprocessing module comprises a preselection filter, a low noise amplifier and a band-pass filter;
the preselection filter is used for receiving external signals and filtering out-of-band noise and interference signals;
the low noise amplifier is used for receiving the signal output by the preselection filter and amplifying the signal;
the band-pass filter is used for receiving the signal output by the low-noise amplifier and filtering out-of-band noise.
Specifically, the output module comprises a driving amplifier and a low-pass filtering submodule;
the driving amplifier is used for receiving the signal output by the AGC module and amplifying the signal;
the low-pass filtering module is used for filtering harmonic waves of the signals output by the receiving driving amplifier and outputting the signals.
Further preferably, the system further comprises a first fixed attenuation submodule, a second fixed attenuation submodule and a third fixed attenuation submodule which are used for impedance matching among the modules and adjusting the size of the received signal; the low noise amplifier is electrically connected with the band-pass filter through a first fixed attenuation submodule, the first fixed attenuation submodule comprises a first resistor, a second resistor and a third resistor, the output end of the low noise amplifier is electrically connected with one end of the first resistor and one end of the second resistor respectively, the other end of the second resistor is grounded, the other end of the first resistor is electrically connected with the input end of the band-pass filter through one end of the third resistor respectively, and the other end of the third resistor is grounded;
the AGC module is electrically connected with the driving amplifier through a second fixed attenuation submodule, the second fixed attenuation submodule comprises a fourth resistor, a fifth resistor and a sixth resistor, the output end of the AGC module is electrically connected with one end of the fourth resistor and one end of the fifth resistor respectively, the other end of the fifth resistor is grounded, the other end of the fourth resistor is electrically connected with one end of the sixth resistor and the input end of the driving amplifier respectively, and the other end of the sixth resistor is grounded;
the driving amplifier is electrically connected with the low-pass filtering module through a third fixed attenuation submodule, the third fixed attenuation submodule comprises a seventh resistor, an eighth resistor and a ninth resistor, the output end of the driving amplifier is electrically connected with one end of the seventh resistor and one end of the eighth resistor respectively, the other end of the eighth resistor is grounded, the other end of the seventh resistor is electrically connected with one end of the ninth resistor and the input end of the low-pass filtering module respectively, and the other end of the ninth resistor is grounded;
the low-pass filtering module outputs the signal after passing through the fourth fixed attenuation submodule, the third fixed attenuation submodule comprises a tenth resistor, an eleventh resistor and a twelfth resistor, the output end of the low-pass filtering module is electrically connected with one end of the tenth resistor and one end of the eleventh resistor respectively, the other end of the eleventh resistor is grounded, the other end of the tenth resistor is electrically connected with one end of the tenth resistor and the output end of the automatic gain control receiver respectively, and the other end of the ninth resistor is grounded.
The first low-frequency amplification sub-module comprises a first operational amplifier, a thirteenth resistor and a fourteenth resistor;
the non-inverting input end of the first operational amplifier is electrically connected with the output end of the detector, the inverting input end of the first operational amplifier is electrically connected with one end of the thirteenth resistor and one end of the fourteenth resistor respectively, the other end of the thirteenth resistor is grounded, and the output end of the first operational amplifier is electrically connected with the other end of the fourteenth resistor and the input end of the hysteresis comparison submodule respectively.
The hysteresis comparison submodule comprises a second operational amplifier, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor and a voltage stabilizing diode; the inverting input end of the second operational amplifier is the input end of the hysteresis comparison submodule;
the non-inverting input end of the second operational amplifier is grounded through a fifteenth resistor, the non-inverting input end of the second operational amplifier is electrically connected with the positive electrode of the voltage stabilizing diode after passing through a sixteenth resistor, the negative electrode of the voltage stabilizing diode is electrically connected with the positive power source end of the second operational amplifier, and the output end of the second operational amplifier is electrically connected with the positive electrode of the voltage stabilizing diode and the input end of the second low-frequency amplification submodule through a seventeenth resistor.
Specifically, the second low-frequency amplification sub-module comprises an eighteenth resistor, a nineteenth resistor, a twentieth resistor and a third operational amplifier;
the non-inverting input end of the third operational amplifier is electrically connected with the output end of the hysteresis comparison submodule, the inverting input end of the third operational amplifier is respectively connected with the power supply and the nineteenth resistor through the eighteenth resistor and then grounded, and the output end of the third operational amplifier is electrically connected with the voltage-controlled attenuator through the twentieth resistor.
Specifically, the low-pass filtering module comprises a first capacitor, a second capacitor, a third capacitor, a first inductor and a second inductor;
the output end of the second fixed attenuation submodule is electrically connected with one end of a first capacitor and one end of a first inductor respectively, the other end of the first capacitor is grounded, the other end of the first inductor is electrically connected with one end of a second capacitor and one end of a second inductor respectively, the other end of the second capacitor is grounded, and the other end of the second inductor is grounded after passing through a third capacitor and is output after passing through a third fixed attenuation submodule.
Due to the adoption of the technical scheme, compared with the prior art, the invention has the following advantages and positive effects:
1) the automatic gain control receiver of the invention uses the wave detector to detect the signal, thereby outputting the power signal, and judges the power signal by the hysteresis comparator, because the hysteresis comparator has two reference voltages of one lower reference voltage and one higher reference voltage, when the power signal reaches the larger reference voltage from small to large or the power signal reaches the smaller reference voltage from large to small, the AGC module will act once respectively; therefore, the anti-interference performance of the receiver is enhanced, the AGC module can not deteriorate the vector amplitude Error (EVM) of the signal, the contradiction of the AGC time constant is reduced, and a reset signal is not needed;
2) the AGC module of the invention adopts a cascading mode to ensure that the large dynamic of the input end can be converted into the small dynamic of the output end.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention.
Fig. 1 is a block diagram of an automatic gain control receiver according to an embodiment of the present invention;
fig. 2 is a block diagram of an AGC module according to an embodiment of the present invention;
fig. 3 is a schematic structural diagram of an automatic gain control receiver according to an embodiment of the present invention;
fig. 4 is a schematic structural diagram of an AGC module according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of the single stage AGC module receiver input output dynamics in accordance with one embodiment of the present invention;
fig. 6 is a signal time slot and interval diagram illustration of an automatic gain control receiver of an embodiment of the present invention;
FIG. 7 is a signal diagram of a signal header and an AGC control voltage signal according to one embodiment of the present invention;
FIG. 8 is a signal tail and AGC control voltage signal diagram of an embodiment of the present invention;
FIG. 9 is a signal envelope diagram of an embodiment of the present invention;
fig. 10 is a diagram of an input signal and an AGC control voltage of an AGC block according to an embodiment of the invention.
Description of the reference numerals
A1: a low noise amplifier; a2; a driver amplifier; c1: a first capacitor; c2: a second capacitor; c3: a third capacitor; c4: a fourth capacitor; d1: a first operational amplifier; d2: a second operational amplifier; d3: a third operational amplifier; n1, voltage controlled attenuator; r1: a first resistor; r2: a second resistor; r3: a third resistor; r4: a fourth resistor; r5: a fifth resistor; r6: a sixth resistor; r7: a seventh resistor; r8: an eighth resistor; r9: a ninth resistor; r10: a tenth resistor; r11: an eleventh resistor; r12: a twelfth resistor; r13: a thirteenth resistance; r14: a fourteenth resistance; r15: a fifteenth resistor; r16: a sixteenth resistor; r17: a seventeenth resistor; r18: an eighteenth resistor; r19: a nineteenth resistor; r20: a twentieth resistor; p1: a power divider; v1: a detector; v2, a voltage stabilizing diode; z1: a preselection filter; z2: a band pass filter.
Detailed Description
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following description will be made with reference to the accompanying drawings. It is obvious that the drawings in the following description are only some examples of the invention, and that for a person skilled in the art, other drawings and embodiments can be derived from them without inventive effort.
For the sake of simplicity, the drawings only schematically show the parts relevant to the present invention, and they do not represent the actual structure as a product. In addition, in order to make the drawings concise and understandable, components having the same structure or function in some of the drawings are only schematically illustrated or only labeled. In this document, "one" means not only "only one" but also a case of "more than one".
The following describes an automatic gain control receiver for a time division digital communication system according to the present invention with reference to the accompanying drawings and specific embodiments. Advantages and features of the present invention will become apparent from the following description and from the claims.
Referring to fig. 1, 2 and 3, the present embodiment provides an automatic gain control receiver for a time division digital communication system, including: the device comprises a preprocessing module, an AGC module and an output module; the preprocessing module is used for receiving external signals, filtering interference and amplifying signals; the AGC module is used for receiving the signal output by the band-pass filter and adjusting the signal dynamic in real time so as to reduce the signal dynamic; the output module is used for receiving the signal output by the AGC module, amplifying the signal, filtering harmonic clutter and outputting the amplified signal. The indexes of the embodiment are that the noise coefficient is less than 3dB, the dynamic range of an input signal is-110 dBm to-10 dBm, the modulation mode is 8PSK, the working frequency of the signal is positioned in a VHF frequency band, the symbol rate is 25k symbol/s, the time slot length of the signal is 26ms, the time slot interval is 1ms, the corresponding time of an AGC module is less than 400us, and the EVM is less than 5%.
The present embodiment will now be described in detail according to the signal direction:
referring to fig. 3, first, an external signal enters the preprocessing module of the present embodiment, and the preprocessing module includes a preselection filter Z1, a low noise amplifier a1, a first fixed attenuation sub-module, and a band pass filter Z2, which are sequentially arranged in series in the signal moving direction.
Specifically, in this embodiment, it is necessary to select a low noise amplifier and a preselection filter of an appropriate type according to the noise coefficient and the Error Vector Magnitude (EVM) of the input signal. According to a noise coefficient formula of a cascade system:
wherein G is1For preselecting filter gain, G2For low noise amplifier gain, F1For preselecting the noise coefficient of the filter, F2For noise figure from low noise amplifiers, F3Is the overall noise figure of the circuit after the low noise amplifier. The preselected filter bandwidth and gain G are determined from the above equation, the system noise figure index, the input signal power range, the EVM, and the relationship between the preselected filter bandwidth and the insertion loss1While also selecting the low noise amplifier noise factor F2And gain G thereof2And 1dB compression point.
The signal from the low noise amplifier a1 then enters a first fixed attenuation sub-module, which is used to adjust the signal size. Specifically, the first fixed attenuation submodule includes a first resistor R1, a second resistor R2, and a third resistor R3, and the signal output by the low noise amplifier a1 enters the band-pass filter Z2 through the first fixed attenuation submodule. The circuit is specifically arranged, wherein the first resistor R1, the second resistor R2 and the third resistor R3 are arranged in a pi shape. The low noise amplifier A1 is connected in parallel with the second resistor R2, then connected in series with the first resistor R1, and then connected in parallel with the third resistor R3, after the signal is attenuated by the first fixed attenuation submodule, the first fixed attenuation submodule is connected in series with the band-pass filter Z2.
Referring to fig. 3 and 4, the signal then enters an AGC module, specifically, the AGC module includes a power divider P1, a detection sub-module, a first low frequency amplification sub-module, a hysteresis comparison sub-module, a second low frequency amplification sub-module, and a voltage controlled attenuator N1.
Specifically, port 1 of the power divider P1 is configured to receive a signal output by the band-pass filter Z2, divide the signal into two paths of signals, and output the two paths of signals, where the signal output by port 2 is input to the voltage-controlled attenuator N1, and the signal output by port 3 is input to the detector module.
The detector module comprises a detector V1 and a fourth capacitor C4, the fourth capacitor C4 is matched with the detector V3878, a port 6 of the detector V1 is used for receiving a path of signal output by the power divider P1 and converting the path of signal into a power voltage signal to be output to the first low-frequency amplification sub-module, a port 1 and a port 4 of the detector V1 are both connected with a power supply, a port 5 of the detector V1 is connected with the power supply through the fourth capacitor C4, and a port 2 of the detector V is grounded. In this embodiment, the detector is a root mean square response detector, a linear relationship between the output voltage and the input power of the detector is set as A mV/dB, and the rising voltage slew rate of the output voltage of the detector is set as S1mV/us, falling slew rate of S2mV/us then needs to satisfy S1>(10×S2)，S1>50, the slew rate can be adjusted by adjusting the capacitance of the fourth capacitor C4.
The first low-frequency amplification sub-module is used for receiving the power voltage signal output by the port 3 of the detector V1 and performing signal amplification to output an amplified power voltage signal. Specifically, the first low-frequency amplification sub-module includes: a first operational amplifier D1, a thirteenth resistor R13, and a fourteenth resistor R14;
a non-inverting input end, i.e., a port 3, of the first operational amplifier D1 is electrically connected to a port 3 of the detector V1 and is configured to receive a signal, an inverting input end, i.e., a port 2, of the first operational amplifier D1 is connected in parallel to a thirteenth resistor R13 and a fourteenth resistor R14, one end of the thirteenth resistor R13, which is not electrically connected to the first operational amplifier D1, is grounded, and two ends of the fourteenth resistor R14 are electrically connected to a port 2 and an output end, i.e., a port 6, of the first operational amplifier D1, respectively; the signal enters the hysteresis comparison submodule through a port 6 of the first operational amplifier D1, so that power voltage signal amplification is realized. In addition, the first operational amplifier D1 has a power supply voltage VCC2V at port 1, and a ground at port 4, wherein the first operational amplifier D1 is a rail-to-rail input/output operational amplifier. The first low frequency amplification sub-module amplifies the detector module output voltage to (1+ R13/R14) such that U1×(1+R13/R14)>1000 and U2×(1+R13/R14)<500 × VCC2, wherein U1、U2Respectively obtaining the output voltage values of the voltage-controlled attenuator input end reaching two trigger point detectors according to the linear relation of the voltage and the power, and U1-U2The capacitance value of the fourth capacitor is adjusted to 400 × S ═ 6 × a) mV1>U2And 40 × S2<(U1-U2)。
The hysteresis comparison submodule is used for receiving the power voltage signal output by the first low-frequency amplification submodule and converting the power voltage signal into a high-low level signal. Specifically, referring to fig. 3 and 4, the hysteresis comparison sub-module includes a second operational amplifier D2, a fifteenth resistor R15, a sixteenth resistor R16, a seventeenth resistor R17 and a zener diode V2;
the inverting input terminal, i.e., port 2, of the second operational amplifier D2 is the input terminal of the hysteresis comparison submodule, i.e., the power voltage signal enters from port 2 of the second operational amplifier D2. The output end of the second operational amplifier D2, i.e. the output signal of the port 2, passes through a seventeenth resistor R17 and then enters a second low-frequency amplification sub-module, preferably, the seventeenth resistor R17 is further connected in parallel with the zener diode V2 and the sixteenth resistor R16, i.e. the signal passing through the seventeenth resistor R17 is further input to the zener diode V2 and the sixteenth resistor R16, wherein one path of signal enters the zener diode from the positive pole of the zener diode and then is input to the port 1 of the second operational amplifier D2; the other signal enters a sixteenth resistor R16, the sixteenth resistor R16 is further connected in parallel with the fifteenth resistor R15 and the second operational amplifier D2, and in detail, the signal is divided into two paths after passing through the sixteenth resistor R16, wherein one path of the signal is released after passing through the fifteenth resistor R15, the other path of the signal enters the positive power supply end, i.e., the port 3, of the second operational amplifier D2, and the negative power supply end, i.e., the port 4, of the second operational amplifier D2 is grounded.
In the hysteresis comparison submodule, a voltage stabilizing diode V2 is set to stabilize the voltage to be U3V, and make 3<U3<VCC2, adjusting resistor R15 and resistor R16, and recording the input power of the voltage-controlled attenuator to be less than (-63+ G)1+ G) dBm time lag backward comparator output value is U4V, the input power of the voltage-controlled attenuator is larger than (-57+ G)1+ G) dBm time lag backward comparator output value is U5V, when the input power of the voltage-controlled attenuator is increased from small to (-57+ G)1+ G) dBm time lag backward comparator module output value is generated by U4V jump to U5V, when the input power of the voltage-controlled attenuator is reduced from a large value to (-63+ G)1+ G) dBm time lag backward comparator module output value is generated by U5V jump to U4And V, wherein G is the circuit gain before the voltage-controlled attenuator after the preselection filter.
Next, referring to fig. 3 and 4, the second low frequency amplification sub-module is configured to receive the high and low level signals and perform signal amplification to obtain a control voltage signal. Specifically, the second low-frequency amplification sub-module comprises an eighteenth resistor R18, a nineteenth resistor R19, a twentieth resistor R20 and a third operational amplifier D3; the non-inverting input end, namely the port 3, of the third operational amplifier D3 is electrically connected with the output end of the hysteresis comparison submodule; an external power is inputted to the inverting input terminal of the third operational amplifier D3, i.e., the port 2, through the eighteenth resistor R18, and both ends of the nineteenth resistor R19 are connected to the third operational amplifier D3And the port 2 is connected with the ground end. The port 1 of the third operational amplifier D3 is a positive power supply terminal for connecting to an external power supply VCC2, and the port 4 thereof is a negative power supply terminal for grounding. Then, the signal is outputted through the output terminal of the third operational amplifier D3, i.e. the port 6, and the amplified control voltage signal enters the voltage controlled attenuator N1 through the twentieth resistor R20. Adjusting the resistors R18, R19 and R20 to make the input value of the second low-frequency amplification submodule be U respectively4V、U5V, the voltage value of the output end is respectively CU1V and CU2V, wherein, CU1And CU2Obtained by a voltage controlled attenuator.
The voltage-controlled attenuator N1 is used for adjusting the dynamic of the signal input from port 2 to port 2 of the voltage-controlled attenuator by the power divider in real time according to the control voltage signal, and the voltage-controlled attenuator needs to meet the requirement that the difference between the maximum attenuation and the minimum attenuation is greater than half of the dynamic range of the input signal as much as possible, assuming that the maximum attenuation is L1dB, minimum attenuation of L2dB, i.e. (L)1-L2)>50. Wherein, the dynamic range of the signal before the voltage-controlled attenuator is (-110+ G)1+G)dBm～(-10+G2+ G) dBm, the power of two trigger points at the input end of the voltage-controlled attenuator is (-63+ G)1+ G) dBm and (-57+ G)1+ G) dBm. When the input power of the voltage-controlled attenuator reaches two trigger points, the attenuation values are respectively L2dB and L3dB, and the following two formulas are required
(-110+G-L2)<(-63+G-L3)<(-110+G-L2+2)；
(-10+G-L3)＝(-57+G-L2)；
In the above two formulas, G represents the net gain of the circuit before the voltage-controlled attenuator.
When the voltage-controlled attenuation values are respectively L2dB and L3In dB, the control voltage is recorded as CU1V and CU2V。
Referring to FIG. 4, in the present embodiment, the slew rates of the first, second and third operational amplifiers D3D1, D2 and D3 should all be greater than 0.1V/us. L is2May be 3, L3The optimum value can be 49, so that the dynamic range of the input of the receiver is 100dB, and the dynamic range of the output can be adjusted to be54 dB. If the receiver output is used as the input of another automatic gain control receiver, namely if the receiver has two-stage AGC cascade, the output dynamic can be reduced to 31dB, and if the receiver has three-stage AGC cascade, the output dynamic can be reduced to 19 dB.
Referring to fig. 3, the output module includes a second fixed attenuation sub-module, a driving amplifier a2, a third fixed attenuation sub-module, a low pass filter sub-module, and a fourth fixed attenuation sub-module, which are sequentially arranged in series. Specifically, the second fixed attenuation sub-module is used for receiving the signal output by the AGC module and adjusting the size of the signal. The second fixed attenuation submodule includes a fourth resistor R4, a fifth resistor R5, and a sixth resistor R6, and the signal of the AGC module enters the driving amplifier a2 through the second fixed attenuation submodule. The circuit is specifically arranged, wherein the fourth resistor R4, the fifth resistor R5 and the sixth resistor R6 are arranged in a pi shape. The AGC module is connected in parallel with a fifth resistor R5, then connected in series with a fourth resistor R4, then connected in parallel with a sixth resistor R6, and after the signal is attenuated by a second fixed attenuation submodule, the second fixed attenuation submodule is connected in series with a drive amplifier A2.
The port 1 of the driving amplifier a2 is used for receiving the signal of the second fixed attenuation submodule and outputting the signal after amplifying the signal from the port 3, the port 4 is connected with the power supply, and the port 2 is grounded. Specifically, the third fixed attenuation submodule is configured to receive the signal output from port 3 of the driver amplifier a2 and adjust the magnitude of the signal. The third fixed attenuation submodule comprises a seventh resistor R7, an eighth resistor R8 and a ninth resistor R9, and a signal output by the driving amplifier A2 enters the low-pass filtering module through the third fixed attenuation submodule. The circuit is specifically arranged, wherein the seventh resistor R7, the eighth resistor R8 and the ninth resistor R9 are arranged in a pi shape. The driving amplifier A2 is connected in parallel with the eighth resistor R8, then connected in series with the seventh resistor R7, and then connected in parallel with the ninth resistor R9, after the signal is attenuated by the second fixed attenuation submodule, the second fixed attenuation submodule is connected in series with the low-pass filter module.
Next, referring to fig. 3, the low pass filter module is used to harmonic filter and output the signal output by the receiving driver amplifier a 2. Specifically, the low pass filtering module includes a first capacitor C1, a second capacitor C2, a third capacitor C3, a first inductor L1 and a second inductor L2. The output end of the third fixed attenuation submodule is electrically connected with one end of a first capacitor C1 and one end of a first inductor L1 respectively, the other end of the first capacitor C1 is grounded, the other end of the first inductor L1 is electrically connected with one end of a second capacitor C2 and one end of a second inductor L2 respectively, the other end of the second capacitor C2 is grounded, one end of the second inductor L2, which is connected with the third capacitor C3, is a low-pass filter module output end, and the other end of the third capacitor C3 is grounded.
Finally, referring to fig. 3, the fourth fixed attenuation sub-module is configured to receive the signal output by the low-pass filtering module, adjust the magnitude of the signal, and output the signal to the outside of the embodiment. The fourth fixed attenuation submodule comprises a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12, and the signal output by the low-pass filtering module is output to the outside through the fourth fixed attenuation submodule. The circuit is specifically provided, wherein the tenth resistor R10, the eleventh resistor R11 and the twelfth resistor R12 are arranged in a pi shape. The low-pass filtering module is connected with the eleventh resistor R11 in parallel, then connected with the tenth resistor R10 in series, then connected with the twelfth resistor R12 in parallel, and the signal is attenuated by the fourth fixed attenuation sub-module and then output to the outside.
Referring to fig. 5 to fig. 10, the principle of the present embodiment is now explained, the key point of the present embodiment is that the AGC module converts the input large dynamic into the smaller dynamic output by using the dichotomy, and the output dynamic through the first-stage AGC module is reduced by about one half of the input dynamic; the influence of critical point noise and the digital modulation signal with the band limit are not constant amplitude signals, so a protection section (two trigger points) is arranged through a hysteresis comparator, thereby avoiding the unstable attenuation state and also maximally accelerating the AGC response speed; the rising slew rate and the falling slew rate of the output voltage of the detection module are adjusted, so that the requirement of AGC time constant is met, and simultaneously, the fluctuation of the output voltage of the detection module caused by the fluctuation of the envelope of noise and signals is smaller than the voltage difference of two trigger points, the output of the hysteresis attenuator is kept unchanged, the control voltage is also kept unchanged, the attenuation value of the voltage-controlled attenuator is also kept unchanged, the power of the output signal of the receiver is not changed due to AGC control, and the anti-noise performance is improved without deteriorating the signal quality. The voltage signal is amplified by the operational amplifier with high slew rate to drive the voltage-controlled attenuator, so that the first-stage automatic gain control can be completed. The output of the front AGC module is used as the input of the secondary AGC module, the output dynamics of the two-stage AGC cascade can be reduced, and the output dynamics of the three-stage AGC cascade can be further reduced by the analogy.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments. Even if various changes are made to the present invention, it is still within the scope of the present invention if they fall within the scope of the claims of the present invention and their equivalents.
Claims (8)
1. An automatic gain control receiver for a time division digital communication system, comprising: the device comprises a preprocessing module, an AGC module and an output module;
the preprocessing module is used for receiving external signals, amplifying the signals and filtering interference;
the AGC module is used for receiving the signal output by the band-pass filter and adjusting the signal dynamic in real time to reduce the signal dynamic;
the output module is used for receiving the signal output by the AGC module and outputting the signal after amplifying and filtering harmonic waves;
wherein the AGC module includes: the power divider, the detection submodule, the first low-frequency amplification submodule, the hysteresis comparison submodule, the second low-frequency amplification submodule and the voltage-controlled attenuator;
the power divider is used for receiving the signal output by the band-pass filter, dividing the signal into two paths of signals and outputting the two paths of signals;
the detection submodule is used for receiving the first path of signal output by the power divider and detecting to obtain a power voltage signal;
the first low-frequency amplification sub-module is used for receiving the power voltage signal and amplifying the power voltage signal;
the hysteresis comparison submodule is used for receiving the power voltage signal output by the first low-frequency amplification submodule and converting the power voltage signal into a high-low level signal;
the second low-frequency amplification submodule is used for receiving the high-low level signal and amplifying the signal to obtain a control voltage signal;
and the voltage-controlled attenuator is used for adjusting the signal dynamic of the second path of signal output by the power divider in real time according to the control voltage signal.
2. The automatic gain control receiver for a time division digital communication system according to claim 1, wherein said preprocessing module comprises a preselection filter, a low noise amplifier, said band pass filter;
the preselection filter is used for receiving external signals and filtering out-of-band noise and interference signals;
the low noise amplifier is used for receiving the signal output by the preselection filter and amplifying the signal;
the band-pass filter is used for receiving the signal output by the low-noise amplifier and filtering out-of-band noise.
3. The automatic gain control receiver for a time division digital communication system according to claim 2, wherein the output module includes a driver amplifier and a low pass filter module;
the driving amplifier is used for receiving the signal output by the AGC module and amplifying the signal;
and the low-pass filtering module is used for filtering harmonic waves of the signals received and output by the driving amplifier and outputting the signals.
4. The automatic gain control receiver for a time division digital communication system according to claim 3, further comprising a first fixed attenuation sub-module, a second fixed attenuation sub-module, a third fixed attenuation sub-module and a fourth fixed attenuation sub-module for impedance matching between the respective modules and adjusting the magnitude of the received signal;
the low noise amplifier is electrically connected with the band-pass filter through the first fixed attenuation submodule, the first fixed attenuation submodule comprises a first resistor, a second resistor and a third resistor, the output end of the low noise amplifier is electrically connected with one end of the first resistor and one end of the second resistor respectively, the other end of the second resistor is grounded, the other end of the first resistor is electrically connected with the input end of the band-pass filter through one end of the third resistor respectively, and the other end of the third resistor is grounded;
the AGC module is electrically connected with the driving amplifier through the second fixed attenuation submodule, the second fixed attenuation submodule comprises a fourth resistor, a fifth resistor and a sixth resistor, the output end of the AGC module is electrically connected with one end of the fourth resistor and one end of the fifth resistor respectively, the other end of the fifth resistor is grounded, the other end of the fourth resistor is electrically connected with one end of the sixth resistor and the input end of the driving amplifier respectively, and the other end of the sixth resistor is grounded;
the driving amplifier is electrically connected with the low-pass filtering module through the third fixed attenuation submodule, the third fixed attenuation submodule comprises a seventh resistor, an eighth resistor and a ninth resistor, the output end of the driving amplifier is electrically connected with one end of the seventh resistor and one end of the eighth resistor respectively, the other end of the eighth resistor is grounded, the other end of the seventh resistor is electrically connected with one end of the ninth resistor and the input end of the low-pass filtering module respectively, and the other end of the ninth resistor is grounded;
the low-pass filtering module outputs the signal after passing through the fourth fixed attenuation submodule, the fourth fixed attenuation submodule comprises a tenth resistor, an eleventh resistor and a twelfth resistor, the output end of the low-pass filtering module is respectively and electrically connected with one end of the tenth resistor and one end of the eleventh resistor, the other end of the eleventh resistor is grounded, the other end of the tenth resistor is respectively and electrically connected with one end of the twelfth resistor and the output end of the automatic gain control receiver, and the other end of the twelfth resistor is grounded.
5. The automatic gain control receiver for a time division digital communication system according to claim 4, wherein the first low frequency amplification sub-module comprises a first operational amplifier, a thirteenth resistor and a fourteenth resistor;
the non-inverting input end of the first operational amplifier is electrically connected with the output end of the detection submodule, the inverting input end of the first operational amplifier is electrically connected with one end of the thirteenth resistor and one end of the fourteenth resistor respectively, the other end of the thirteenth resistor is grounded, and the output end of the first operational amplifier is electrically connected with the other end of the fourteenth resistor and the input end of the hysteresis comparison submodule respectively.
6. The automatic gain control receiver for a time division digital communication system according to claim 5, wherein the hysteresis comparison sub-module includes a second operational amplifier, a fifteenth resistor, a sixteenth resistor, a seventeenth resistor and a zener diode;
the inverting input end of the second operational amplifier is the input end of the hysteresis comparison submodule;
the non-inverting input end of the second operational amplifier is grounded after passing through the fifteenth resistor and is electrically connected with the anode of the voltage stabilizing diode after passing through the sixteenth resistor, the cathode of the voltage stabilizing diode is electrically connected with the positive power supply end of the second operational amplifier, and the output end of the second operational amplifier is electrically connected with the anode of the voltage stabilizing diode and the input end of the second low-frequency amplification submodule through the seventeenth resistor.
7. The automatic gain control receiver for a time division digital communication system according to claim 6, wherein the second low frequency amplification sub-module comprises an eighteenth resistor, a nineteenth resistor, a twentieth resistor, and a third operational amplifier;
the in-phase input end of the third operational amplifier is electrically connected with the output end of the hysteresis comparison submodule, the reverse-phase input end of the third operational amplifier is respectively connected with a power supply after passing through the eighteenth resistor, and is grounded after passing through the nineteenth resistor, and the output end of the third operational amplifier is electrically connected with the voltage-controlled attenuator through the twentieth resistor.
8. The automatic gain control receiver for a time division digital communication system according to claim 4, wherein the low pass filtering module comprises a first capacitor, a second capacitor, a third capacitor, a first inductor and a second inductor;
the output end of the second fixed attenuation submodule is electrically connected with one end of the first capacitor and one end of the first inductor respectively, the other end of the first capacitor is grounded, the other end of the first inductor is electrically connected with one end of the second capacitor and one end of the second inductor respectively, the other end of the second capacitor is grounded, and the other end of the second inductor is grounded after passing through the third capacitor and is output after passing through the third fixed attenuation submodule respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110368757.6A CN113098537B (en) | 2021-04-06 | 2021-04-06 | Automatic gain control receiver for time division digital communication system |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110368757.6A CN113098537B (en) | 2021-04-06 | 2021-04-06 | Automatic gain control receiver for time division digital communication system |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113098537A CN113098537A (en) | 2021-07-09 |
| CN113098537B true CN113098537B (en) | 2022-05-27 |
Family
ID=76674593
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110368757.6A Active CN113098537B (en) | 2021-04-06 | 2021-04-06 | Automatic gain control receiver for time division digital communication system |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113098537B (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101674441A (en) * | 2008-09-09 | 2010-03-17 | 扬智科技股份有限公司 | Automatic gain controller and control method thereof |
| CN204425284U (en) * | 2015-02-10 | 2015-06-24 | 苏州思源通科技有限公司 | A kind of automatic gain control circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2003125012A (en) * | 2001-10-16 | 2003-04-25 | Matsushita Electric Ind Co Ltd | Ask demodulator with agc |
| TWI392227B (en) * | 2009-07-22 | 2013-04-01 | Sunplus Technology Co Ltd | Automatic gain control loop with hysteresis switching |
| CN104135299B (en) * | 2014-07-18 | 2016-10-19 | 中国电子科技集团公司第四十一研究所 | A kind of dual pathways two-stage frequency conversion broadband receiver and auto gain control method thereof |
| CN105356897A (en) * | 2015-10-18 | 2016-02-24 | 中国电子科技集团公司第十研究所 | Wireless receiving front-end containing asymmetrical adjustment speed AGC controller |
| CN206649085U (en) * | 2017-04-12 | 2017-11-17 | 南京信息工程大学 | A kind of device of acquisition pulse rise time |
| CN209283218U (en) * | 2018-12-28 | 2019-08-20 | 中兵通信科技股份有限公司 | Automatic growth control zero intermediate frequency reciver |
-
2021
- 2021-04-06 CN CN202110368757.6A patent/CN113098537B/en active Active
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101674441A (en) * | 2008-09-09 | 2010-03-17 | 扬智科技股份有限公司 | Automatic gain controller and control method thereof |
| CN204425284U (en) * | 2015-02-10 | 2015-06-24 | 苏州思源通科技有限公司 | A kind of automatic gain control circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113098537A (en) | 2021-07-09 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7659707B2 (en) | RF detector with crest factor measurement | |
| US20020037706A1 (en) | Baseband circuit incorporated in direct conversion receiver free from direct-current offset voltage without change of cut-off frequency | |
| CN105490655B (en) | The power control circuit and method of a kind of solid-state power amplifier | |
| CN112332803B (en) | Active low-pass filter bandwidth calibration circuit | |
| CN112564726B (en) | Receiver broadband large dynamic automatic gain control circuit | |
| JP2023529847A (en) | High-frequency power amplifiers, high-frequency front-end modules and communication terminals | |
| CN114024511B (en) | Digitally controlled broadband high-linearity variable gain amplifier | |
| CN212726952U (en) | Amplifying circuit for converting microphone differential input into single-ended output | |
| CN101510786B (en) | Receiver with low power consumption | |
| CN113098537B (en) | Automatic gain control receiver for time division digital communication system | |
| CN108880483B (en) | Broadband amplifier with noise feedforward cancellation | |
| CN110166064B (en) | Novel Gaussian passband intermediate frequency receiver | |
| CN115567070B (en) | Front end assembly capable of self-adapting to instantaneous dynamic expansion | |
| CN101252366A (en) | Apparatus for eliminating zero intermediate frequency wireless receiver direct current partial difference | |
| CN101291136A (en) | Frequency converter circuit and receiver | |
| CN111049487A (en) | Automatic gain control circuit and control method | |
| CN102035578B (en) | Automatic grain control method and device for diversity receiving | |
| CN113740878B (en) | Balance detector circuit for wind-finding radar | |
| CN204481809U (en) | High-precision radio frequency module | |
| CN218850761U (en) | Radio frequency receiver based on single-bit frequency measurement | |
| CN115622519A (en) | Band-notch low-noise amplifier based on LC resonance technology and method for improving out-of-band input 1dB compression point thereof | |
| CN109067413A (en) | A kind of ultrashort wave channel receiver of high dynamic range | |
| CN219980820U (en) | Multichannel radio frequency front end based on LRM framework | |
| CN216930007U (en) | Satellite-borne spread spectrum transponder large dynamic linear AGC radio frequency receiving circuit | |
| CN217010817U (en) | High-gain low-noise amplifier |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |