CN105356897A - Wireless receiving front-end containing asymmetrical adjustment speed AGC controller - Google Patents
Wireless receiving front-end containing asymmetrical adjustment speed AGC controller Download PDFInfo
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- CN105356897A CN105356897A CN201510671195.7A CN201510671195A CN105356897A CN 105356897 A CN105356897 A CN 105356897A CN 201510671195 A CN201510671195 A CN 201510671195A CN 105356897 A CN105356897 A CN 105356897A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
Abstract
The invention provides a wireless receiving front-end containing an asymmetrical adjustment speed AGC (Automatic Gain Control) controller, which can perform adjustment by adopting different controllable speeds in signal amplification and attenuation directions. The wireless receiving front-end containing the asymmetrical adjustment speed AGC controller is realized through the technical scheme below: RF signals received by an antenna after being amplified by a low-noise amplifier are attenuated by a numerical control attenuator and subjected to frequency conversion by a down converter to form intermediate frequency signals; then the intermediate frequency signals are sampled by an ADC (Analogue-Digital Converter) and then transmitted to the asymmetrical adjustment speed AGC controller for AGC control word calculation; and a control word calculation result is fed back to the numerical control attenuator of a RF front end to form a new round of AGC control word circular calculation loop. As a multiplier controllable coefficient and a control word register bit width as well as any controllable asymmetrical adjustment speed in two directions of AGC control word decrease and increase are adopted by the asymmetrical adjustment speed AGC controller, control for any controllable asymmetrical adjustment speed in the signal amplification and attenuation directions is realized.
Description
Technical field
The present invention relates in wireless communication receiver system the radio receiver front end circuit structure being mainly used in asymmetric adjustment speed automatic growth control AGC and controlling.
Background technology
In a wireless communication system, the signal that antenna receives often has the feature of power instability, therefore in order to ensure the demodulation of wireless receiver, often need to introduce no matter Received signal strength is excessive or too small at radio receiver front end, signal can be adjusted to appropriate power scope, so that automatic growth control (AGC) circuit of the correct demodulation of receiver.From the classification realized, AGC controls mainly to be divided into digital AGC, simulation AGC and mixed AGC.Digital AGC in digit chip, carries out digital processing to AD sampled signal directly realize; Simulation AGC is application simulation circuit realiration; Mixed AGC has the feature of digital AGC and simulation AGC concurrently, first in digital circuit, calculates AGC control word, then sends it to the gain that the variable gain amplifier (VGA) of analog circuit or numerical-control attenuator realize signal and controls.From traditional AGC controller, no matter be which kind of implementation method, all that input signal crosses its decay of senior general, input signal crosses young pathbreaker, and it amplifies, and the convergence in this both direction is regulated the speed often identical or close, even if convergence can be changed regulate the speed, usually also just both direction to accelerate simultaneously or slack-off.If need to realize asymmetric convergence adjustment speed controlled arbitrarily in both directions, traditional AGC controller is not supported or realizes complexity.In some discontinuous communication systems, signal frame might not be continuously send, so receiver is likely in the state receiving noise for a long time, at this moment traditional AGC controller then can to receive under lower-powered noise situations constantly adjustment controlled quentity controlled variable and to be amplified to by signal the power bracket of needs, when once receive signal frame power moment grow, now receiver still carried out signal adjustment based on the AGC controlled quentity controlled variable in a upper moment, and strong signal attenuation is needed certain response time by AGC controller, signal power will be caused during this period excessive, easily cause the saturated or demodulation mistake of receiver signal.In this case a kind of amplification by input signal and the asymmetric AGC controller of convergence adjustment speed in decay both direction is just needed, slow as much as possible toward convergence adjustment speed on the direction that signal amplifies when receiving lower-powered noise, AGC controlled quentity controlled variable based on a upper moment when such signal arrives can not cause power excessive, then by the direction of signal attenuation adopting the speed of convergence adjustment faster rapidly signal is adjusted to suitable power bracket, the receiving demodulation of signal is not affected.
Summary of the invention
In order to overcome the drawback that in discontinuous communication system, traditional AGC controller causes, the present invention proposes a kind of realize simple, resource occupation is less, can amplify at signal and decay both direction realize any controlled asymmetrical convergence adjustment speed, the wireless receiving front end containing asymmetric adjustment speed AGC controller.
Above-mentioned purpose of the present invention can be reached by following measures, a kind of wireless receiving front end containing asymmetric adjustment speed AGC controller, comprise low noise amplifier in sequential series, numerical-control attenuator, with low-converter and the analog to digital converter ADC of local oscillator, it is characterized in that: the output series connection asymmetric adjustment speed AGC controller of analog to digital converter ADC, wherein, antenna receives after radiofrequency signal amplifies by low noise amplifier, decayed by numerical-control attenuator, intermediate-freuqncy signal is converted to through low-converter, intermediate-freuqncy signal carries out hits word processing by analog to digital converter ADC, deliver to asymmetric adjustment speed AGC controller and carry out the calculating of AGC control word, control word result of calculation feeds back to the numerical-control attenuator of radio-frequency front-end, form the AGC control word cycle calculations loop of a new round, within constantly adjusting signal power size to double threshold by the cycle calculations loop introducing radio receiver front end like this, asymmetric adjustment speed AGC controller inside adopts these two key parameters of bit wide of multiplier controllable factor and control word register to decide AGC control word adjustment speed, and by reducing AGC control word and strengthening in this both direction and adopt asymmetric adjustment speed controlled arbitrarily, realize the control to asymmetric adjustment speed controlled arbitrarily in the amplification of signal and this both direction that decays.
The present invention is compared to traditional AGC controller compared to prior art and originally has following beneficial effect:
Realize simple, take resource few.The present invention is at the analog to digital converter ADC output series connection asymmetric adjustment speed AGC controller of radio receiver front end, realize signal to amplify and any controlled asymmetrical convergence adjustment speed in decay both direction, can be realized in this digit chip of FPGA very easily, realize simple, take resource few, only need a small amount of accumulator, multiplier, adder, subtracter, register, comparator and data selector etc.
The present invention carries out the calculating of AGC control word by asymmetric adjustment speed AGC controller to the intermediate-freuqncy signal after AD sampling, is sent to the watt level of radio frequency numerical-control attenuator and then regulation output signal by interface.Asymmetric adjustment speed AGC controller inside adopts these two key parameters of bit wide of multiplier controllable factor and control word register to decide AGC control word adjustment speed, so just, achieve the control to the asymmetric convergence adjustment speed in signal amplification and decay both direction, solve in some special discontinuous communication systems, tradition AGC controller can cause signal power excessive, easily causes the drawback of the saturated or demodulation mistake of receiver signal.
Accompanying drawing explanation
Fig. 1 is wireless communication system receiving front-end model schematic.
Fig. 2 is asymmetric adjustment speed AGC controller circuit structure schematic diagram.
Fig. 3 is the asymmetric adjustment speed AGC control flow chart of corresponding diagram 2.
Embodiment
Shown in Fig. 1 based in wireless communication system receiving front-end model, wireless receiving front end containing asymmetric adjustment speed AGC controller, comprise low noise amplifier in sequential series, numerical-control attenuator, output series connection asymmetric adjustment speed AGC controller with the low-converter of local oscillator and analog to digital converter ADC, analog to digital converter ADC.After radiofrequency signal changes to intermediate-freuqncy signal by low noise amplifier, numerical-control attenuator, low-converter, enter asymmetric adjustment speed AGC controller through analog-to-digital conversion ADC sampling and calculate AGC control word, then control word is fed back to by interface the size that numerical-control attenuator forms loop and then regulation output signal.Asymmetric adjustment speed AGC controller adopts these two key parameters of bit wide of multiplier controllable factor and control word register to decide AGC control word adjustment speed, can amplify signal and decay both direction adopt different controlled rates to adjust.Low noise amplifier is a uncontrollable fixing multiplication factor.To the amplification of signal and the adjustment of this both direction that decays be correspond to asymmetric adjustment speed AGC controller feed back to numerical-control attenuator AGC control word reduce and increase realize.The AGC control word delivering to numerical-control attenuator is larger, then larger to the decay of signal; And AGC control word is less, then less to the decay of signal, be equal to and signal is amplified larger.AGC control word increases faster, also faster to the decay of signal, otherwise also slower to the decay of signal; AGC control word reduces faster, also faster to the amplification of signal, otherwise also slower to the amplification of signal.
Consult Fig. 2.According to above description, a kind of concrete asymmetric adjustment speed AGC controller circuit structure can be proposed.Conveniently set forth, the AGC control word bit wide K setting radio frequency numerical-control attenuator is here 8 bits, and also namely correspondence 0 is to the pad value of 255dB, and M-bit control word register bit wide is 10 bits, and N bits control words register bit wide is 20 bits.
Asymmetric adjustment speed AGC controller contains average power signal higher than the Upper threshold branch road of Upper threshold and the average power signal Lower Threshold branch road lower than Lower Threshold, the speed speed that multiplier controllable factor on these two branch roads and these two key parameter control AGC control words of the bit wide of control word register reduce and increase, and then the control realizing the asymmetric convergence adjustment speed of signal being amplified and decays in both direction.Asymmetric adjustment speed AGC controller circuitry mainly comprises: the subtracter branch road being connected on multiplier front and back end, the subtracter being connected on multiplier front end and be connected on multiplier rear end adder branch road and by between the subtracter parallel connections of above-mentioned two branch roads, two, superior musical instruments used in a Buddhist or Taoist mass front end, DC filtering circuit in sequential series, fixedly average power meter of counting calculate circuit, fixing double threshold comparator and data selector.Wherein, the effect of DC filtering circuit is filtering direct current, to eliminate the impact that this non-signal composition calculates AGC control word.The effect of average power meter of fixedly counting calculation device is the watt level of accurate evaluation current Received Signal, so that the AGC of complete pair signals controls.The effect of fixing double threshold comparator is the size of comparison signal average power and high and low thresholds, data selector is sent by comparative result, the effect of data selector is then select the AGC control word of corresponding branch road to send numerical-control attenuator according to comparator Output rusults, if average power is within double threshold, then keep the AGC control word sending numerical-control attenuator.Subtracter by multiplier series type adder, and forms average power signal higher than Upper threshold branch road by the 10 bit control register R1 that adder input is connected; Subtracter to be connected subtracter by multiplier, and forms average power signals lower than Lower Threshold branch road by the 20 bit control register R2 that subtracter input is connected.10 bit control register R1 connect the splicer be connected in parallel between adder and data selector.20 bit control register R2 connect the splicer be connected in parallel between subtracter and data selector.
AGC control word is mainly added ambassador's signal attenuation higher than the Upper threshold branch road of Upper threshold by average power signal, the average power signal calculated is deducted upper threshold by a subtracter by this branch road, this difference is multiplied by by a multiplier can establish coefficient coe_1 to obtain result D1, D1 bit wide 10 bit, by an adder, D1 adds that 10 bit control register R1 values obtain result add, if result add most-significant byte is more than 255, remain 255, add bit wide 10 bit.The most-significant byte of add is sent data selector by adder.
AGC control word mainly reduces signal is amplified lower than the Lower Threshold branch road of Lower Threshold by average power signal, lower threshold is deducted by a subtracter average power signal calculated by this branch road, this difference being multiplied by by a multiplier to establish coefficient coe_2 to obtain result D2, D2 bit wide 20 bit, then 20 bit control register R2 values are deducted D2 by a subtracter and obtain result sub, sub is less than 0 and remains 0, sub bit wide 20 bit, the most-significant byte of sub is sent data selector by subtracter.
The main points that realize of this asymmetric adjustment speed AGC controller circuitry are that DC filtering is carried out to the digital signal after ADC sampling in its inside first, the average power of digital signal after calculation of filtered again, then compares average power and the double threshold (high and low thresholds) preset.If average power is higher than Upper threshold, then enter the average power that is made up of multiplier, control word register, the adder subtracter Upper threshold branch road higher than Upper threshold; If average power is lower than Lower Threshold, then enter the average power that is made up of multiplier, control word register, the subtracter Lower Threshold branch road lower than Lower Threshold.Article two, the multiplier controllable factor on thresholding branch road carries out coarse adjustment to convergence adjustment speed, and the bit wide of control word register R1, R2 carries out fine tuning to convergence adjustment speed, and both combine and just achieve asymmetric adjustment speed controlled arbitrarily.Multiplier controllable factor is larger, and control word register bit wide is less, then AGC control word value adjusts faster, and signal amplifies or decays also faster; Otherwise AGC control word value adjusts slower, signal amplifies or decays also slower.Analyze from this physical circuit of design, if the multiplier controllable factor on two thresholding branch roads is identical, because control word register R1 is 10 bits, R2 is 20 bits, so when average power signal lower than during Lower Threshold convergence adjustment speed be that average power signal is higher than 1/ during Upper threshold (2^10).
The Output rusults of data selector and low 2 data being spliced into 10 bits of add carry out assignment to 10 bit control register R1, carry out assignment with low 12 data being spliced into 20 bits of sub to 20 bit control register R2.The object of such process is to deposit the AGC control word that latest computed goes out, and calculates adjustment to AGC control word once on carrying out based on the Received signal strength on this control word basis.Within such loop feedback constantly adjusts and finally makes the watt level of Received signal strength drop on double threshold.
Consult Fig. 3.Corresponding above-mentioned asymmetric adjustment speed AGC controller circuit structure, asymmetric adjustment speed AGC controller control flow mainly comprises following step:
Step 1: intermediate-freuqncy signal DC filtering.Intermediate-freuqncy signal is sampled by analog to digital converter ADC, and the digital signal after AD conversion is carried out DC filtering by DC filtering circuit, to remove the impact that this non-signal of direct current composition calculates follow-up AGC control word.
Step 2: calculate average power signal.Asymmetric adjustment speed AGC controller adopts and fixedly to count instantaneous power cumulative mean, the computational methods such as digital envelope detection, to be averaged power calculation to the digital signal after above-mentioned DC filtering.
Step 3: compare with predetermined threshold value.The average power signal that asymmetric adjustment speed AGC controller calculates and the high and low thresholds preset, namely double threshold is made comparisons, if average power is just in time within double threshold, then keep sending the K bit AGC control word of numerical-control attenuator constant, if average power is higher than Upper threshold or lower than Lower Threshold, then enters the corresponding thresholding branch road of step 4 and carry out control word calculating.
Step 4: if the average power that step 2 calculates is greater than Upper threshold, the difference that average power is deducted Upper threshold by asymmetric adjustment speed AGC controller is multiplied by controllable factor coe_1 and obtains step value D1, then the value of M-bit control word register R1 is added D1 and deposits, the control word register R1 high K bit intercepted after depositing send numerical-control attenuator as AGC control word, simultaneously the control word register R1 height K position assignment after depositing to the high K position of the N bit register R2 on another thresholding branch road; If average power is less than Lower Threshold, difference Lower Threshold being deducted average power is multiplied by controllable factor coe_2 and obtains step value D2, then the value of N bits control words register R2 is deducted D2 and deposits, the register R2 high K bit intercepted after depositing send numerical-control attenuator as AGC control word, simultaneously the control word register R2 height K position assignment after depositing to the high K position of the M-bit register R1 on another thresholding branch road, wherein, K≤M, K≤N.Multiplier controllable factor is larger, and control word register bit wide M and N is less, then AGC control word value adjusts faster, and signal amplifies or decays also faster; Otherwise AGC control word value adjusts slower, signal amplifies or decays also slower.
Step 5: asymmetric adjustment speed AGC controller has just carried out the calculating that one takes turns AGC control word after step 4.The AGC control word that asymmetric adjustment speed AGC controller selects corresponding thresholding branch road to calculate according to the relation of average power and double threshold send numerical-control attenuator to carry out the adjustment of signal, then the control word calculating that step 1 carries out a new round is got back to again, within constantly adjusting signal power size to double threshold by such loop.
As can be seen here, if this AGC control circuit is applied in special discontinuous communication receiving system, when to be in for a long time receive small-power noise time, because average power is lower than Lower Threshold, the now convergence of AGC controller is regulated the speed very slow, AGC control word declines also just very slow, signal can not be put too much when strong signal arrives by the time based on current control word.Then once average power is regulated the speed very fast higher than the convergence of AGC controller after Upper threshold, AGC control word increases also just fast, thus within rapidly average power signal being adjusted to double threshold, can not cause follow-up demodulation mistake.So also just effectively compensate for the drawback of traditional AGC controller under this specific communication pattern, and realize simple, take resource few, can be realized in digit chip efficiently and use.
Claims (10)
1. the wireless receiving front end containing asymmetric adjustment speed AGC controller, comprise low noise amplifier in sequential series, numerical-control attenuator, with low-converter and the analog to digital converter ADC of local oscillator, it is characterized in that: the output series connection asymmetric adjustment speed AGC controller of analog to digital converter ADC, wherein, after the radiofrequency signal that antenna receives by low noise amplifier is amplified, decayed by numerical-control attenuator, intermediate-freuqncy signal is converted to through low-converter, intermediate-freuqncy signal carries out hits word processing by analog to digital converter ADC, deliver to asymmetric adjustment speed AGC controller and carry out the calculating of AGC control word, control word result of calculation feeds back to the numerical-control attenuator of radio-frequency front-end, form the AGC control word cycle calculations loop of a new round, within constantly adjusting signal power size to double threshold by the cycle calculations loop introducing radio receiver front end like this, asymmetric adjustment speed AGC controller inside adopts these two key parameters of bit wide of multiplier controllable factor and control word register to decide AGC control word adjustment speed, and by reducing AGC control word and strengthening in this both direction and adopt asymmetric adjustment speed controlled arbitrarily, realize the control to asymmetric adjustment speed controlled arbitrarily in the amplification of signal and this both direction that decays.
2. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 1, is characterized in that: low noise amplifier is the amplifier of a unadjustable multiplication factor.
3. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 1, it is characterized in that: amplifier and numerical-control attenuator are correspond to the reduction and increasing that asymmetric adjustment speed AGC controller feeds back to the AGC control word of numerical-control attenuator to realize to the amplification of signal and this both direction that decays, the AGC control word feeding back to numerical-control attenuator is larger, and the decay of numerical-control attenuator to signal is larger; The AGC control word feeding back to numerical-control attenuator is less, and the decay of numerical-control attenuator to signal is less, is equal to and amplifies larger by signal.
4. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 1, it is characterized in that: asymmetric adjustment speed AGC controller contains Upper threshold branch road and Lower Threshold branch road, the speed speed that multiplier controllable factor on these two branch roads and these two key parameter control AGC control words of the bit wide of control word register reduce and increase, and then the control realizing the asymmetric convergence adjustment speed of signal being amplified and decays in both direction.
5. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 1, it is characterized in that: asymmetric adjustment speed AGC controller circuitry comprises: the subtracter branch road being connected on multiplier front and back end, be connected on the subtracter of multiplier front end and be connected on the adder branch road of multiplier rear end, be connected in parallel between two subtracter parallel connections by the multiplier front end on above-mentioned two branch roads, wherein, DC filtering circuit in sequential series, average power meter of fixedly counting calculates circuit, fixing double threshold comparator and data selector, subtracter is by multiplier series type adder, the 10 bit control register R1 that adder input is connected form the Upper threshold branch road of average power signal higher than Upper threshold, subtracter to be connected another subtracter by multiplier, and the 20 bit control register R2 that this subtracter input is connected form the Lower Threshold branch road of average power signals lower than Lower Threshold.
6. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 5, it is characterized in that: 10 bit control register R1 connect the splicer be connected in parallel between adder and data selector, 20 bit control register R2 connect the splicer be connected in parallel between subtracter and data selector.
7. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 5, it is characterized in that: AGC control word is added ambassador's signal attenuation higher than the Upper threshold branch road of Upper threshold by average power signal, the average power signal calculated deducts upper threshold by a subtracter, this difference is multiplied by by a multiplier can establish coefficient coe_1 to obtain result D1, D1 bit wide 10 bit, by an adder, D1 adds that 10 bit control register R1 values obtain result add, the most-significant byte of add is sent data selector by adder.
8. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 7, it is characterized in that: AGC control word is reduced enable signal amplification lower than the Lower Threshold branch road of Lower Threshold by average power signal, lower threshold is deducted by a subtracter average power signal calculated by this branch road, this difference being multiplied by by a multiplier to establish coefficient coe_2 to obtain result D2, D2 bit wide 20 bit, then 20 bit control register R2 values are deducted D2 by a subtracter and obtain result sub, the most-significant byte of sub is sent data selector by subtracter.
9. as right wants the wireless receiving front end containing asymmetric adjustment speed AGC controller as described in 6, it is characterized in that: multiplier controllable factor carries out coarse adjustment to convergence adjustment speed, the bit wide of control word register R1, R2 carries out fine tuning to convergence adjustment speed, and both combine and just achieve asymmetric adjustment speed controlled arbitrarily.
10. the wireless receiving front end containing asymmetric adjustment speed AGC controller as claimed in claim 7, it is characterized in that: the Output rusults of data selector and low 2 data being spliced into 10 bits of add carry out assignment to 10 bit control register R1, with low 12 data being spliced into 20 bits of sub, assignment is carried out to 20 bit control register R2, deposit the AGC control word that latest computed goes out, and adjustment is calculated to AGC control word once on carrying out based on the Received signal strength on this control word basis.
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| CN114024635A (en) * | 2021-11-17 | 2022-02-08 | 南京长峰航天电子科技有限公司 | Wide signal measurement method and device considering signal-to-noise ratio |
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