CN113097206A - Electrostatic protection circuit and electrostatic protection network - Google Patents

Electrostatic protection circuit and electrostatic protection network Download PDF

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Publication number
CN113097206A
CN113097206A CN202110355616.0A CN202110355616A CN113097206A CN 113097206 A CN113097206 A CN 113097206A CN 202110355616 A CN202110355616 A CN 202110355616A CN 113097206 A CN113097206 A CN 113097206A
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pad
electrostatic
protection circuit
electrostatic protection
energy storage
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CN202110355616.0A
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CN113097206B (en
Inventor
孙豳
李新
应战
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0266—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using field effect transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0288—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using passive elements as protective elements, e.g. resistors, capacitors, inductors, spark-gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

The application provides an electrostatic protection circuit and electrostatic protection network sets up between first pad and second pad, still sets up internal circuit between first pad and second pad, and internal circuit has first end and second end, includes: a monitoring unit for monitoring an electrostatic pulse on the first pad caused by the electrostatic charge; the drain transistor is used for conducting after monitoring the electrostatic pulse so as to drain electrostatic charges; and the first end of the energy storage element is connected with the first bonding pad, and the second end of the energy storage element is connected with the first end of the internal circuit and is used for storing partial static charges. The scheme can realize timely discharge of electrostatic charges when the electrostatic pulse arrives and can also ensure the discharge capacity of the circuit.

Description

Electrostatic protection circuit and electrostatic protection network
Technical Field
The present application relates to the field of integrated circuit technologies, and in particular, to an electrostatic protection circuit and an electrostatic protection network.
Background
Static electricity is ubiquitous, and without the electrostatic protection circuit, a chip is quickly damaged by static electricity introduced for various reasons, and is almost fatal by a single-shot.
Therefore, the chip is usually provided with an electrostatic protection circuit, and the electrostatic protection circuit is used for timely discharging electrostatic charges, so as to prevent the protected circuit from being invalid and even being burnt down due to the high voltage brought by the electrostatic charges.
Disclosure of Invention
The application provides an electrostatic protection circuit and an electrostatic protection network, and aims to provide a scheme which can timely discharge electrostatic charges when electrostatic pulses arrive and can also ensure the discharge capacity of the circuit.
The application provides an electrostatic protection circuit sets up between first pad and second pad, still sets up internal circuit between first pad and second pad, and internal circuit has first end and second end, includes:
a monitoring unit for monitoring an electrostatic pulse on the first pad caused by the electrostatic charge;
the drain transistor is used for conducting after monitoring the electrostatic pulse so as to drain electrostatic charges;
and the first end of the energy storage element is connected with the first bonding pad, and the second end of the energy storage element is connected with the first end of the internal circuit and is used for storing partial static charges.
Optionally, the energy storage element comprises an inductance.
Optionally, the monitoring unit comprises:
a monitoring resistor, the first end of which is connected with the first bonding pad;
and the first end of the monitoring capacitor is connected with the second end of the monitoring resistor, and the second end of the monitoring capacitor is connected with the second bonding pad.
Optionally, the method further comprises:
and the input end of the driving unit is connected with the output end of the monitoring unit, and the output end of the driving unit is connected with the control end of the bleeder transistor.
Optionally, the monitoring unit comprises:
a first end of the monitoring capacitor is connected with the first bonding pad;
and the first end of the monitoring resistor is connected with the second end of the monitoring capacitor, and the second end of the monitoring resistor is connected with the second bonding pad.
Optionally, the energy storage element includes a top metal line, a first end of the top metal line is connected to the first pad, and a second end of the top metal line is connected to the first end of the internal circuit.
Optionally, the top layer metal wire comprises a first segment, a second segment and a third segment; the first section is connected with the second section, and the included angle of the joint of the first section and the second section is less than 180 degrees; the second section is connected with the third section, and the included angle of the joint of the second section and the third section is less than 180 degrees.
Optionally, the projected shape of the second segment on the substrate includes a U-shape, a V-shape, a C-shape, an Ω -shape, a concave shape, or a convex shape.
Optionally, the second segment constitutes a non-closed coil, and two ends of the non-closed coil are respectively connected with the first segment and the third segment.
Optionally, the energy storage element further includes a second-top metal line and a via, the second-top metal line is connected to the second-top metal line through the via, and the second-top metal line, the via, and the second-top metal line form a loop.
Optionally, a projection of the first pad on the substrate overlaps a projection of the drain region of the bleeder transistor on the substrate.
Optionally, a projection of the first pad on the substrate is denoted as a first projection, a projection of the drain region on the substrate is denoted as a second projection, and the first projection is located within the second projection.
Optionally, the gate structure of the bleeder transistor is ring-shaped, and the drain region is located within the gate structure.
Optionally, the annular shape comprises a quadrilateral, a hexagon, an octagon.
Optionally, the gate structure of the bleeder transistor is centrosymmetric with respect to a center point of the drain region.
The application provides an electrostatic protection network of a chip, the chip comprises two first bonding pads and two second bonding pads, the two first bonding pads are respectively marked as a first bonding pad P1, a first bonding pad P2, a second bonding pad P1 and a second bonding pad P2, and an electrostatic protection circuit is arranged between the first bonding pad P1 and the second bonding pad P1 and is marked as a first electrostatic protection circuit; the electrostatic protection circuit is arranged between the first bonding pad P2 and the second bonding pad P2 and is marked as a second electrostatic protection circuit; a third electrostatic protection circuit is arranged between the first bonding pad P1 and the first bonding pad P2; a fourth electrostatic protection circuit is provided between the second pad P1 and the second pad P2.
Optionally, the third electrostatic protection circuit comprises a first diode; when the voltage of the first pad P1 in normal operation is less than that of the first pad P2 in normal operation, the positive end of the first diode is connected with the first pad P1, and the negative end of the first diode is connected with the first pad P2; when the voltage of the first pad P1 in normal operation is greater than the voltage of the first pad P2 in normal operation, the positive terminal of the first diode is connected to the first pad P2, and the negative terminal of the first diode is connected to the first pad P1.
Optionally, the fourth electrostatic protection circuit comprises a second diode and a third diode; the positive terminal of the second diode is connected with the second pad P1, and the negative terminal of the second diode is connected with the second pad P2; the positive terminal of the third diode is connected to the second pad P2, and the negative terminal of the third diode is connected to the second pad P1.
Optionally, a first energy storage element is arranged between the first pad P1 and the first end of the first internal circuit; a second energy storage element is arranged between the second bonding pad P1 and the second end of the first internal circuit; a third energy storage element is arranged between the first bonding pad P2 and the first end of the second internal circuit; a fourth energy storage element is provided between the second pad P2 and the second end of the second internal circuit.
The utility model provides an electrostatic protection circuit, detect the electrostatic pulse back on first pad, the bleeder transistor in time switches on, the partial electrostatic charge of bleeding, energy storage element passes through the mode of the partial electrostatic charge of storage simultaneously, make the electrostatic pulse current that flows to the internal circuit weaken greatly, effectively protect the internal circuit, make the internal circuit need not to bear the high pressure that the electrostatic pulse brought, and absorb the energy in the electrostatic charge simultaneously by bleeder transistor and energy storage element, improve the biggest electrostatic charge amount that whole electrostatic protection circuit can bear, and the size of the bleeder transistor who uses is little, can evenly switch on when electrostatic pulse arrives, guarantee the robustness of the discharge capacity of bleeder transistor, promote the protective properties of whole electrostatic protection circuit.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and together with the description, serve to explain the principles of the application.
Fig. 1 is a circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure;
fig. 2 is a circuit diagram of an electrostatic protection circuit according to an embodiment of the present disclosure;
fig. 3 is a circuit diagram of an electrostatic protection circuit according to another embodiment of the present disclosure;
fig. 4 is a circuit diagram of an electrostatic protection circuit according to another embodiment of the present disclosure;
fig. 5 is a circuit diagram of an electrostatic protection circuit according to another embodiment of the present disclosure;
fig. 6 is a front view of an electrostatic protection circuit according to another embodiment of the present disclosure;
fig. 7 is a top view of an esd protection circuit structure according to another embodiment of the present application;
fig. 8 is a top view of a gate structure of a bleeder transistor according to another embodiment of the present application;
fig. 9a to 9f are top views of energy storage devices according to another embodiment of the present disclosure;
fig. 10 is a top view of an energy storage element according to another embodiment of the present disclosure;
FIG. 11 is a schematic diagram of an electrostatic protection network of a chip;
FIG. 12 is an embodiment of the ESD3 of FIG. 11;
fig. 13 is an embodiment of the ESD4 of fig. 11.
With the above figures, there are shown specific embodiments of the present application, which will be described in more detail below. These drawings and written description are not intended to limit the scope of the inventive concepts in any manner, but rather to illustrate the inventive concepts to those skilled in the art by reference to specific embodiments.
Detailed Description
Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present application, as detailed in the appended claims.
As shown in fig. 1, an embodiment of an electrostatic protection circuit is disposed between a power supply terminal VDD and a ground terminal GND. An inverter M is arranged between the monitoring unit 102 and the bleeder transistor T, the monitoring unit 101 monitors the electrostatic pulse, the inverter M is turned on according to the monitoring result, the larger bleeder transistor T is driven by the inverter M, and the driving current of the inverter M is designed according to the size of the bleeder transistor T. The peak current of the electrostatic charge leakage can reach 1.5A, which requires that the size of the leakage transistor 101 is larger, and the larger leakage transistor T can be quickly turned on only by the larger driving current, at a moment when the electrostatic pulse arrives, the embodiment of fig. 1 has a risk of non-timely conduction or non-uniform conduction due to the oversize size of the leakage transistor T, and the electrostatic charge cannot be timely leaked, so that the protected circuit of the chip still has a risk of being damaged.
As shown in fig. 2, the present application provides an electrostatic protection circuit 100, wherein the electrostatic protection circuit 100 is disposed between a first pad 301 and a second pad 302. An internal circuit 200 is further provided between the first pad 301 and the second pad 302, the internal circuit 200 being provided with a first end and a second end.
The electrostatic protection circuit 100 includes a monitoring unit 102, a bleeding transistor 101, and an energy storage element 103. The energy storage element 103 is provided with a first end and a second end, the first end of the energy storage element 103 is connected to the first pad 301, the second end of the energy storage element 103 is connected to the first end of the internal circuit 200, and the second end of the internal circuit 200 is connected to the second pad 302.
The monitoring unit 102 is configured to monitor an electrostatic pulse caused by the electrostatic charge on the first pad 301, the discharging transistor 101 is configured to turn on to discharge the electrostatic charge after the monitoring of the electrostatic pulse, and the energy storage element 103 is configured to store a part of the electrostatic charge.
After monitoring the electrostatic pulse on the first pad 301, the monitoring unit 102 controls the bleeding transistor 101 to be turned on in time to bleed off a part of electrostatic charge, the electrostatic pulse also flows to the internal circuit 200 through the energy storage element 103, because the energy storage element 103 can also store a part of electrostatic charge, and the electrostatic pulse can be regarded as a high-frequency signal, when the high-frequency signal arrives at an instant, the equivalent impedance value of the energy storage element 103 to the high-frequency signal will rise sharply, so that the electrostatic pulse can be effectively blocked from flowing to the internal circuit, and through the bleeding of the electrostatic charge by the bleeding transistor 101 and the storage and blocking of the electrostatic charge by the energy storage element 103, the intensity or amplitude of the electrostatic pulse flowing to the internal circuit 200 is weakened, thereby reducing the damage of the electrostatic pulse to the internal circuit 200.
On one hand, the leakage transistor 101 is used for leaking the electrostatic charges, and on the other hand, the energy storage element 103 is used for storing and blocking part of the electrostatic charges, so that the maximum electrostatic charge amount which can be borne by the whole electrostatic protection circuit is improved, namely the electrostatic protection capability of the whole electrostatic protection circuit is improved.
More specifically, as shown in fig. 3, the first pad 301 is a power supply pad VDD, the second pad 302 is a ground pad GND, the energy storage element 103 includes an inductor L1, a first terminal of the inductor L1 is connected to the first pad 301, a second terminal of the inductor L1 is connected to the first terminal of the internal circuit 200, and a second terminal of the internal circuit 200 is connected to the second pad 302.
The monitoring unit 102 comprises a monitoring resistor R1 and a monitoring capacitor C1, wherein the monitoring resistor R1 is provided with a first end and a second end, and the monitoring capacitor C1 is also provided with a first end and a second end. The first terminal of the monitor capacitor C1 is connected to the first pad 301, and the second terminal of the monitor resistor R1 is connected to the second pad 302. The second terminal of the monitor capacitor C1 is connected to the first terminal of the monitor resistor R1 as the output terminal of the monitor unit 102.
The bleeder transistor 101 is an N-type transistor, a gate of the bleeder transistor 101 is connected to an output terminal of the monitoring unit 102, a drain of the bleeder transistor 101 is connected to the first pad 301, and a source of the bleeder transistor 101 is connected to the second pad 302.
The principle of the electrostatic protection circuit 100 shown in fig. 3 is described below: the equivalent impedance of the monitoring capacitor C1 to the high frequency signal is 1/(2 × pi × f × C1), and the smaller the rise time, the higher the frequency of the signal, and the smaller the equivalent impedance of the monitoring capacitor C1. When the electrostatic pulse arrives, the equivalent impedance of the monitoring capacitor C1 drops sharply, the voltage at the node D1 is approximately the power supply voltage VDD, the monitoring unit 102 outputs a high-level signal, the drain transistor N0 is turned on gradually, and a part of the electrostatic charges is drained by the drain transistor N0.
The equivalent impedance of the inductor L1 to the high-frequency signal is 2 × pi × f × L1, and when the rise time is smaller, the frequency of the signal is higher, the equivalent impedance of the inductor L1 is higher, that is, the amount of electrostatic charge stored in the inductor L1 is larger, so that the electrostatic pulse current can be effectively isolated, the intensity of the electric pulse current flowing to the internal circuit is weakened, and the leakage transistor 101 also leaks part of electrostatic charge, so that when the electrostatic pulse arrives, the voltage on the internal circuit is prevented from rising too fast due to the accumulation of the electrostatic charge, and the effect of protecting the internal circuit 200 is achieved.
In the above technical solution, after the electrostatic pulse is detected on the first pad 301, the leakage transistor 101 is turned on in time to leak a part of the electrostatic charge, and the energy storage element 103 weakens the intensity or amplitude of the electrostatic pulse flowing to the internal circuit 200 by storing a part of the electrostatic charge, thereby effectively protecting the internal circuit 200 and reducing the damage of the electrostatic pulse to the internal circuit 200. The leakage transistor 101 leaks most of the electrostatic charges and the energy storage element 103 stores a small amount of electrostatic charges, so that the maximum electrostatic charge amount borne by the whole electrostatic protection circuit is increased, and the electrostatic protection capability of the electrostatic protection circuit is improved.
As shown in fig. 4, the present application provides an electrostatic protection circuit 100, wherein the electrostatic protection circuit 100 is disposed between a first pad 301 and a second pad 302. An internal circuit 200 is further provided between the first pad 301 and the second pad 302, the internal circuit 200 further having a first end and a second end.
The electrostatic protection circuit 100 includes a monitoring unit 102, a bleeding transistor 101, an energy storage element 103, and a driving unit 104. The energy storage element 103 is provided with a first end and a second end, the first end of the energy storage element 103 is connected to the first pad 301, the second end of the energy storage element 103 is connected to the first end of the internal circuit 200, and the second end of the internal circuit 200 is connected to the second pad 302. The driving unit 104 is provided with an input end and an output end, the input end of the driving unit 104 is connected with the output end of the monitoring unit 102, and the output end of the driving unit 104 is connected with the control end of the bleeder transistor 101.
After the monitoring unit 102 monitors the electrostatic pulse on the first pad 301, the driving unit 104 controls the drain transistor 101 to be turned on, the drain transistor 101 drains part of the electrostatic charge, the electrostatic pulse further flows to the internal circuit 200 through the energy storage unit 103, because the energy storage element 103 can store part of the electrostatic charge, the function of isolating the direct current is achieved, the electrostatic pulse current can be regarded as a high-frequency current signal, the electrostatic pulse current flowing through the internal circuit 200 is obviously weakened, and the internal circuit 200 can be protected from bearing high voltage.
More specifically, as shown in fig. 5, the first pad 301 is a power supply pad VDD, the second pad 302 is a ground pad GND, the energy storage element 103 includes an inductor L1, a first terminal of the inductor L1 is connected to the first pad 301, a second terminal of the inductor L1 is connected to the first terminal of the internal circuit 200, and a second terminal of the internal circuit 200 is connected to the second pad 302.
The monitoring unit 102 comprises a monitoring resistor R1 and a monitoring capacitor C1, wherein the monitoring resistor R1 is provided with a first end and a second end, and the monitoring capacitor C1 is also provided with a first end and a second end. The first terminal of the monitor resistor R1 is connected to the first pad 301, and the second terminal of the monitor resistor R1 is connected to the second pad 302. The second terminal of the monitor resistor R1 is connected to the first terminal of the monitor capacitor C1 as the output terminal of the monitor unit 102.
The driving unit 104 includes a first driving transistor P1 and a second driving transistor N1, the first driving transistor P1 is a P-type transistor, the second driving transistor N1 is an N-type transistor, a source of the first driving transistor P1 is connected to the first pad 301, and a source of the second driving transistor N1 is connected to the second pad 302. The drain of the first driving transistor P1 and the drain of the second driving transistor N1 are connected to each other and then serve as the output terminal of the driving unit 104. The gate of the first driving transistor P1 and the gate of the second driving transistor N1 are connected to each other and then serve as input terminals of the driving unit 104.
The bleeder transistor 101 is an N-type transistor, a gate of the bleeder transistor 101 is connected to an output terminal of the driving unit 104, a drain of the bleeder transistor 101 is connected to the first pad 301, and a source of the bleeder transistor 101 is connected to the second pad 302.
The principle of the electrostatic protection circuit 100 shown in fig. 5 is described below: when the electrostatic pulse arrives, since the equivalent impedance of the monitoring capacitor C1 drops sharply under the high frequency signal, the voltage of the node D1 is approximately GND, the monitoring unit 102 outputs a low level signal, the first driving transistor P1 is gradually turned on, then the voltage of the node D2 is pulled to the power supply voltage VDD, the drain transistor N0 is gradually turned on, and the electrostatic charge is drained by the drain transistor N0.
The electrostatic pulse on the first pad 301 is a high frequency pulse signal, the frequency of the high frequency pulse signal reaches GHz level in general, and the inductor L1 is used for alternating current and direct current, and the formula R is calculated according to the equivalent impedance of the inductor L12 pi f L1, the higher the frequency of the VDD pulse signal, the greater the impedance of the inductor L1 to the high frequency pulse signal. For example, when the inductance of the inductor is 0.42nH (equivalent to the inductance generated by a metal coil having a diameter of 6.6 μm) and the frequency of the electrostatic pulse is 1GHz, the equivalent impedance R of the inductor is set to be equal toL1About 2.6 ohms.
That is, when the electrostatic pulse arrives, the equivalent impedance of the inductor L1 is obviously increased, which can effectively isolate the electrostatic pulse current, reduce the intensity of the electrostatic pulse flowing to the internal circuit, and prevent the voltage on the internal circuit from rising too fast due to the accumulation of electrostatic charges, thereby playing the role of protecting the internal circuit 200. Although the impedance of L1 is only a few ohms, when the peak value of the electrostatic current is at an ampere level, a voltage drop of a few volts is generated, and the leakage transistor 101 leaks the electrostatic charge, so that the voltage drop of the internal circuit 200 at the time of the electrostatic pulse can be reduced, thereby reducing the damage of the internal circuit 200 caused by the static electricity.
In the above technical solution, after the monitoring unit 102 monitors the electrostatic pulse, the driving unit 104 controls the conduction of the drain transistor 101, the drain transistor 101 drains the electrostatic charge, the electrostatic pulse flows into the internal circuit 200 through the inductor, the equivalent impedance of the inductor is significantly improved when the electrostatic pulse arrives, and the voltage drop caused by most of the electrostatic pulse can be borne, so that the voltage drop on the internal circuit 200 can be reduced when the electrostatic pulse arrives, and the effect of protecting the internal circuit 200 is further achieved.
Fig. 6 and fig. 7 are schematic structural diagrams of an electrostatic protection circuit 100 according to an embodiment of the invention.
Fig. 6 is a front view of the electrostatic protection circuit 100, and fig. 7 is a top view of the electrostatic protection circuit 100.
Referring to fig. 6 and 7, a top metal layer M3, a second top metal layer M2, a third metal layer M1, and a fourth metal layer M0 are sequentially disposed from top to bottom. The top metal layer M3 and the second top metal layer M2 are connected by a via V3, the second top metal layer M2 and the third metal layer M1 are connected by a via V2, and the third metal layer M1 and the fourth metal layer M0 are connected by a via V1.
The electrostatic protection circuit 100 includes a leakage transistor 101, and the leakage transistor 101 is located on the substrate 10 and is used for leaking electrostatic charges. The bleeder transistor 101 is provided with a drain region 111, a source region 112 and a gate structure 113. The drain region 111 and the fourth metal layer M0 are electrically connected through the contact hole 120. The contact hole 120 is typically a semiconductor material.
The first pad 301 is located on the top metal layer M3, the first pad 301 is electrically connected to the drain region 111 of the bleeder transistor 101, and more specifically, the first pad 301 is connected to the drain region 111 through the via hole V3, the second top metal layer M2, the via hole V2, the third metal layer M1, the via hole V1, the fourth metal layer M0, and the contact hole 120.
Wherein, the projection of the first pad 301 on the substrate 10 overlaps with the projection of the drain region 111 on the substrate 10. In one embodiment, the projection of the first pad 301 on the substrate 10 is a first projection, and the projection of the drain region 111 on the substrate 10 is a second projection, and the first projection is located in the second projection. So set up, on the one hand, be favorable to further reducing the effective area of electrostatic protection device, and then in the direction that is on a parallel with substrate 10 surface, for other electronic component reservation spaces. On the other hand, the contact hole 120 between the fourth metal layer M0 and the drain region 111 of the bleeder transistor 101 is completely located below the first pad 301, the electrostatic pulse current directly reaches the drain region 111 of the bleeder transistor 101 from the first pad 301 through the via hole V3, the second-top metal layer M2, the via hole V2, the third metal layer M1, the via hole V1, the fourth metal layer M0, and the contact hole 120, the leakage current path is shortest, the parasitic resistance on the leakage path is reduced, the robustness of the leakage performance of the bleeder transistor 101 is ensured, and the current leakage performance of the entire electrostatic protection circuit 100 is significantly improved.
In one embodiment, the contact hole 120 may be, for example, a 4 × 4 array, or may be a larger contact hole, so that the parasitic resistance on the current bleeding path is smaller.
In this embodiment, the gate structure 113 of the bleeder transistor 101 is ring-shaped, and the drain region 111 is located in the gate structure 113. Thus, the uniformity of the leakage current is further improved, and the current leakage capability of the esd protection circuit 100 is further improved.
In this embodiment, the annular shape includes regular polygons such as a quadrangle, a hexagon, and an octagon, and the number of the side edges of the regular polygon is an even number.
In this embodiment, the inner corners of the annular shape are each greater than 90 degrees. Referring to fig. 8, taking the circular shape of the gate structure 113 as a regular quadrangle as an example, the inner contour of the circular shape has a first corner θ 1, and the outer contour has a second corner θ 2, and the first corner θ 1 and the second corner θ 2 of the circular shape are made larger than 90 degrees by providing chamfers at the inner contour corner and the outer contour corner of the circular shape. Therefore, the current impact strength at the corner of the gate structure 113 is reduced, the corner is prevented from being aged and damaged in advance due to too strong current impact, and the bleeder transistor 101 is ensured to have a longer service life.
It should be noted that the number of the small sides formed by the chamfers is not counted in the number of the sides of the ring shape; furthermore, in other embodiments, it is also possible to adjust only the first corner of the inner contour or only the second corner of the outer contour, i.e. to provide chamfers only at the corners of the inner contour or the outer contour.
In this embodiment, the gate structure of the leakage transistor 101 is centrosymmetric with respect to the central point of the drain region, which is beneficial to leakage of electrostatic charges and improves the current leakage capability of the electrostatic protection circuit 100.
With continued reference to fig. 7, the fourth metal layer M0 under the first pad 301 needs to provide the power supply VDD for other internal circuits 200, so that enough space is left for leading out the power supply VDD, which is led out from four corners of the quadrangle in this embodiment. The power supply VDD may also be led out from four sides of the quadrangle of the fourth metal layer M0 in a manner of being spaced from the ground terminal VSS by the power supply VDD, which is not limited herein.
As shown in fig. 9a, the esd protection circuit 100 further includes an energy storage element 103, the energy storage element 103 is located on the top metal layer, and the energy storage element 103 is used for storing electrostatic charges. The energy storage element 103 includes a top metal line having a first end 1034 and a second end 1037 (not shown), the first end 1034 of the top metal line is connected to the first pad 301, and the second end 1037 (not shown) of the top metal line is connected to the first end of the internal circuit 200.
The top layer metal line includes a first segment 1031, a second segment 1032, and a third segment 1033. The first section 1031 is connected with the second section 1032, and an included angle at the connection position of the first section 1031 and the second section 1032 is smaller than 180 degrees. That is, the first section 1031 and the second section 1032 do not form a straight line. The second section 1032 is connected with the third section 1033, and an included angle between a connection part of the second section 1032 and the third section 1033 is less than 180 degrees, that is, the second section 1032 and the third section 1033 do not form a straight line. By so setting, the energy storage parameter of the storage element can be adjusted to increase the energy storage capacity of the energy storage element 103. For example: when the energy storage element 103 is an inductor, the inductance of the inductor can be increased.
In one embodiment, as shown in fig. 9a, the projection shape of the second segment 1032 on the substrate is U-shaped, as shown in fig. 9b, the projection shape of the second segment 1032 on the substrate is V-shaped, as shown in fig. 9C, the projection shape of the second segment 1032 on the substrate is C-shaped, as shown in fig. 9d, the projection shape of the second segment 1032 on the substrate is Ω -shaped, as shown in fig. 9e, the projection shape of the second segment 1032 on the substrate is concave, as shown in fig. 9f, and the projection shape of the second segment 1032 on the substrate is convex, and by providing the second segment 1032 with the above-mentioned shapes, the energy storage capacity of the energy storage element 103 is increased, and the production and manufacturing of the energy storage element 103 are also facilitated.
It is particularly noted that the embodiments of fig. 9a to 9f do not constitute a limitation of the energy storage element 103. In fact, the energy storage elements in fig. 9a to 9f are not strictly energy storage elements, but the energy storage elements in this application should be understood as structures with certain energy storage characteristics, either inductive structures or metal lines with certain parasitic inductance, such as the embodiments in fig. 9a to 9f, although only the top metal lines are arranged in a specific shape, such arrangement increases the parasitic inductance of the structure at least to some extent. The present application makes a special design for the trace from the first pad 301 to the internal circuit 200 on the premise of considering the electrostatic protection, and we do not limit the specific range of the parasitic inductance value on the trace, and it should not limit the present application.
In one embodiment, the second segment 1032 constitutes a non-closed coil, and both ends of the non-closed coil are connected to the first and third segments 1031 and 1033, respectively. By so setting, the energy storage parameter of the storage element can be adjusted to increase the energy storage capacity of the energy storage element 103.
The electrostatic pulse is a high-frequency pulse signal in nature, and the energy storage element 103 is arranged on the top metal layer, so that the energy storage element 103 has a signal reflection effect on the electrostatic pulse, and the peak value from the electrostatic pulse to the internal circuit 200 is weakened to a certain extent, that is, the adverse effect of the electrostatic pulse on the internal circuit 200 is reduced by using the impedance generated by the parasitic inductance and the equivalent impedance sudden change of a signal channel. In addition, by disposing the energy storage element 103 in the top metal layer, the parasitic resistance of the energy storage element 103 can be reduced, and the influence of the energy storage element 103 on the normal power-up and normal operation of the internal circuit 200 can be reduced.
In other embodiments, as shown in fig. 10, the energy storage element 103 is located in the top metal layer and the next-to-top metal layer, the energy storage element 103 includes a top metal line M3_1, a next-to-top metal line M2_1, and a via V3, the top metal line M3_1 is connected to the next-to-top metal line M2_1 through a via V3, and the top metal line M3_1, the via V3, and the next-to-top metal line M2_1 form a loop.
The first end 1034 of the top-level metal line M3_1 is connected to the first pad 301, the second end 1035 of the top-level metal line M3_1 is connected to the first end of the via V3_1, the second end of the via V3_1 is connected to the first end of the next-to-top-level metal line M2_1, the second end 1036 of the next-to-top-level metal line M2_1 is connected to the first end of the via V3_2, the second end of the via V3_2 is connected to the first end of the top-level metal line M3_2, and the second end (not shown) of the top-level metal line M3_2 is connected to the first end of the internal circuit 200. The via V3_1 and the via V3_2 are vias connecting the top metal layer M3 and the next-to-top metal layer M2.
Between the first pad 301 and the internal circuit 200, the top metal layer M3, the via V3, and the second top metal layer M2 form a "loop" shaped trace, and the "loop" shaped trace is similar to a metal coil, so that the inductance value of the inductor L1 can be increased to some extent.
Through the routing, parasitic inductance is generated between the first pad 301 and the internal circuit 200, but parasitic resistance is generated at the same time, and the length or the diameter of the loop-shaped routing needs to be designed according to the normal power-on rate and the electrostatic pulse rate of the internal circuit 200, so that on one hand, the generated parasitic inductance can absorb electrostatic charge, and the internal circuit 200 is prevented from bearing high voltage caused by electrostatic pulse, and on the other hand, the generated parasitic inductance and parasitic resistance cannot influence the normal power-on. Of course, the speed of normal power-up is about tens of microseconds, while the electrostatic pulse is usually only a few nanoseconds, which provides enough space for designing the inductance L1.
In the above technical solution, on one hand, the electrostatic charges on the first pad 301 are discharged to the drain region through the multiple metal layers, the through holes between the metal layers, and the contact holes between the metal layers and the drain region, and on the other hand, the energy storage element 103 is formed by arranging the routing of the metal lines on the top metal layer or the next top metal layer, so that at a moment when the electrostatic pulse arrives, the electrostatic charges on the first pad 301 are stored partially by the energy storage element 103. One part of the electrostatic charges is shunted and discharged through the discharge transistor 101, and the other part of the electrostatic charges is stored by the energy storage element 103, so that the intensity of the pulse current flowing to the internal circuit 200 through the energy storage element 103 can be weakened at the moment of arrival of the electrostatic pulse, and the internal circuit 200 is prevented from bearing high voltage.
Referring to fig. 11, the present application provides an electrostatic protection network for a chip, the chip includes a first pad VDD, a second pad VSS, a third pad VDDQ, and a fourth pad VSSQ, a first internal circuit is provided between the first pad VDD and the second pad VSS, a second internal circuit is provided between the third pad VDDQ and the fourth pad VSSQ, and the above electrostatic protection circuit is provided between the first pad VDD and the second pad VSS, which is denoted as a first electrostatic protection circuit ESD 1; the electrostatic protection circuit is arranged between the third bonding pad VDDQ and the fourth bonding pad VSSQ and is marked as a second electrostatic protection circuit ESD 2; a third electrostatic protection circuit ESD3 is arranged between the first bonding pad VDD and the third bonding pad VDDQ; a fourth electrostatic protection circuit ESD4 is provided between the second pad VSS and the fourth pad VSSQ.
Referring to fig. 12, fig. 12 shows an embodiment of a third ESD protection circuit ESD3, the third ESD protection circuit ESD3 includes a first diode D1; when the voltage of the first bonding pad VDD in normal operation is lower than the voltage of the third bonding pad VDDQ in normal operation (for example, the first bonding pad VDD is 1.0V, and the third bonding pad VDDQ is 1.1V), the positive end of the first diode D1 is connected to the first bonding pad VDD, and the negative end of the first diode is connected to the third bonding pad VDDQ; when the voltage of the first bonding pad VDD in normal work is larger than the voltage of the third bonding pad VDDQ in normal work, the anode end of the first diode is connected with the third bonding pad VDDQ, and the cathode end of the first diode is connected with the first bonding pad VDD. Fig. 12 illustrates a diode formed of a transistor having a gate and a drain connected as a positive terminal of the diode and a source as a negative terminal of the diode.
Referring to fig. 13, fig. 13 is an embodiment of a fourth ESD protection circuit ESD4, the fourth ESD protection circuit ESD4 including a second diode D2 and a third diode D3; the positive electrode end of the second diode D2 is connected with the second bonding pad VSS, and the negative electrode end of the second diode is connected with the fourth bonding pad VSSQ; the positive terminal of the third diode is connected to the fourth pad VSSQ, and the negative terminal of the third diode is connected to the second pad VSS.
With continued reference to fig. 11, the first pad VDD has a first energy storage element L1 between it and the first end of the first internal circuit; a second energy storage element L2 is arranged between the second bonding pad VSS and the second end of the first internal circuit; a third energy storage element L3 is provided between the third pad VDDQ and the first terminal of the second internal circuit; a fourth energy storage element L4 is provided between the fourth pad VSSQ and the second end of the second internal circuit. When the electrostatic pulse occurs on the first pad VDD, the first energy storage element L1 can attenuate damage of the electrostatic pulse to the first internal circuit; the second energy storage element L2 can attenuate damage of the first internal circuit by the electrostatic pulse when the electrostatic pulse occurs on the second pad VSS, the third energy storage element L3 can attenuate damage of the second internal circuit by the electrostatic pulse when the electrostatic pulse occurs on the third pad VDDQ, and the fourth energy storage element L4 can attenuate damage of the second internal circuit by the electrostatic pulse when the electrostatic pulse occurs on the fourth pad VSSQ. The first energy storage element L1, the second energy storage element L2, the third energy storage element L3, and the fourth energy storage element L4 have the structures of the embodiments shown in fig. 9a to 9f, and fig. 10.
Other embodiments of the present application will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the invention pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.
It will be understood that the present application is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims (19)

1. An electrostatic protection circuit provided between a first pad and a second pad, an internal circuit being further provided between the first pad and the second pad, the internal circuit having a first end and a second end, comprising:
a monitoring unit for monitoring an electrostatic pulse on the first pad caused by electrostatic charge;
a discharge transistor for conducting to discharge the electrostatic charge after monitoring the electrostatic pulse;
and the first end of the energy storage element is connected with the first bonding pad, and the second end of the energy storage element is connected with the first end of the internal circuit and is used for storing part of the electrostatic charges.
2. The esd protection circuit of claim 1, wherein the energy storage element comprises an inductor.
3. The electrostatic protection circuit according to claim 1, wherein the monitoring unit includes:
a monitoring resistor, the first end of which is connected with the first bonding pad;
and the first end of the monitoring capacitor is connected with the second end of the monitoring resistor, and the second end of the monitoring capacitor is connected with the second bonding pad.
4. The electrostatic protection circuit according to claim 3, further comprising:
and the input end of the driving unit is connected with the output end of the monitoring unit, and the output end of the driving unit is connected with the control end of the bleeder transistor.
5. The electrostatic protection circuit according to claim 1, wherein the monitoring unit includes:
a monitoring capacitor, the first end of which is connected with the first bonding pad;
and the first end of the monitoring resistor is connected with the second end of the monitoring capacitor, and the second end of the monitoring resistor is connected with the second bonding pad.
6. The ESD protection circuit of claim 1 wherein the energy storage element comprises a top metal line, a first end of the top metal line is connected to the first pad, and a second end of the top metal line is connected to the first end of the internal circuit.
7. The electrostatic protection circuit of claim 6, wherein the top layer metal line comprises a first segment, a second segment, and a third segment; the first section is connected with the second section, and an included angle at the joint of the first section and the second section is less than 180 degrees; the second section is connected with the third section, and an included angle at the joint of the second section and the third section is less than 180 degrees.
8. The ESD protection circuit of claim 7 wherein the projected shape of the second segment on the substrate comprises a U-shape, a V-shape, a C-shape, an omega-shape, a concave shape, or a convex shape.
9. The ESD protection circuit of claim 7 wherein the second segment forms a non-closed coil, and both ends of the non-closed coil are connected to the first segment and the third segment, respectively.
10. The ESD protection circuit of claim 6 wherein the energy storage element further comprises a top-next-level metal line and a via, the top-level metal line connected to the top-next-level metal line through the via, the top-level metal line, the via, and the top-next-level metal line forming a loop.
11. The electrostatic protection circuit according to claim 1, wherein a projection of the first pad on a substrate overlaps with a projection of the drain region of the bleeder transistor on the substrate.
12. The esd protection circuit of claim 11, wherein the projection of the first pad on the substrate is a first projection, and the projection of the drain region on the substrate is a second projection, and wherein the first projection is located within the second projection.
13. The esd protection circuit of claim 11, wherein the gate structure of the bleeder transistor has an annular shape, and the drain region is located within the gate structure.
14. The esd protection circuit of claim 13, wherein the annular shape comprises a quadrilateral, a hexagon, an octagon.
15. The ESD protection circuit of claim 13, wherein the gate structure of the bleeder transistor is centrosymmetric with respect to a center point of the drain region.
16. An electrostatic protection network of a chip, the chip includes two first pads, two second pads, respectively noted as first pad P1, first pad P2, second pad P1, second pad P2, its characterized in that:
the electrostatic protection circuit as claimed in any one of claims 1 to 15 is provided between the first pad P1 and the second pad P1, which is referred to as a first electrostatic protection circuit;
the electrostatic protection circuit as claimed in any one of claims 1 to 15 is provided between the first pad P2 and the second pad P2, and is referred to as a second electrostatic protection circuit;
a third electrostatic protection circuit is arranged between the first bonding pad P1 and the first bonding pad P2;
a fourth electrostatic protection circuit is provided between the second pad P1 and the second pad P2.
17. The electrostatic protection network of claim 16, wherein:
the third electrostatic protection circuit comprises a first diode;
when the voltage of the first pad P1 in normal operation is less than that of the first pad P2 in normal operation, the positive end of the first diode is connected with the first pad P1, and the negative end of the first diode is connected with the first pad P2;
when the voltage of the first pad P1 in normal operation is greater than the voltage of the first pad P2 in normal operation, the positive end of the first diode is connected with the first pad P2, and the negative end of the first diode is connected with the first pad P1.
18. The electrostatic protection network of claim 16, wherein:
the fourth electrostatic protection circuit comprises a second diode and a third diode;
the positive terminal of the second diode is connected with the second pad P1, and the negative terminal of the second diode is connected with the second pad P2;
the positive terminal of the third diode is connected to the second pad P2, and the negative terminal of the third diode is connected to the second pad P1.
19. The electrostatic protection network of claim 16, wherein:
a first energy storage element is arranged between the first bonding pad P1 and the first end of the first internal circuit;
a second energy storage element is arranged between the second bonding pad P1 and the second end of the first internal circuit;
a third energy storage element is arranged between the first bonding pad P2 and the first end of the second internal circuit;
a fourth energy storage element is arranged between the second bonding pad P2 and the second end of the second internal circuit.
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