CN113097135A - Method for improving wafer cutting performance and wafer structure - Google Patents

Method for improving wafer cutting performance and wafer structure Download PDF

Info

Publication number
CN113097135A
CN113097135A CN201911338582.3A CN201911338582A CN113097135A CN 113097135 A CN113097135 A CN 113097135A CN 201911338582 A CN201911338582 A CN 201911338582A CN 113097135 A CN113097135 A CN 113097135A
Authority
CN
China
Prior art keywords
wafer
metal
cutting
gap
pad
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201911338582.3A
Other languages
Chinese (zh)
Inventor
许乐
赵立新
李玮
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Geke Microelectronics Shanghai Co Ltd
Galaxycore Shanghai Ltd Corp
Original Assignee
Geke Microelectronics Shanghai Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Geke Microelectronics Shanghai Co Ltd filed Critical Geke Microelectronics Shanghai Co Ltd
Priority to CN201911338582.3A priority Critical patent/CN113097135A/en
Publication of CN113097135A publication Critical patent/CN113097135A/en
Pending legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/12—Measuring as part of the manufacturing process for structural parameters, e.g. thickness, line width, refractive index, temperature, warp, bond strength, defects, optical inspection, electrical measurement of structural dimensions, metallurgic measurement of diffusions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/10—Measuring as part of the manufacturing process
    • H01L22/14—Measuring as part of the manufacturing process for electrical parameters, e.g. resistance, deep-levels, CV, diffusions by electrical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00—Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/30—Structural arrangements specially adapted for testing or measuring during manufacture or treatment, or specially adapted for reliability measurements
    • H01L22/32—Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54426—Marks applied to semiconductor devices or parts for alignment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54453—Marks applied to semiconductor devices or parts for use prior to dicing
    • H01L2223/5446—Located in scribe lines

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Dicing (AREA)

Abstract

The invention provides a method for improving the cutting performance of a wafer and a wafer structure, wherein the wafer provided with a plurality of semiconductor chips is provided, the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel; and removing part of metal or all metal of the metal structure or the metal bonding pad along the cutting channel direction to form a gap so as to reduce the process difficulty in the cutting process, improve the cutting quality and improve the product performance of the semiconductor chip.

Description

Method for improving wafer cutting performance and wafer structure
Technical Field
The invention relates to a method for improving the cutting performance of a wafer and a wafer structure.
Background
As shown in fig. 1, in the integrated circuit manufacturing process, a plurality of semiconductor chips 2 are integrated on the same wafer 1, and fig. 2 and 3 are partially enlarged views of a region P in fig. 1, wherein two adjacent semiconductor chips 21 and 22 and a dicing street a-a between the semiconductor chips 21 and 22 are shown, and during the wafer dicing process, dicing is performed along the dicing street a-a to form individual semiconductor chips 21 and 22.
According to a preferred embodiment of the prior art shown in fig. 2, a metal structure 23 for alignment is provided on the scribe line a-a, the illumination laser is reflected by the metal structure 23 vertically incident on the wafer and then diffracted and returned, the positive and negative first-order diffracted lights are retained by a specially constructed filter, the diffracted lights are returned to the projection objective and then interfered with the mask mark, the two-dimensional alignment stack grid intensity information containing the mask mark and the metal structure 23 on the wafer is received by the photodetector, and finally, the moire signal function (sinusoidal relationship) of the light intensity along with the displacement of the wafer can be received by the photodetector after the mask grid.
According to another preferred embodiment of the prior art shown in fig. 3, a metal pad 24 for electrical property test or film thickness measurement is disposed on the scribe line a-a, wherein the current method for measuring film thickness is mainly elliptical polarization test, and the basic principle is that a laser beam is converted into linearly polarized light by a polarizer, then the linearly polarized light is converted into elliptically polarized light by an 1/4 wave plate, the polarization state (amplitude and phase) of the light is changed by reflection on the film surface to be measured, for a certain sample, a polarizing azimuth P can be always found, the reflected light is converted into linearly polarized light by elliptically polarized light, then an analyzer is rotated to obtain an extinction state under the corresponding azimuth a, and the film thickness is calculated by two azimuths a and P.
In the prior art, the metal structure 23 for alignment and the metal pad 24 for electrical test or film thickness measurement are all monolithic metals, and due to the reasons that the wafer 1 is thick, the metal structure 23 or the metal pad 24 is high in metal hardness, the subsequent cutting process is difficult to achieve, the cutting quality is difficult to guarantee, and the product performance of the semiconductor chip is affected.
Disclosure of Invention
The invention aims to provide a method for improving the cutting performance of a wafer and a wafer structure, which can reduce the process difficulty in the cutting process, improve the cutting quality and improve the product performance of a semiconductor chip.
Based on the above consideration, one aspect of the present invention provides a method for improving wafer dicing performance, comprising: providing a wafer provided with a plurality of semiconductor chips, wherein the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel; and removing part of metal or all of metal of the metal structure or the metal bonding pad along the cutting path direction to form a gap so as to reduce the difficulty of subsequent cutting.
Preferably, the metal is completely etched in the depth direction of the gap.
Preferably, the metal is partially etched in the depth direction of the gap.
Preferably, the position, size and shape of the gap are designed in advance to ensure the effectiveness of wafer alignment, electrical test or film thickness measurement.
Preferably, for the metal pad for film thickness measurement, the measurement performance is guaranteed to be higher than or equal to 0.9 in confidence.
Preferably, light spots are provided to irradiate the wafer, and the light spots respectively correspond to the metal pads for wafer measurement.
Preferably, when the ratio of the gap width to the metal pad width is greater than or equal to a threshold, the pad gap may be disposed in a non-middle region of the metal pad.
Preferably, the gap is realized by layout design, and the direction of the gap is consistent with the direction of the cutting street.
Preferably, the wafer is cut along the middle area of the metal structure or the metal bonding pad by adopting a laser invisible cutting process.
Preferably, the wafer is cut along the middle area of the metal structure or the metal pad by using a mechanical cutting mode.
Preferably, the wafer is cut through its entire thickness or a portion thereof, and the wafer is subjected to a film expansion process to form individual semiconductor chips.
Another aspect of the present invention provides a wafer structure for improving the dicing performance of a wafer, including: the wafer is provided with a plurality of semiconductor chips, the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel; gaps along the cutting path direction are formed in the metal structure or the metal bonding pad, so that the difficulty of subsequent cutting is reduced.
Preferably, the depth of the gap is equal to the thickness of the metal structure or the metal pad.
Preferably, the gap depth is less than the thickness of the metal structure or the metal pad.
Preferably, the position, size and shape of the gap ensure the effectiveness of wafer alignment, electrical testing or film thickness measurement.
Preferably, for the metal pad for film thickness measurement, the measurement performance is guaranteed to be higher than or equal to 0.9 in confidence.
Preferably, when the ratio of the gap width to the metal pad width is greater than or equal to a threshold, the pad gap may be disposed in a non-middle region of the metal pad.
Preferably, the direction of the gap is consistent with the direction of the cutting path.
The invention provides a method for improving the cutting performance of a wafer and a wafer structure.A wafer provided with a plurality of semiconductor chips is provided, the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel; and removing part of metal or all metal of the metal structure or the metal bonding pad along the cutting channel direction to form a gap so as to reduce the process difficulty in the cutting process, improve the cutting quality and improve the product performance of the semiconductor chip.
Drawings
Other features, objects and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments thereof, which proceeds with reference to the accompanying drawings.
FIG. 1 is a schematic diagram of a semiconductor chip integrated on a wafer;
FIG. 2 is an enlarged view of a portion of region P of FIG. 1 in accordance with a preferred embodiment of the prior art;
FIG. 3 is an enlarged view of a portion of region P of FIG. 1 in accordance with another preferred embodiment of the prior art;
FIG. 4 is an enlarged partial view of region P of FIG. 1 in accordance with a preferred embodiment of the present invention;
FIG. 5 is a partial cross-sectional view taken along line B-B of FIG. 4 in accordance with a preferred embodiment of the present invention;
FIG. 6 is a partial cross-sectional view taken along line B-B of FIG. 4 in accordance with another preferred embodiment of the present invention;
FIG. 7 is a partial enlarged view of region P of FIG. 1 in accordance with another preferred embodiment of the present invention;
FIG. 8 is a partial enlarged view of region P of FIG. 1 in accordance with another preferred embodiment of the present invention;
FIG. 9 is a partial enlarged view of region P of FIG. 1 in accordance with another preferred embodiment of the present invention;
fig. 10 is a partially enlarged view of a region P of fig. 1 in accordance with still another preferred embodiment of the present invention.
In the drawings, like or similar reference numbers indicate like or similar devices (modules) or steps throughout the different views.
Detailed Description
In order to solve the problems in the prior art, the invention provides a method for improving the wafer cutting performance and a wafer structure, wherein a wafer provided with a plurality of semiconductor chips is provided, the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical test and a metal bonding pad for film thickness measurement is arranged on each cutting channel; and removing part of metal or all metal of the metal structure or the metal bonding pad along the cutting channel direction to form a gap so as to reduce the process difficulty in the cutting process, improve the cutting quality and improve the product performance of the semiconductor chip.
In the following detailed description of the preferred embodiments, reference is made to the accompanying drawings which form a part hereof. The accompanying drawings illustrate, by way of example, specific embodiments in which the invention may be practiced. The illustrated embodiments are not intended to be exhaustive of all embodiments according to the invention. It is to be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the present invention. The following detailed description, therefore, is not to be taken in a limiting sense, and the scope of the present invention is defined by the appended claims.
The present invention will be described in detail with reference to specific examples.
The invention provides a method for improving the cutting performance of a wafer, which comprises the following steps: providing a wafer provided with a plurality of semiconductor chips, wherein the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel; and removing part of metal or all of metal of the metal structure or the metal bonding pad along the cutting path direction to form a gap so as to reduce the difficulty of subsequent cutting.
As shown in fig. 4, the adjacent semiconductor chips 121 and 122 have a scribe line a-a, and a metal pad 124 for electrical test or film thickness measurement is provided on the scribe line a-a as an example, and a part of metal or all metal of the metal pad 124 is removed along the scribe line a-a direction to form a gap 125, thereby reducing difficulty of subsequent dicing, improving dicing quality, and improving product performance of the semiconductor chip.
FIG. 5 is a partial cross-sectional view taken along line B-B of FIG. 4, wherein the metal is completely etched along the depth of the gap 125, i.e., the depth of the gap Ds is equal to the thickness Dp of the metal pad 124, in accordance with a preferred embodiment of the present invention; fig. 6 is a partial cross-sectional view taken along line B-B of fig. 4, wherein the metal is partially etched along the depth of the gap 125, i.e., the depth Ds of the gap is less than the thickness Dp of the metal pad 124, in accordance with another preferred embodiment of the present invention.
Furthermore, in the preferred embodiment shown in fig. 4, all the metal of the metal pad 124 is removed along the cutting path a-a direction, that is, the gap 125 extends through the entire metal pad 124; in another preferred embodiment as shown in fig. 7, a portion of the metal pad 124 is removed along the cutting track a-a direction, and the portion of the metal pad 124 where the metal is removed is continuous; in another preferred embodiment as shown in fig. 8, a portion of the metal pad 124 is removed along the cutting path a-a direction, and the portion of the metal pad 124 where the metal is removed is discontinuous.
Those skilled in the art will appreciate that the above-described alternative embodiments can effectively reduce the difficulty of subsequent dicing, so that the position, size and shape of the gap 125 can be designed in advance to ensure the effectiveness of electrical testing or film thickness measurement. For the metal pad 124 for measuring the film thickness, light spots are provided to irradiate the wafer, the light spots respectively correspond to the metal pad 124 for wafer measurement, and the position, size and shape of the gap 125 can be designed to ensure that the confidence of the measurement performance is greater than or equal to 0.9.
As shown in fig. 9, when the ratio of the gap width Ws to the metal pad width Wp is greater than or equal to a threshold, the influence of the gap 125 on the film thickness measurement may tend to be significant, and at this time, the pad gap 125 may be disposed in a non-middle region of the metal pad 124, so as to reduce the influence of the light spot irradiated on the gap 125 on the film thickness measurement performance as much as possible.
Fig. 10 shows a preferred embodiment of a metal structure 123 for alignment on a scribe line a-a, wherein a part of metal or all of metal of the metal structure 123 is removed along the scribe line a-a to form a gap 125, thereby reducing the difficulty of subsequent dicing. It can be understood by those skilled in the art that the position, size and shape of the gap 125 can also be designed in advance to ensure the effectiveness of wafer alignment, which is similar to the gap arrangement in the metal pad 124 described above and will not be described herein again.
By adopting the method for improving the wafer cutting performance, in the wafer cutting process, for the case that the gap 125 is arranged in the middle area or the non-middle area of the metal structure 123 or the metal pad 124, the wafer can be cut along the middle area of the metal structure 123 or the metal pad 124 by adopting the laser invisible cutting process, and the wafer can also be cut along the middle area of the metal structure 123 or the metal pad 124 by adopting the mechanical cutting mode. Preferably, the wafer is cut through its entire thickness or a portion thereof, and the wafer is subjected to a film expansion process to form individual semiconductor chips.
Another aspect of the present invention provides a wafer structure for improving the dicing performance of a wafer, including: a plurality of semiconductor chips 121 and 122 are arranged on the wafer, the adjacent semiconductor chips 121 and 122 are provided with a cutting path A-A, and at least one of a metal structure 123 for alignment, a metal pad 124 for electrical test and a metal pad 124 for film thickness measurement is arranged on the cutting path A-A; the metal structure 123 or the metal pad 124 is provided with a gap 125 along the cutting path a-a direction, so as to reduce the difficulty of subsequent cutting, improve the cutting quality, and improve the product performance of the semiconductor chip.
According to a preferred embodiment of the present invention, the gap depth Ds is equal to the thickness Dp of the metal structure 123 or the metal pad 124. According to another preferred embodiment of the present invention, the gap depth Ds is smaller than the thickness Dp of the metal structure 123 or the metal pad 124.
Preferably, the direction of the gap 125 is the same as the direction of the scribe line a-a, and the position, size and shape of the gap 125 ensure the effectiveness of wafer alignment, electrical test or film thickness measurement.
Preferably, for the metal pad 124 for film thickness measurement, the measurement performance is guaranteed to have a confidence greater than or equal to 0.9. When the ratio of the gap width Ws to the metal pad width Wp is greater than or equal to a threshold, the pad gap 125 may be disposed in a non-middle region of the metal pad 124.
In summary, in the method for improving the wafer dicing performance and the wafer structure of the present invention, a wafer provided with a plurality of semiconductor chips is provided, and the adjacent semiconductor chips have dicing streets, and at least one of a metal structure for alignment, a metal pad for electrical property test, and a metal pad for film thickness measurement is provided on the dicing streets; and removing part of metal or all metal of the metal structure or the metal bonding pad along the cutting channel direction to form a gap so as to reduce the process difficulty in the cutting process, improve the cutting quality and improve the product performance of the semiconductor chip.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential attributes thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive. Furthermore, it will be obvious that the word "comprising" does not exclude other elements or steps, and the word "a" or "an" does not exclude a plurality. Several elements recited in the apparatus claims may also be implemented by one element. The terms first, second, etc. are used to denote names, but not any particular order.

Claims (18)

1. A method for improving the cutting performance of a wafer is characterized by comprising the following steps:
providing a wafer provided with a plurality of semiconductor chips, wherein the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel;
and removing part of metal or all of metal of the metal structure or the metal bonding pad along the cutting path direction to form a gap so as to reduce the difficulty of subsequent cutting.
2. The method of improving dicing performance of a wafer as claimed in claim 1, wherein the metal is completely etched in a depth direction of the gap.
3. The method of improving dicing performance of a wafer as claimed in claim 1, wherein the metal is partially etched in a depth direction of the gap.
4. The method as claimed in claim 1, wherein the position, size and shape of the gap are designed in advance to ensure the effectiveness of wafer alignment, electrical test or film thickness measurement.
5. The method of claim 4, wherein for the metal pad for film thickness measurement, the measurement performance is guaranteed with a confidence level of 0.9 or higher.
6. The method according to claim 5, wherein light spots are provided to irradiate the wafer, and the light spots respectively correspond to the metal pads for wafer measurement.
7. The method for improving the cutting performance of the wafer as claimed in claim 5, wherein when the ratio of the gap width to the metal pad width is greater than or equal to a threshold value, the pad gap is disposed in a non-middle region of the metal pad.
8. The method for improving the wafer cutting performance as claimed in claim 1, wherein the gap is realized by layout design, and the direction of the gap is consistent with the direction of the cutting street.
9. The method for improving the cutting performance of the wafer according to claim 1, wherein the wafer is cut along the middle area of the metal structure or the metal bonding pad by adopting a laser invisible cutting process.
10. The method for improving the cutting performance of the wafer as claimed in claim 1, wherein the wafer is cut along the middle area of the metal structure or the metal pad by using a mechanical cutting method.
11. The method for improving the cutting performance of the wafer as claimed in claim 1, characterized in that all or part of the thickness of the wafer is cut, and the wafer is subjected to the expanding process to form individual semiconductor chips.
12. A wafer structure for improving the cutting performance of a wafer is characterized by comprising:
the wafer is provided with a plurality of semiconductor chips, the adjacent semiconductor chips are provided with cutting channels, and at least one of a metal structure for alignment, a metal bonding pad for electrical property test and a metal bonding pad for film thickness measurement is arranged on each cutting channel;
gaps along the cutting path direction are formed in the metal structure or the metal bonding pad, so that the difficulty of subsequent cutting is reduced.
13. The wafer structure of claim 12 wherein the depth of the gap is equal to the thickness of the metal structure or the metal pad.
14. The wafer structure of claim 12 wherein the depth of the gap is less than the thickness of the metal structure or the metal pad.
15. The wafer structure of claim 12 wherein the position, size, and shape of the gap ensure wafer alignment, electrical testing, or film thickness measurement effectiveness.
16. The wafer structure of claim 15 wherein for the metal pads for film thickness measurement, the measurement performance is guaranteed with a confidence level of 0.9 or higher.
17. The wafer structure of claim 16, wherein the pad gap is disposed in a non-middle region of the metal pad when a ratio of the gap width to the metal pad width is greater than or equal to a threshold value.
18. The wafer structure for improving the cutting performance of the wafer as claimed in claim 12, wherein the direction of the gap is consistent with the direction of the cutting path.
CN201911338582.3A 2019-12-23 2019-12-23 Method for improving wafer cutting performance and wafer structure Pending CN113097135A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201911338582.3A CN113097135A (en) 2019-12-23 2019-12-23 Method for improving wafer cutting performance and wafer structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201911338582.3A CN113097135A (en) 2019-12-23 2019-12-23 Method for improving wafer cutting performance and wafer structure

Publications (1)

Publication Number Publication Date
CN113097135A true CN113097135A (en) 2021-07-09

Family

ID=76662869

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201911338582.3A Pending CN113097135A (en) 2019-12-23 2019-12-23 Method for improving wafer cutting performance and wafer structure

Country Status (1)

Country Link
CN (1) CN113097135A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540041A (en) * 2021-09-13 2021-10-22 广州粤芯半导体技术有限公司 Alignment mark and wafer slicing method
CN113953689A (en) * 2021-12-16 2022-01-21 湖北三维半导体集成创新中心有限责任公司 Wafer cutting method

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN113540041A (en) * 2021-09-13 2021-10-22 广州粤芯半导体技术有限公司 Alignment mark and wafer slicing method
CN113540041B (en) * 2021-09-13 2022-02-15 广州粤芯半导体技术有限公司 Alignment mark and wafer slicing method
CN113953689A (en) * 2021-12-16 2022-01-21 湖北三维半导体集成创新中心有限责任公司 Wafer cutting method

Similar Documents

Publication Publication Date Title
US7759223B2 (en) Semiconductor wafer and manufacturing process for semiconductor device
JP4931502B2 (en) Surface inspection method and inspection apparatus
US7481579B2 (en) Overlay metrology using X-rays
CN113097135A (en) Method for improving wafer cutting performance and wafer structure
US5023188A (en) Method of determining the depth of trenches formed in a semiconductor wafer
JPH07239212A (en) Position detector
US6667253B2 (en) Alignment mark and exposure alignment system and method using the same
JP4359689B2 (en) Inspection apparatus and inspection method, pattern substrate manufacturing method
CN211605132U (en) Wafer structure for improving wafer cutting performance
JP2006105951A (en) Defect inspection method
US20240085804A1 (en) Frequency-picked methodology for diffraction-based overlay measurement
JP2007107960A (en) Flaw inspection device
JPH0663982B2 (en) Foreign object detection method and apparatus
US11852981B2 (en) Frequency-picked methodology for diffraction based overlay measurement
JPH0560253B2 (en)
CN109509738B (en) Method for manufacturing alignment mark on wafer and structure of alignment mark
JP2011180145A (en) Flaw inspection device
JP2898669B2 (en) Defect inspection equipment
RU2797785C1 (en) Semiconductor structure
JPH01196822A (en) Semiconductor integrated circuit device
KR100711923B1 (en) Method for detecting void in semiconductor device
JPH06229939A (en) Inspection apparatus for foreign matter
JP2585607B2 (en) Semiconductor wafer
JP2797195B2 (en) Semiconductor wafer alignment method
JPS63247603A (en) Pattern detector

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination