CN113095017A - General simulator for memory element - Google Patents

General simulator for memory element Download PDF

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CN113095017A
CN113095017A CN202110210392.4A CN202110210392A CN113095017A CN 113095017 A CN113095017 A CN 113095017A CN 202110210392 A CN202110210392 A CN 202110210392A CN 113095017 A CN113095017 A CN 113095017A
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current feedback
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feedback operational
memory
current
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CN113095017B (en
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郑辞晏
庄楚源
李亚
练明坚
颜坤哲
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Guangdong Polytechnic Normal University
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Abstract

The invention provides a memory device general simulator, a current feedback operational amplifier U1Respectively connected with a current feedback operational amplifier U3And as input A, a current feedback operational amplifier U2First transformation memory interface T as series resistance or inductance1Positive and negative terminals of the current feedback operational amplifier U2Respectively connected with a current feedback operational amplifier U4And as input B, a current feedback operational amplifier U2And multiplier U5Connected, multiplier U5Both ends are grounded after being connected together, and a multiplier U5And current feedback operational amplifier U3Connecting, current feedback operational amplifier U3Open-circuit, current-fed operational amplifier U3Current feedback operational amplifier U4Second transformation memory interface T as series-connected resistor or capacitor2Positive and negative terminals of the current feedback operational amplifier U4Are respectively open at both endsAnd is grounded. The memristor, the memory container and the memory sensor which are conveniently simulated are put into industrial production.

Description

General simulator for memory element
Technical Field
The invention relates to the technical field of memory element construction, in particular to a general simulator for a memory element.
Background
In 1971, the Chua begonia team studied the current i, voltage V, charge q and magnetic flux
Figure BDA0002952048300000011
The relationship between them to predict a fourth basic circuit element, called memristor, that exists in addition to the resistance, capacitance, inductance, representing the charge q and the magnetic flux
Figure BDA0002952048300000012
The mathematical relationship of (a).
In 2008, Hewlett packard laboratories successfully fabricated nanoscale solid-state devices with memristor characteristics. From this, the historical position of the memristor as the fourth basic circuit element was determined. Due to the unique memory characteristic and the nanostructure of the memristor, the memristor has wide application prospects in the fields of nonvolatile storage, artificial intelligence (including brain-like operation and neural networks), chaotic circuits, logic chips and the like. In 2009, the zeita begonia team further proposed the concept of a memristor and a memcapacitor, and the characteristics of the memcapacitor and the meminductor both show the memory function as the same as the memristor. Thus, memristors, memcapacitors, and memristors are also collectively referred to as memory elements. However, compared with a memristor, the memristor and the memristor exist as a novel generalized energy storage element. Unlike memristors, in some low-power integrated circuits, the memcapacitor and the meminductor do not need to consume energy when operating. Therefore, it is reasonable to believe that memcapacitors and meminductors can have more applications in the field of electronic circuits.
However, due to development costs and the technical difficulties in fabricating nanoscale devices, commercial-scale memory elements cannot be overcome in a short time. Therefore, in order to explore the subsequent application of the three memory elements, it is necessary to research the simulation model and the equivalent circuit simulator.
And in the patent numbers: CN201610580825, patent name: a method for simulating the use of a memristor, a memcapacitor and a meminductor respectively by using five current feedback operational amplifiers and a field effect transistor is disclosed in a patent document (the following patent document A), because the patent document A can realize the simulation of the memory characteristics of the memristor, the memcapacitor and the meminductor by depending on the field effect transistor working in a linear region, the memristor, the memcapacitor and the meminductor simulated by the method of the patent document A can only be used in a circuit with the frequency of 0.8kHZ, but the frequency of the existing circuit is far beyond 0.8kHZ, so that the general memory device simulator obtained in the patent document A can not meet the actual circuit working requirements and can not be really used in a conventional circuit, the general memory device simulator in the patent document A can not be put into the conventional production, and the simulated memristor the memcapacitor and the meminductor can not be really put into the conventional production, The memory container and the memory inductor are put into industrial production.
Disclosure of Invention
The invention aims to provide a universal simulator for a memory element, which is used for simulating a memristor, a memristor and a memristor, can flexibly use the simulated memristor, memristor and memristor in a circuit with the frequency of 100kHZ magnitude, and is convenient for the simulated memristor, memristor and memristor to be put into industrial production.
Therefore, the memory element universal simulator comprises a controller, four current feedback operational amplification chips for amplifying signals at high frequency, a multiplier, a power supply, an integrator, a plurality of resistors, a capacitor and an inductor, wherein the four current feedback operational amplifiers are respectively marked as U1、U2、U3、U4Any one of the current feedback operational amplification chips has an x terminal, a y terminal, a p terminal and a z terminal, and the current feedback operational amplification chip U1The y end of the current transformer is divided into two branches, wherein one branch is connected to a current feedback operational amplification chip U3And the other branch is taken as an input end A, and the current feedback operation is used for amplifying the chip U1The x terminal of the first transformation memory interface T1The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation2As a first transformationMemory interface T1Negative terminal of, the first transformation memory interface T1The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or an inductor in series, and the current feedback operational amplifier chip U2The y end of the current transformer is connected with a current feedback operational amplification chip U, and two branches are divided4And the other branch is taken as an input end B, and a current feedback operation amplification chip U1The z end is grounded through an integrator, and a current feedback operational amplification chip U1P terminal of and multiplier U5X of1End connection, current feedback operational amplification chip U2The z end is grounded through a resistor, and a current feedback operational amplification chip U2P terminal of and multiplier U5Y of (A) to (B)1End-connected, multiplier U5X of2The end is grounded through a power supply, and a multiplier U5Y of (A) to (B)2The end and the z end are grounded after being connected together, and a multiplier U5W terminal and current feedback operational amplification chip U3The y end of the current feedback operational amplifier chip U is connected with3P end of the p-type amplifier is open-circuited, and the current feedback operation is used for amplifying the chip U3The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation4The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2Negative terminal of, a second transformation memory interface T2The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or a capacitor in series, and the current feedback operational amplifier chip U4P-end open circuit, current feedback operational amplification chip U4The y end of the controller is grounded, the controller is connected with the input end A and the input end B, and the working frequency ranges from 0kHZ to 100 kHZ.
Further, the integrator is a capacitor.
Further, the current flowing from the input terminal a is iABCurrent feedback operational amplifier chip U3Has a current of i at the z-terminal5Flow direction to the first conversion memory interface T1Has a current of i as a negative terminal1From current feedback operational amplification chip U4The current flowing out of the z terminal is i6From current feedback operational amplification chip U1The current flowing out of the z terminal is i2From current feedback operational amplification chip U2The current flowing out of the z terminal is i3From current feedback operational amplification chip U3The x terminal of (a) flows a current of i4。
Further, if the first transformation memory interface T1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The other resistor is connected in series between the input end A and the input end B, and then the input end A and the input end B are connected with an external circuit to simulate a memristor.
Further, if the first transformation memory interface T1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memcapacitor.
Further, if the first transformation memory interface T1Positive terminal and first transformation memory interface T1An inductance is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memory inductor.
Further, the V1x＝VA，V2x＝VB(ii) a According to an algorithm
Figure BDA0002952048300000031
To obtain the current flowing through the first transformation memory interface T1Current i between positive and negative terminals1；
According to an algorithm
Figure BDA0002952048300000032
To obtain current feedback operational amplification chip U1The voltage of the middle p-terminal is,
according to an algorithm
Figure BDA0002952048300000033
To obtain current feedback operational amplification chip U2The voltage of the middle p-terminal is,
according to an algorithm
Figure BDA0002952048300000034
To find the multiplier U5Output voltage V ofw
Calculating current feedback operational amplification chip U3Current feedback operational amplification chip U4The voltages respectively correspond to: v3x＝V3y＝Vw，V4x＝V4y＝0
Calculating current feedback operational amplification chip U3Current feedback operational amplification chip U4The respective currents are: i.e. i4＝-iAB，
Figure BDA0002952048300000035
According to an algorithm
Figure BDA0002952048300000036
Figure BDA0002952048300000037
To obtain the memristor memory conductance value
Figure BDA0002952048300000038
Wherein the content of the first and second substances,
Figure BDA0002952048300000039
is the voltage V between the input terminal A and the input terminal BABIntegral value over time, memristor's memristive memristor's value
Figure BDA00029520483000000310
Is about
Figure BDA00029520483000000311
Function of alpha1Representing the rate of change of the memory conductance, beta1Represents the initial value of the memory conductance value, and alpha1、β1Respectively as follows:
Figure BDA00029520483000000312
further, according to an algorithm
Figure BDA00029520483000000324
To obtain the capacitance C2Voltage across
Figure BDA00029520483000000313
Through a capacitor C2Electric charge of
Figure BDA00029520483000000314
Comprises the following steps:
Figure BDA00029520483000000323
Figure BDA00029520483000000317
Figure BDA00029520483000000318
wherein the content of the first and second substances,
Figure BDA00029520483000000319
is flowing through a capacitor C2Current i of4Integral over time, CmFor memory capacity of a memory vessel, alpha2Representing a memory capacity value CmRate of change of beta2Representing a memory capacity value CmIs a from an initial value of2、β2Respectively as follows:
Figure BDA00029520483000000320
further, the current flowing through the inductor is calculated according to an algorithm as:
Figure BDA00029520483000000321
according to an algorithm
Figure BDA00029520483000000322
To obtain the capacitance C1A charge q on, a calculating multiplier U5Output voltage V ofwComprises the following steps:
Figure BDA0002952048300000041
calculating current feedback operational amplification chip U2Z terminal output voltage V2z：
Figure BDA0002952048300000042
Where ρ isABIs a magnetic flux
Figure BDA0002952048300000043
The integral of the time is taken into account,
Figure BDA0002952048300000044
voltage V for memory sensorABIntegral over time, Lm -1(ρAB) Is the reciprocal of the memristive value of the memristor, alpha3Represents Lm -1Rate of change of beta3Represents Lm -1Is a from an initial value of3、β3Respectively as follows:
Figure BDA0002952048300000045
has the advantages that:
the invention provides a memory element universal simulator, which comprises a controller, four current feedback operational amplifiers, a multiplier, a power supply, an integrator, a plurality of resistors, capacitors and inductors which are connected in series to form an input end A and an input end B which are used as two ports for connecting the memory element universal simulator with an external circuit, wherein a first transformation memory interface T is arranged in the memory element universal simulator1And a second transformation memory interface T2By using the first transformation memory interface T1Medium series resistance or inductance, in the second transformation memory interface T2The middle series resistor or capacitor is used for simulating a memristor, a memristor capacitor and a memristor inductor, and the simulated memristor, the simulated memristor capacitor and the simulated memristor inductor can be flexibly used in a circuit with the frequency of 100kHZ magnitude, so that the simulated memristor, the simulated memristor capacitor and the simulated memristor inductor can be put into industrial production conveniently.
The foregoing description is only an overview of the technical solutions of the present invention, and the embodiments of the present invention are described below in order to make the technical means of the present invention more clearly understood and to make the above and other objects, features, and advantages of the present invention more clearly understandable.
Drawings
Various other advantages and benefits will become apparent to those of ordinary skill in the art upon reading the following detailed description of the preferred embodiments. The drawings are only for purposes of illustrating the preferred embodiments and are not to be construed as limiting the invention. Also, like reference numerals are used to refer to like parts throughout the drawings. In the drawings:
FIG. 1 is a schematic diagram of a memory device simulator according to the present invention;
FIG. 2 is a schematic diagram of a simulated memristor of the present disclosure;
FIG. 3 is a schematic diagram of a simulated memcapacitor according to the present invention;
FIG. 4 is a schematic diagram of a simulated memory sensor according to the present invention;
FIG. 5 is a schematic diagram of the operating frequency behavior of the simulated memristor of the present disclosure;
FIG. 6 is a schematic diagram of the operating frequency of a simulated memcapacitor of the present invention;
FIG. 7 is a schematic diagram of the operating frequency behavior of an analog memristor of the present disclosure;
FIG. 8 is a schematic structural diagram of an electronic device according to the present invention;
fig. 9 is a schematic structural diagram of a computer-readable storage medium according to the present invention.
Description of reference numerals: 21-a processor; 22-a memory; 23-storage space; 24-program code; 31-program code.
Detailed Description
The invention is further described with reference to the following examples.
Referring to fig. 1, the memory device universal simulator of the present embodiment includes four current feedback operational amplifiers U respectively electrically connected to the controller1Current feedback operational amplifier U2Current feedback operational amplifier U3And current feedback operational amplifier U4A current feedback type current feedback operational amplifier AD844 and a multiplier U5Resistance R1A capacitor C functioning as an integrator1A DC voltage source Vs, a current feedback operational amplifier U1And a branch connected to a current feedback operational amplifier U3The other branch is used as the input end A of the memory element general simulator, and the voltage of the input end A is VAThe current flowing from the input terminal A to the node of the two branches is iABIn-flow current feedback operational amplifier U3Has a current of i at the z-terminal5Feeding back the operational amplifier U with current1The x terminal of the first transformation memory interface T1With a current feedback operational amplifier U2The x terminal of the first transformation memory interface T1Negative terminal of, the first transformation memory interface T1Positive terminal and first transformation memory interface T1The negative terminal of the first conversion memory interface T can be connected with a resistor or an inductor in series1Positive end of the current feedback operational amplifier U2The x terminal of (b) has a current of i1Current feedback operational amplifier U2And a branch connected to a current feedback operational amplifier U4And the other branch is used as the input end B of the memory element general simulator, and the operational amplifier U is fed back from the current4The current flowing out of the z terminal is i6Current feedback operational amplifier U1Z terminal of (C)1Back grounded, slave current feedback operational amplifier U1The current flowing out of the z terminal is i2Current feedback operational amplifierU1P terminal of and multiplier U5X of1End-connected, current-fed operational amplifier U2Z terminal series resistance R1Back grounded, slave current feedback operational amplifier U2The current flowing out of the z terminal is i3Current feedback operational amplifier U2P terminal of and multiplier U5Y of (A) to (B)1End-connected, multiplier U5X of1End-series direct current source VsRear grounded, multiplier U5Y of (A) to (B)2Terminals are connected to the z terminal and grounded, and a multiplier U5W terminal and current feedback operational amplifier U3Is connected to a slave current feedback operational amplifier U3The y terminal of (a) flows a current of i4Current feedback operational amplifier U3The p end of the operational amplifier U is open-circuited and fed back by current3The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2With a current feedback operational amplifier U4The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2Negative terminal of, a second transformation memory interface T2Positive terminal and second transformation memory interface T2The negative end of the operational amplifier can be connected with a resistor or a capacitor in series, and the current is fed back to the operational amplifier U4P-terminal open-circuit, current feedback operational amplifier U4The y-terminal of (1) is grounded. Current feedback operational amplifier U1The x, y, p and z terminals of the voltage source respectively correspond to the voltage V1x、V1y、V1p、V1zCurrent feedback operational amplifier U2The x, y, p and z terminals of the voltage source respectively correspond to the voltage V2x、V2y、V2p、V2zCurrent feedback operational amplifier U3The x, y, p and z terminals of the voltage source respectively correspond to the voltage V3x、V3y、V3p、V3zCurrent feedback operational amplifier U4The x, y, p and z terminals of the voltage source respectively correspond to the voltage V4x、V4y、V4p、V4z。
The input end A and the input end B are used as external ports of the universal interface circuit, so that the memory element universal simulator can be connected and communicated with external equipment. By using the first transformation memory interface T1Positive and negative end, second conversion memory interface T2The positive and negative ends are respectively connected with a resistor or a capacitor in seriesOr the inductor is used for changing the state variable relation in the memory element universal simulator, so that the memory element universal simulator simulates the characteristics of a memristor, a memory capacitor and a memory sensor, and is flexibly connected with an external circuit through the input end A and the input end B for use, and therefore the effect of simulating the use of the memristor, the memory capacitor and the memory sensor by using hardware is achieved.
The current feedback operational amplifier AD844 is a current feedback type current feedback operational amplifier, plays the role of a current transmitter and a voltage follower in a memory element universal simulator, and based on the characteristics of the AD844 current feedback operational amplifier, an x end is an inverted input end, a y end is a same-direction input end, a p end and a z end are output ends, and V isp＝Vz，Vy＝Vx，ip＝iz，iy＝ixSince the z terminal has a weak ability to drive the load, the p terminal is usually connected to the external load. Multiplier U5For the two-input multiplier AD633 chip, its input terminal x is recorded1、x2、y1、y2And z have a voltage (or potential) value of Vx1、Vx2、Vy1、Vy2And VzThe voltage (or potential) value of the output end w is marked as VwBased on AD633 multiplier U5Of which is
Figure BDA0002952048300000061
Capacitor C1The memory device universal simulator of the present embodiment functions as an integrator, and equivalently, integrates the input voltage.
The memory element comprises a memristor, a memory container and a memory inductor which respectively correspond to different constitutive relations, and the constitutive relation of the memristor is
Figure BDA0002952048300000062
The constitutive relation of the nonlinear relation and the memcapacitor is
Figure BDA0002952048300000063
The nonlinear relation and the constitutive relation of the memory sensor are q-rho nonlinear relations. Wherein q represents an electric chargeThe amount of the compound (A) is,
Figure BDA0002952048300000064
is the magnetic flux, i.e. the integral of voltage over time, σ is the integral of q over time, ρ is
Figure BDA0002952048300000065
Integration over time.
The following embodiments all propose corresponding memory element simulators based on the constitutive relation of memristors, memristors and memristors, and memristors. Namely, only the first transformation memory interface T is changed under the condition of ensuring that the circuit topology structure of the simulator is not changed1Positive and negative end, second conversion memory interface T2The positive end and the negative end of the memory cell are respectively connected with a resistor, a capacitor or an inductor in series, so that the simulator can be respectively converted into a memristor, a memory capacitor and a memory inductor. For example, memristors, converting state variables inside a memory element simulator into magnetic flux by changing the properties of an access element
Figure BDA0002952048300000066
And a charge q, and the relationship between them can be characterized by a quadratic non-linear function. For the memcapacitor and the meminductor, the constitutive relation of the memcapacitor and the meminductor can be characterized through a quadratic nonlinear function. Thereby, the relationship between the internal state variables of the memory simulator is characterized in the form of a quadratic non-linear function.
Example 1
For memristors, internal state variables of the simulator
Figure BDA0002952048300000067
Relationship (D) and memory conductance value Wm(the reciprocal of memristance, like conductance) can be defined as:
Figure BDA0002952048300000068
Figure BDA0002952048300000069
wherein alpha is1Represents WmSlope of change of beta1Represents WmIs started.
Referring to fig. 2, under the condition that an excitation voltage is applied between a and B, the matched setting of various parameters in the memory element general simulator of the embodiment is completed by the following method to simulate the use of a memristor:
will resistance R2Connected in series to the first transformation memory interface T1Between the positive and negative terminals, a resistance R3Connected in series to the second transformation memory interface T2Between the positive and negative terminals, the voltage following characteristic of the current feedback operational amplifier AD844 can be obtained:
V1x＝VA，V2x＝VB；
obtaining the flow through the first transformation memory interface T1Current i between positive and negative terminals1；
In particular, the resistance R2The voltage at both ends is equal to the external input voltage VABThe current i is obtained according to the following algorithm1
Figure BDA0002952048300000071
In the current feedback operational amplifier U1、U2The output current at each z-terminal is as follows:
i2＝i1
Figure BDA0002952048300000072
capacitor C1Plays an integral role in the general interface circuit, so VC1Can be expressed as:
Figure BDA0002952048300000073
Figure BDA0002952048300000074
is the voltage V between the input terminal A and the input terminal BABThe integral value of time is calculated to obtain:
Figure BDA0002952048300000075
Figure BDA0002952048300000076
available multiplier U5Output voltage V ofwComprises the following steps:
Figure BDA0002952048300000077
current feedback operational amplifier U3Current feedback operational amplifier U4The corresponding voltages and currents, respectively, are:
V3x＝V3y＝Vw
V4x＝V4y＝0
i4＝-iAB
therefore, the method can obtain:
Figure BDA0002952048300000078
Figure BDA0002952048300000079
Figure BDA00029520483000000710
wherein the memristor has a memristive memristor
Figure BDA00029520483000000711
Is about
Figure BDA00029520483000000712
Function of alpha1Representing the memory conductance value
Figure BDA00029520483000000713
Rate of change of beta1Representing the memory conductance value
Figure BDA00029520483000000714
Is a from an initial value of1、β1Respectively as follows:
Figure BDA0002952048300000081
the parameters obtained by the above calculation are put into the memory element general simulator of this embodiment, and the input terminal a and the input terminal B are respectively connected to an external circuit to simulate the use of the memristor.
In order to verify the correctness of the memristor imitated by the memory element general simulator of the embodiment, the applicant uses the formula V of the excitation voltageABObtaining (2 pi ft) or (ω t) A sin
Figure BDA0002952048300000082
Wherein the content of the first and second substances,
Figure BDA0002952048300000083
is a VABThe integral value of time is compared to obtain the magnetic flux of the memristor
Figure BDA0002952048300000084
Amplitude of and
Figure BDA0002952048300000085
in a proportional relationship.
And according to the formula
Figure BDA0002952048300000086
Transform derived algorithm
Figure BDA0002952048300000087
And according to an algorithm
Figure BDA0002952048300000088
At VAB-iABDrawing hysteresis curve in plane, comparing to obtain when exciting voltage VABWhile the amplitude of the magnetic flux is kept constant, the magnetic flux increases with the excitation frequency
Figure BDA00029520483000000811
Is reduced in amplitude, current iABIs also reduced in amplitude, at VAB-iABThe hysteresis loop curve is drawn in the plane to contract inwards.
According to the theoretical analysis, the applicant also adopts Pspice software to carry out simulation experiments, and builds the memory element universal simulator of the embodiment in the Pspice software and puts the following parameters into the simulator: sinusoidal excitation voltage VABIs a VABSin (2 pi ft) (V), capacitance C1＝0.1nF、R1＝45kΩ、R2＝16kΩ、R3＝55kΩ、Vs-2.5V, in each of the current feedback type current feedback operational amplifier and multiplier U5The power supply ends are respectively connected with a direct current power supply voltage with the amplitude of +/-15V.
For a memory device general simulator, current iABThe current flowing between the input end A and the input end B can be directly measured by a meter pen in Pspice software simulation; voltage VABCan also be directly measured.
When the excitation frequencies are 80kHz, 100kHz and 130kHz, respectively, the voltage V between the input terminal A and the input terminal BABAnd current iABThe lissajous phase trace of (a) is shown in fig. 5.
It can be seen that the voltage VABAnd current iABWhen the frequency of the Lissajous phase track is respectively 80kHz, 100kHz and 130kHz, the memory characteristic of a memristor can be achieved, namely the memory resistance reciprocal wmAt VAB-iABKeeping a magnetic hysteresis loop in a shape like a slant '8' in a plane, keeping the amplitude of the voltage unchanged along with the increase of the frequency of the excitation voltage, and keeping the current iABReduction of hysteresisAnd (4) annular inward contraction.
In summary, the simulation experiment result is consistent with the theoretical analysis, so the memory device general simulator of the present embodiment can simulate the memory characteristics of the memristor.
Example 2
For memcapacitor, internal state variables of simulator
Figure BDA00029520483000000812
Relationship and memory capacity value CmCan be defined as:
Figure BDA0002952048300000089
Figure BDA00029520483000000810
wherein alpha is2Represents CmSlope of change of beta2Represents CmIs started.
Referring to fig. 3, in the case of applying an excitation voltage between an input terminal a and an input terminal B, matching setting of various parameters in the memory element general simulator of the present embodiment is completed by the following method to simulate the use of a memcapacitor:
will resistance R2Connected in series to the first transformation memory interface T1Between the positive and negative terminals, a resistance C2Connected in series to the second transformation memory interface T2Between the positive end and the negative end, the capacitor C can be obtained by the voltage following characteristic of the current feedback operational amplifier AD8442Voltage across
Figure BDA00029520483000000911
Comprises the following steps:
Figure BDA00029520483000000912
current feedback operational amplifier U3Is equal to its z-terminal input current:
i4＝-iAB
thus passing through the capacitor C2Electric charge of
Figure BDA00029520483000000913
Comprises the following steps:
Figure BDA0002952048300000091
wherein the content of the first and second substances,
Figure BDA00029520483000000914
is flowing through a capacitor C2Current i of4Integration over time, i.e.
Figure BDA0002952048300000092
Figure BDA0002952048300000093
Figure BDA0002952048300000094
Wherein C ismFor memory capacity of a memory vessel, alpha2Representing a memory capacity value CmRate of change of beta2Representing a memory capacity value CmIs a from an initial value of2、β2Respectively as follows:
Figure BDA0002952048300000095
the parameters obtained by the above calculation are put into the memory element general simulator of this embodiment, and the input terminal a and the input terminal B are respectively connected to an external circuit to simulate the use of a memcapacitor.
In order to verify the correctness of the memcapacitor simulated by the memory element general simulator of the embodiment, the applicant shows that the formula V of the excitation voltage is usedABObtaining (2 pi ft) or (ω t) A sin
Figure BDA0002952048300000096
Wherein the content of the first and second substances,
Figure BDA00029520483000000915
is a VABThe integral value of time is compared to obtain the magnetic flux of memory container
Figure BDA00029520483000000916
Amplitude of and
Figure BDA0002952048300000097
in a proportional relationship.
And according to the formula
Figure BDA0002952048300000098
Transform derived algorithm
Figure BDA0002952048300000099
And according to an algorithm
Figure BDA00029520483000000910
At VAB-qABDrawing hysteresis curve in plane, comparing to obtain when exciting voltage VABWhile the amplitude of the magnetic flux is kept constant, the magnetic flux increases with the excitation frequency
Figure BDA00029520483000000917
Is reduced in amplitude, the charge qABBecomes smaller in magnitude at VAB-qABThe hysteresis loop curve is drawn in the plane to contract inwards.
According to the theoretical analysis, the applicant also adopts Pspice software to carry out simulation experiments, and builds the memory element universal simulator of the embodiment in the Pspice software and puts the following parameters into the simulator: sinusoidal excitation voltage VABIs a VABSin (2 pi ft) (V), capacitance C1＝0.25nF、C2＝0.1nF、R1＝3kΩ、R2＝11kΩ、Vs-0.5V, in each of the current feedback type current feedback operational amplifier and the multiplier U5The power supply ends are respectively connected with a direct current supply voltage with the amplitude of +/-15V。
Because some internal variables to be measured are not easy to be directly detected, the memory element universal simulator of the embodiment adopts an equivalent substitution mode to equivalently substitute measurable data which is in direct proportion to the variables to be measured for the requirement of experimental result analysis. This approach is suitable for Pspice software simulation.
For the memory device general simulator of this embodiment, qABIs a current i flowing between the input terminal A and the input terminal BABThe time integral value is obtained by i based on the current following characteristic of the current feedback operational amplifier AD844AB＝-i4. Capacitor C2The integration function is performed in the general simulator of the memory device
Figure BDA0002952048300000101
Wherein the content of the first and second substances,
Figure BDA0002952048300000107
is a capacitor C2The voltage value at both ends is
Figure BDA0002952048300000102
It can be seen that q isABAnd
Figure BDA0002952048300000105
in a proportional relationship, can be used
Figure BDA0002952048300000106
Equivalent substitution of qABFor calculating, and VABThe voltage between the input end A and the input end B can be directly measured.
When the excitation frequency is 95kHz, 100kHz and 105kHz, the voltage V between the input end A and the input end BABAnd is equivalent to charge qABVoltage of
Figure BDA0002952048300000108
The lissajous phase trace of (a) is shown in fig. 6.
Comparing the trace graphs at the frequencies of 95kHz, 100kHz and 105kHz respectively, the important characteristics of the memcapacitor can be obtained: memory capacity value CmAt VAB-qABKeeping a hysteresis loop in a shape like a slant '8' in a plane, keeping the amplitude of the voltage unchanged along with the increase of the frequency of the excitation voltage, and keeping the charge qABThe variation range of (2) is reduced, and the hysteresis ring is contracted inwards.
In summary, the result of the simulation experiment is consistent with the theoretical analysis, so the memory device general simulator of the present embodiment can simulate the memory characteristics of the memory capacitor.
Example 3
For the memristor, the relationship of the internal state variables q- ρ of the simulator and the reciprocal L of the memristive valuem -1Can be defined as:
Figure BDA0002952048300000103
Figure BDA0002952048300000104
wherein alpha is3Represents Lm -1Slope of change of beta3Represents Lm -1Is started.
Referring to fig. 4, under the condition that an excitation voltage is applied between a and B, the matching setting of various parameters in the memory element general simulator of the embodiment is completed by the following method to simulate the use of a memory sensor:
inductor L1Connected in series to the first transformation memory interface T1Between the positive and negative terminals, a resistance R2Connected in series to the second transformation memory interface T2Between the positive end and the negative end, the inductance L can be obtained by the voltage following characteristic of the current feedback operational amplifier AD8441Voltage V acrossABAnd current i1Respectively as follows:
Figure BDA0002952048300000111
wherein the content of the first and second substances,
Figure BDA00029520483000001113
voltage V for memory sensorABIntegration over time.
Current feedback operational amplifier U1C on the z-terminal of1Providing integral operation, current feedback operational amplifier U1The current outputted by the z terminal is equal to the current outputted by the x terminal, so that the current passes through C1The charge q of (a) is:
Figure BDA0002952048300000112
where ρ isABIs a magnetic flux
Figure BDA00029520483000001114
Integration over time.
Available multiplier U5Output voltage V ofwComprises the following steps:
Figure BDA0002952048300000113
current feedback operational amplifier U2Z terminal output voltage V2zCan be expressed as:
Figure BDA0002952048300000114
Figure BDA0002952048300000115
Figure BDA0002952048300000116
wherein L ism -1(ρAB) For magnetic flux memory sensors to memorize inverse values of induction values, alpha3Represents Lm -1Rate of change of beta3Represents Lm -1Is a from an initial value of3、β3Respectively as follows:
Figure BDA0002952048300000117
the parameters obtained by the above calculation are put into the memory element general simulator of this embodiment, and the input terminal a and the input terminal B are respectively connected to an external circuit to be used as a simulated memory sensor.
In order to verify the correctness of the memcapacitor simulated by the memory element general simulator of the embodiment, the applicant shows that the formula V of the excitation voltage is usedABA sin (2 pi ft) ═ a sin (ω t), where,
Figure BDA00029520483000001117
is a VABIntegral value over time, pABIs composed of
Figure BDA00029520483000001118
Integral value over time, and thus the conversion formula can be obtained
Figure BDA0002952048300000118
The integral value rho can be obtained by comparisonABAmplitude of and
Figure BDA0002952048300000119
in a proportional relationship.
And according to the formula
Figure BDA00029520483000001110
Transform derived algorithm
Figure BDA00029520483000001111
And according to an algorithm
Figure BDA00029520483000001112
In that
Figure BDA00029520483000001119
Drawing hysteresis curve in plane, comparing to obtain when exciting voltage VABWhile the amplitude of the magnetic flux is kept constant, the magnetic flux increases with the excitation frequency
Figure BDA00029520483000001115
And integrated value ρ thereofABWill become smaller, making the memory sensing value inverse value Lm -1Gradually approaches beta3In a
Figure BDA00029520483000001116
The hysteresis loop curve is drawn in the plane to contract inwards.
The memory element universal simulator of the present embodiment was built in Pspice software and the following parameters were put in: sinusoidal excitation voltage VABIs a VAB3sin (2 pi ft) (V), capacitance C1＝0.02nF、R1＝3kΩ、R2＝8kΩ、L1＝0.05H、Vs-2.5V, in each of the current feedback type current feedback operational amplifier and multiplier U5The power supply ends are respectively connected with a direct current power supply voltage with the amplitude of +/-15V.
Since some variables to be measured in the memory device general simulator of this embodiment are not easily detected, for the analysis of experimental results, we will use an equivalent substitution method to substitute measurable data, which is directly proportional to the variables to be measured, for the variables to be measured. This approach is suitable for Pspice software simulation.
For the memory sensor simulated by the memory element general simulator of the embodiment, iABThe current flowing between the input end A and the input end B can be directly measured by a meter pen in Pspice software simulation; based on the voltage following characteristic of the current feedback operational amplifier AD844, and the inductance L1Has a voltage of V at both endsABCan derive
Figure BDA0002952048300000121
As can be seen,
Figure BDA0002952048300000122
and i1In a proportional relationship, i can be used1Equivalent substitution
Figure BDA0002952048300000125
For algorithmic calculations.
When the excitation frequencies are 95kHz, 100kHz and 105kHz, respectively, the current iABAnd equivalent to magnetic flux
Figure BDA0002952048300000123
Current i of1The Lissajous phases of (A) are shown in FIG. 7.
Comparing the trace plots at frequencies of 95kHz, 100kHz and 105kHz respectively, important characteristics of the memory sensor can be obtained: memory inductance reciprocal Lm -1At i1-iABThe magnetic hysteresis loop in the shape of an oblique 8 is kept in a plane, and the voltage amplitude is kept unchanged and the magnetic flux is kept constant along with the increase of the frequency of the excitation voltage
Figure BDA0002952048300000124
And ρABThe hysteresis ring contracts inward as it becomes smaller.
In summary, the simulation experiment result is consistent with the theoretical analysis, so the memory device general simulator of the present embodiment can simulate the memory characteristics of the memory sensor.
Has the advantages that: in the above embodiments 1, 2 and 3, only the first transformation memory interface T is changed1Positive and negative end, second conversion memory interface T2The characteristics of a memristor, a memristor capacitor and a memristor can be simulated by the resistor, the capacitor or the inductor which are respectively connected with the positive end and the negative end in series, and the characteristics of the memristor, the capacitor and the inductor can be realized without additional equipment or auxiliary circuits, so that the memristor, the capacitor and the inductor which are obtained through simulation can be flexibly connected with other circuits for use, meanwhile, the circuit structure of the embodiment is simple, the circuit experiment is easy, and the converted memristor, the capacitor and the inductor can present the memory characteristics under the working frequency higher than 100 kHZ. Compared with the prior art, the memristor, the memcapacitor and the meminductor respectively simulated in the embodiments 1, 2 and 3 can reduce the consumption of the frequency in the circuit by 11.8% in the use process, but the memristor, the memcapacitor and the meminductor in the embodiment can be simulated at the frequency of 100kHZThe frequency of the memory element universal simulator is increased by 162 times compared with the existing 0.8kHZ, so that the memory element universal simulator can be flexibly used in a circuit with the frequency of 100kHZ, and a memristor, a memristor and a memory sensor which are simulated conveniently are put into industrial production.
It should be noted that:
the method of the present embodiment may be implemented by a method that is converted into program steps and apparatuses that can be stored in a computer storage medium and invoked and executed by a controller.
The algorithms and displays presented herein are not inherently related to any particular computer, virtual machine, or other apparatus nor is the particular language used to disclose the best mode of the invention.
In the description provided herein, numerous specific details are set forth. It is understood, however, that embodiments of the invention may be practiced without these specific details. In some instances, well-known methods, structures and techniques have not been shown in detail in order not to obscure an understanding of this description.
Similarly, it should be appreciated that in the foregoing description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together in a single embodiment, figure, or description thereof for the purpose of streamlining the disclosure and aiding in the understanding of one or more of the various inventive aspects. However, the disclosed method should not be interpreted as reflecting an intention that: that the invention as claimed requires more features than are expressly recited in each claim. Rather, as the following claims reflect, inventive aspects lie in less than all features of a single foregoing disclosed embodiment. Thus, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of this invention.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments.
The various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It will be appreciated by those skilled in the art that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components of the apparatus for detecting a wearing state of an electronic device according to embodiments of the present invention. The present invention may also be embodied as apparatus or device programs (e.g., computer programs and computer program products) for performing a portion or all of the methods described herein. Such programs implementing the present invention may be stored on computer-readable media or may be in the form of one or more signals. Such a signal may be downloaded from an internet website or provided on a carrier signal or in any other form.
For example, fig. 8 shows a schematic structural diagram of an electronic device according to an embodiment of the invention. The electronic device conventionally comprises a processor 21 and a memory 22 arranged to store computer-executable instructions (program code). The memory 22 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. The memory 22 has a storage space 23 storing program code 24 for performing any of the method steps in the embodiments. For example, the storage space 23 for the program code may comprise respective program codes 24 for implementing respective steps in the above method. The program code can be read from or written to one or more computer program products. These computer program products comprise a program code carrier such as a hard disk, a Compact Disc (CD), a memory card or a floppy disk. Such a computer program product is typically a computer readable storage medium such as described in fig. 9. The computer readable storage medium may have memory segments, memory spaces, etc. arranged similarly to the memory 22 in the electronic device of fig. 8. The program code may be compressed, for example, in a suitable form. In general, the memory unit stores program code 31 for performing the steps of the method according to the invention, i.e. program code readable by a processor such as 21, which when run by an electronic device causes the electronic device to perform the individual steps of the method described above.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.

Claims (9)

1. A memory element universal simulator is characterized by comprising a controller, four current feedback operational amplification chips for amplifying signals at high frequency, a multiplier, a power supply, an integrator, a plurality of resistors, a capacitor and an inductor, wherein the four current feedback operational amplifiers are respectively marked as U1、U2、U3、U4Any one of the current feedback operational amplification chips has an x terminal, a y terminal, a p terminal and a z terminal, and the current feedback operational amplification chip U1The y end of the current transformer is divided into two branches, wherein one branch is connected to a current feedback operational amplification chip U3And the other branch is taken as an input end A, and the current feedback operation is used for amplifying the chip U1The x terminal of the first transformation memory interface T1The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation2The x terminal of the first transformation memory interface T1Negative terminal of, the first transformation memory interface T1The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or an inductor in series, and the current feedback operational amplifier chip U2The y end of the current transformer is connected with a current feedback operational amplification chip U, and two branches are divided4And the other branch is taken as an input end B, and a current feedback operation amplification chip U1The z end is grounded through an integrator, and a current feedback operational amplification chip U1P terminal of and multiplier U5X of1End connection, current feedback operational amplification chip U2The z end is grounded through a resistor, and a current feedback operational amplification chip U2P terminal of and multiplier U5Y of (A) to (B)1End-connected, multiplier U5X of2The end is grounded through a power supply, and a multiplier U5Y of (A) to (B)2The end and the z end are grounded after being connected together, and a multiplier U5W terminal and current feedback operational amplification chip U3The y end of the current feedback operational amplifier chip U is connected with3P end of the p-type amplifier is open-circuited, and the current feedback operation is used for amplifying the chip U3The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2The positive terminal of the current amplifier is used for amplifying the chip U by current feedback operation4The x terminal of the first conversion memory interface T is used as a second conversion memory interface T2Negative terminal of, a second transformation memory interface T2The positive end and the negative end of the current feedback operational amplifier are connected with a resistor or a capacitor in series, and the current feedback operational amplifier chip U4P-end open circuit, current feedback operational amplification chip U4The y end of the controller is grounded, the controller is connected with the input end A and the input end B, and the working frequency ranges from 0kHZ to 100 kHZ.
2. The memory element universal simulator of claim 1, wherein the integrator is a capacitor.
3. The memory device universal simulator according to claim 2, wherein the current flowing from the input terminal a is iABCurrent feedback operational amplifier chip U3Has a current of i at the z-terminal5Flow direction to the first conversion memory interface T1Has a current of i as a negative terminal1From current feedback operational amplification chip U4The current flowing out of the z terminal is i6From current feedback operational amplification chip U1The current flowing out of the z terminal is i2From current feedback operational amplification chip U2The current flowing out of the z terminal is i3From current feedback operational amplification chip U3The x terminal of (a) flows a current of i4。
4. The memory device universal simulator of claim 1, wherein if the first transformation memory interface T is1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The other resistor is connected in series between the input end A and the input end B, and then the input end A and the input end B are connected with an external circuit to simulate a memristor.
5. The memory device universal simulator of claim 1, wherein if the first transformation memory interface T is1Positive terminal and first transformation memory interface T1A resistor is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2A capacitor is connected in series between the input terminals A and B, and the input terminals A and B are connected with an external circuitTo simulate a memcapacitor.
6. The memory device universal simulator of claim 1, wherein if the first transformation memory interface T is1Positive terminal and first transformation memory interface T1An inductance is connected in series between the negative terminals of the first and second conversion memory interfaces T2Positive terminal and second transformation memory interface T2The input end A and the input end B are connected with an external circuit to simulate the memory inductor.
7. The memory element universal simulator of claim 4, wherein said V1x＝VA，V2x＝VB(ii) a According to an algorithm
Figure FDA0002952048290000021
To obtain the current flowing through the first transformation memory interface T1Current i between positive and negative terminals1；
According to an algorithm
Figure FDA0002952048290000022
To obtain current feedback operational amplification chip U1The voltage of the middle p-terminal is,
according to an algorithm
Figure FDA0002952048290000023
To obtain current feedback operational amplification chip U2The voltage of the middle p-terminal is,
according to an algorithm
Figure FDA0002952048290000024
To find the multiplier U5Output voltage V ofw
Calculating current feedback operational amplification chip U3Current feedback operational amplification chip U4The voltages respectively correspond to: v3x＝V3y＝Vw，V4x＝V4y＝0
Calculating current feedback operational amplification chip U3Current feedback operational amplification chip U4The respective currents are: i.e. i4＝-iAB，
Figure FDA0002952048290000025
According to an algorithm
Figure FDA0002952048290000026
Figure FDA0002952048290000027
To obtain the memristor memory conductance value
Figure FDA0002952048290000028
Wherein the content of the first and second substances,
Figure FDA0002952048290000029
is the voltage V between the input terminal A and the input terminal BABIntegral value over time, memristor's memristive memristor's value
Figure FDA00029520482900000210
Is about
Figure FDA00029520482900000211
Function of alpha1Representing the rate of change of the memory conductance, beta1Represents the initial value of the memory conductance value, and alpha1、β1Respectively as follows:
Figure FDA00029520482900000212
8. memory element universal simulator according to claim 5, characterized in that it is based on an algorithm
Figure FDA00029520482900000213
Figure FDA00029520482900000214
To obtain the capacitance C2Voltage across
Figure FDA00029520482900000215
Through a capacitor C2Electric charge of
Figure FDA00029520482900000216
Comprises the following steps:
Figure FDA00029520482900000217
Figure FDA00029520482900000218
Figure FDA00029520482900000219
wherein the content of the first and second substances,
Figure FDA00029520482900000220
is flowing through a capacitor C2Current i of4Integral over time, CmFor memory capacity of a memory vessel, alpha2Representing a memory capacity value CmRate of change of beta2Representing a memory capacity value CmIs a from an initial value of2、β2Respectively as follows:
Figure FDA0002952048290000031
9. the memory element universal simulator of claim 6, wherein the current through the inductor is calculated according to an algorithm as:
Figure FDA0002952048290000032
according to an algorithm
Figure FDA0002952048290000033
To obtain the capacitance C1A charge q on, a calculating multiplier U5Output voltage V ofwComprises the following steps:
Figure FDA0002952048290000034
calculating current feedback operational amplification chip U2Z terminal output voltage V2z：
Figure FDA0002952048290000035
Where ρ isABIs a magnetic flux
Figure FDA0002952048290000036
The integral of the time is taken into account,
Figure FDA0002952048290000037
voltage V for memory sensorABIntegral over time, Lm -1(ρAB) Is the reciprocal of the memristive value of the memristor, alpha3Represents Lm -1Rate of change of beta3Represents Lm -1Is a from an initial value of3、β3Respectively as follows:
Figure FDA0002952048290000038
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