CN113093639A - Power control method and device for programmable logic device and electronic equipment - Google Patents
Power control method and device for programmable logic device and electronic equipment Download PDFInfo
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- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
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Abstract
The application discloses a power control method and device of an editable logic device and electronic equipment, wherein the method comprises the following steps: determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules; and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches. According to the implementation scheme, when the programmable logic device needs to be reset or reset, all the functional modules in the editable logic device are reset or reset in batches, so that the transient current pressure for resetting or resetting all the functional modules in a centralized manner is dispersed, the service life of the editable logic device is effectively prolonged, and the normal use of a user is guaranteed.
Description
Technical Field
The present disclosure relates to electrical control technologies, and in particular, to a power control method and apparatus for a programmable logic device, and an electronic device.
Background
In order to provide continuous and efficient services, some base stations and data centers use accelerator cards, such as FPGA (Field Programmable Gate Array) chips, to increase data processing speed. When the FPGA is designed for coding, all the functional modules are reset or reset at the same time, so that a large transient current is generated, voltage overshoot or voltage undershoot of the FPGA is caused, the FPGA is permanently damaged or the function of the FPGA is abnormal, and the normal use of a user is influenced.
Disclosure of Invention
In view of this, the present application provides the following technical solutions:
a method of power control for a programmable logic device, comprising:
determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules;
and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
Optionally, the functional module in the functional module set is a functional module whose rated power is greater than a first set value, or the functional module set includes all the functional modules in the programmable logic device.
Optionally, before the controlling the functional modules in the functional module set to gradually implement resetting or resetting in batches, the method further includes:
and decoupling the functional modules in the functional module set, so that the decoupled functional modules can realize resetting or resetting at different times in batches under the condition of receiving a resetting instruction or a resetting instruction.
Optionally, the controlling the functional modules in the functional module set to implement resetting or resetting in batches includes:
determining a range of electrical parameters that the power module is capable of withstanding, the range of electrical parameters including at least one of a voltage float range and a current float range;
determining processing batches of functional modules in the set of functional modules based on the electrical parameter range, so that the change of the electrical parameter caused by all the functional modules in each processing batch in the process of simultaneously executing reset or reset is within the electrical parameter range, wherein each processing batch contains at least one functional module, and different processing batches execute the reset instruction or the reset instruction at different times;
and controlling the functional modules in the functional module set to realize resetting or resetting based on the processing batch.
Optionally, the power sums of the functional modules corresponding to different processing batches are the same or different.
Optionally, the set of functional modules includes a first processing batch, a second processing batch and a third processing batch, the processing time difference between the first processing batch and the second processing batch is a first interval time, the processing time difference between the second processing batch and the third processing batch is a second interval time, and the first interval time and the second interval time are the same or different.
Optionally, the controlling the functional modules in the functional module set to implement resetting or resetting in batches includes:
controlling the functional module corresponding to the first processing batch in the functional module set to realize resetting or resetting;
and controlling the functional module corresponding to the second processing batch in the functional module set to realize resetting or resetting, wherein the priority of the functional module corresponding to the second processing batch is lower than that of the functional module corresponding to the first processing batch.
Optionally, the function implementation of the functional module corresponding to the second processing batch is performed based on the processing result of the functional module corresponding to the first processing batch.
A power control apparatus for a programmable logic device, comprising:
the set determining module is used for determining a functional module set in the programmable logic device, wherein the functional module set comprises a plurality of functional modules;
and the instruction execution module is used for controlling the functional modules in the functional module set to realize resetting or resetting releasing in batches under the condition of receiving a resetting instruction or a resetting releasing instruction.
An electronic device, comprising:
a processor;
a memory for storing executable instructions of the processor;
wherein the executable instructions comprise: determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules; and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
Through the technical scheme, the embodiment of the application discloses a power control method and device of an editable logic device and electronic equipment, and the method comprises the following steps: determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules; and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches. According to the implementation scheme, when the programmable logic device needs to be reset or reset, all the functional modules in the editable logic device are reset or reset in batches, so that the transient current pressure for resetting or resetting all the functional modules in a centralized manner is dispersed, the service life of the editable logic device is effectively prolonged, and the normal use of a user is guaranteed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on the provided drawings without creative efforts.
Fig. 1 is a flowchart of a power control method of a programmable logic device according to an embodiment of the present application;
FIG. 2 is a flow chart of another method for power control of a programmable logic device according to an embodiment of the present disclosure;
FIG. 3 is a flowchart illustrating a batch-wise reset or reset-release process according to an embodiment of the present disclosure;
FIG. 4 is a flow chart of another batch-wise reset or reset-release method disclosed in an embodiment of the present application;
FIG. 5 is a schematic view of a current-time curve without batch processing as disclosed in an embodiment of the present application;
FIG. 6 is a schematic view of a current-time curve for batch processing as disclosed in an embodiment of the present application;
fig. 7 is a schematic structural diagram of a power control method and apparatus for a programmable logic device disclosed in an embodiment of the present application.
Detailed Description
For the sake of reference and clarity, the descriptions, abbreviations or abbreviations of the technical terms used hereinafter are summarized as follows:
FPGA: the Field Programmable Gate Array is a product developed on the basis of Programmable devices such as PAL and GAL. The circuit is a semi-custom circuit in the field of Application Specific Integrated Circuits (ASIC), not only overcomes the defects of the custom circuit, but also overcomes the defect that the number of gate circuits of the original programmable device is limited.
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Fig. 1 is a flowchart of a power control method of a programmable logic device disclosed in an embodiment of the present application, and referring to fig. 1, the power control method of the programmable logic device may include:
step 101: determining a functional module set in the programmable logic device, wherein the functional module set comprises a plurality of functional modules.
The programmable logic device can be but is not limited to an FPGA, and the FPGA belongs to a semi-custom circuit in an application-specific integrated circuit and is a programmable logic array.
In practical application, a user can program corresponding functions on the programmable logic device according to requirements. After the corresponding functional programming is completed, the programmable logic device may include a plurality of functional modules, and the operating states of the functional modules are controlled by the programmable logic device.
Step 102: and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
When the programmable logic device is designed to encode, all the functional modules in the programmable logic device are reset or reset at the same time, so that a large transient current is generated, voltage overshoot or voltage undershoot is caused, and the service life of the programmable logic device is not facilitated. Therefore, in this embodiment, when the programmable logic device needs to be reset or reset, the functional modules in the functional module set are controlled to implement resetting or resetting in batches, so that the functional modules that are reset or reset at the same time are part of all the functional modules, and the transient current required at the time in the implementation is much smaller than the transient current for simultaneously resetting or resetting all the functional modules, thereby avoiding the voltage overshoot or voltage undershoot of the programmable logic device, and effectively ensuring the working performance of the editable logic device.
For example, the FPGA includes a video encoding module, a video decoding module, a protocol conversion module, a data buffering module, a calculating module, a code simulation module, a storage module, a digital clock management module, and other functional modules, and when the modules are reset or reset at the same time, the required transient current may reach 120A. Based on the application, the video coding module and the video decoding module are determined as a first batch, the protocol conversion module, the data buffering module and the code simulation module are determined as a second batch, and the storage module, the calculation module and the digital clock management module are determined as a third batch; when the FPGA realizes the reset, firstly resetting or resetting the functional modules in the first batch at a first time point, wherein the transient current of the first time point is about 35A; resetting or resetting the functional modules of the second batch at a second time point, wherein the transient current change of the second time point is about 50A; resetting or resetting the functional modules of the third batch at a third time point, wherein the transient current change of the third time point is about 35A; therefore, the function modules in the FPGA realize resetting or resetting in batches, and the pressure of the transient current at one time point is dispersed to different time points. It should be noted that the interval time between the first time point and the second time point, and the interval time between the second time point and the third time point are not too large, so as to ensure that the time for the whole FPGA to reset or reset is not too long, and avoid the use experience of the application user.
In the power control method of the editable logic device according to this embodiment, when the programmable logic device needs to be reset or reset, all the functional modules in the editable logic device are reset or reset in batches, so that the transient current pressure for resetting or resetting all the functional modules in a centralized manner is dispersed, the service life of the editable logic device is effectively prolonged, and the normal use of a user is ensured.
For some functional modules with very small rated power, the total value of the current required by all the functional modules in resetting or resetting is also little influenced because the current value required by the functional modules in resetting or resetting is very small. Based on this situation, the present embodiment may consider that only the functional module with a larger rated power is reset or reset in batches. Therefore, the functional modules in the functional module set are functional modules with rated power larger than a first set value. Of course, in the embodiment of the present application, no limitation may be imposed on the functional modules included in the functional module set, and in this case, the functional module set includes all the functional modules in the programmable logic device. For example, for some functional modules rated at less than 1W, since the current variation caused by resetting or resetting is small, the small power functions can be randomly distributed to several determined processing batches based on the average distribution principle.
Fig. 2 is a flowchart of another power control method for a programmable logic device disclosed in an embodiment of the present application, and as shown in fig. 2, in one implementation, the power control method for a programmable logic device may include the following steps:
step 201: determining a functional module set in the programmable logic device, wherein the functional module set comprises a plurality of functional modules.
Step 202: and decoupling the functional modules in the functional module set, so that the decoupled functional modules can realize resetting or resetting at different times in batches under the condition of receiving a resetting instruction or a resetting instruction.
In practical situations, some functional blocks in the editable logic device may have coupling, cascading and the like, so that when reset or reset is performed, the functional blocks having the coupling or cascading condition are reset or reset together. Therefore, in this embodiment, before the function module in the function module set is controlled to implement resetting or resetting in batches, the function module in the function module set is decoupled, so as to better implement subsequent resetting or resetting in batches.
It should be noted that, in order to ensure the normal implementation of the functions of some functional modules, it must be designed to be coupled with other functional modules, or based on the consideration of cost, some functional modules need to be designed to be coupled; in this case, only the functional modules with a small degree of coupling are decoupled, and the functional modules that cannot be decoupled are divided into one processing batch, so that the functional modules having a coupling relationship are reset or reset together.
For example, the FPGA includes a protocol conversion module, a calculation module, a storage module, a code simulation module, a digital clock management module, and other functional modules. The calculating module and the storage module, and the calculating module and the digital clock management module are coupled, only the decoupling of the calculating module and the digital clock management module is realized through decoupling processing, and the calculating module and the storage module cannot realize decoupling due to high coupling degree, so that the calculating module and the storage module need to be in a processing batch when the processing batches are divided, and other functional modules are not limited.
Step 203: and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
The FPGA has different structures, the FPGA can realize combinational logic by utilizing small lookup tables (16 multiplied by 1RAM) in the realization, each lookup table is connected to the input end of a D trigger, and the triggers drive other logic circuits or drive I/O (input/output), thereby forming a basic logic unit module which can realize the combinational logic function and the sequential logic function, and the modules are mutually connected or connected to the I/O module by utilizing metal connecting wires.
In one specific implementation, during FPGA coding design, a plurality of high-power modules inside an FPGA are identified, the high-power modules are decoupled during function design, and the high-power modules are hierarchically reset at intervals in a function loading process; meanwhile, when the function is removed, the modules are reset in a grading way at certain time intervals; thereby reducing the transient current requirements.
Continuing with the example introduced above, the FPGA includes functional modules such as a video encoding module, a video decoding module, a protocol conversion module, a data buffering module, a computing module, a code simulation module, a storage module, and a digital clock management module, wherein the functional modules with power greater than 5W include a frequency encoding module, a video decoding module, a computing module, and a code simulation module, and are high-power functional modules, and the four high-power functional modules do not have a coupling relationship with each other; then, when dividing the processing batch, the four functional modules can be divided into four processing batches, so that only one high-power functional module is included in one processing batch.
Fig. 3 is a flowchart of batch-wise resetting or resetting according to an embodiment of the present disclosure, and referring to fig. 3, in one implementation, the controlling the functional module in the functional module set to batch-wise reset or reset may include:
step 301: a range of electrical parameters that the power module is capable of withstanding is determined, the range of electrical parameters including at least one of a voltage float range and a current float range.
Step 302: determining the processing batches of the functional modules in the functional module set based on the electrical parameter range so that the change of the electrical parameter caused by all the functional modules in each processing batch in the process of simultaneously executing the reset or the reset is within the electrical parameter range.
Wherein each of the processing batches comprises at least one functional module, and different processing batches execute the reset instruction or the reset instruction at different times. The sum of the powers of the functional modules corresponding to different processing batches may be the same or different.
In one implementation, the set of function modules includes a first processing batch, a second processing batch and a third processing batch, the difference between the processing time of the first processing batch and the processing time of the second processing batch is a first interval time, the difference between the processing time of the second processing batch and the processing time of the third processing batch is a second interval time, and the first interval time and the second interval time may be the same or different.
And determining the processing batch of the functional modules in the functional module set based on the electric parameter range, so that the working safety of the power supply module can be effectively guaranteed and the power supply module is in a normal working state. Overall, the normal working state of the power module and the editable logic device can be effectively ensured, and the service life of the power module and the editable logic device is prolonged.
Step 303: and controlling the functional modules in the functional module set to realize resetting or resetting based on the processing batch.
In this embodiment, the processing batches of the functional modules in the functional module set are determined based on the range of the electrical parameters that can be borne by the power supply module, so that the change of the electrical parameters, which is caused in the process of simultaneously performing reset or reset-release of all the functional modules in each processing batch, is within the range of the electrical parameters, and the normal operating state of the editable logic device of the power supply module is ensured.
Fig. 4 is a flowchart of another batch-wise reset or reset-release method disclosed in an embodiment of the present application, and referring to fig. 4, in an implementation, the controlling the functional module in the functional module set to batch-wise reset or reset-release may include:
step 401: and controlling the functional module corresponding to the first processing batch in the functional module set to realize resetting or resetting.
Step 402: and controlling the functional module corresponding to the second processing batch in the functional module set to realize resetting or resetting, wherein the priority of the functional module corresponding to the second processing batch is lower than that of the functional module corresponding to the first processing batch.
It can be understood that there is a difference in priority level between different functional modules, and when the editable logic device is reset or reset, the processing sequence of the processing batches can be determined according to the priority levels of the functional modules corresponding to different processing batches.
In one implementation, the function implementation of the functional module corresponding to the second processing batch is performed based on the processing result of the functional module corresponding to the first processing batch.
For example, the first functional module belongs to a first processing batch, the second functional module belongs to a second processing batch, and the first functional module is a prerequisite implementation of the second functional module, that is, only after the first functional module runs, the function of the second functional module can be implemented, and then the priority of the first functional module is higher than that of the second functional module. Then, when the editable logic device is reset, the first functional module (first processing batch) may be reset first, and the second functional module (second processing batch) may be reset; when the editable logic device is reset, the second functional module (second processing batch) may be reset first, and the first functional module (first processing batch) may be reset.
In one specific implementation, the core current of the programmable logic device is taken as 100A for comparison. Fig. 5 is a schematic view of a current-time curve without batch processing disclosed in the embodiment of the present application, and fig. 6 is a schematic view of a current-time curve with batch processing disclosed in the embodiment of the present application. Referring to fig. 5 and 6, when the batch control is not performed, the 100A load is simultaneously reset and loaded, and the transient current is required to be 100A/several uS; and (3) carrying out batch control, dividing the 100A load into 5 modules (taking 5 modules as an example for explanation), and carrying out resetting loading at an interval of 10uS, wherein the transient current is 20A/several US. In fig. 6, it is shown that the instantaneous current required by each processing batch is the same, and the processing time intervals of different batches are the same, in practical cases, the instantaneous current required by different processing batches may be different, and the processing time intervals of different batches may also be different.
While, for purposes of simplicity of explanation, the foregoing method embodiments have been described as a series of acts or combination of acts, it will be appreciated by those skilled in the art that the present application is not limited by the order of acts or acts described, as some steps may occur in other orders or concurrently with other steps in accordance with the application. Further, those skilled in the art should also appreciate that the embodiments described in the specification are preferred embodiments and that the acts and modules referred to are not necessarily required in this application.
The method is described in detail in the embodiments disclosed in the present application, and the method of the present application can be implemented by various types of apparatuses, so that an apparatus is also disclosed in the present application, and the following detailed description is given of specific embodiments.
Fig. 7 is a schematic structural diagram of a power control apparatus of a programmable logic device disclosed in an embodiment of the present application, and referring to fig. 7, the power control apparatus of an editable logic device may include:
a set determining module 701, configured to determine a set of function modules in the programmable logic device, where the set of function modules includes a plurality of function modules.
And the instruction execution module 702 is configured to, when a reset instruction or a reset release instruction is received, control the functional modules in the functional module set to implement reset or reset release in batches.
In the power control apparatus of the editable logic device according to this embodiment, when the programmable logic device needs to be reset or reset, all the functional modules in the editable logic device are reset or reset in batches, so that the transient current pressure for resetting or resetting all the functional modules in a centralized manner is dispersed, the service life of the editable logic device is effectively prolonged, and the normal use of a user is ensured.
In one implementation, the functional modules in the functional module set are functional modules with rated power greater than a first set value, or the functional module set includes all the functional modules in the programmable logic device.
In one implementation, the method further comprises: and the decoupling processing module is used for decoupling the functional modules in the functional module set before the instruction execution module controls the functional modules in the functional module set to gradually realize resetting or resetting in batches, so that the decoupled functional modules can realize resetting or resetting in batches at different times under the condition of receiving a resetting instruction or a resetting-releasing instruction.
In one implementation, the instruction execution module is specifically configured to: determining a range of electrical parameters that the power module is capable of withstanding, the range of electrical parameters including at least one of a voltage float range and a current float range; determining processing batches of functional modules in the set of functional modules based on the electrical parameter range, so that the change of the electrical parameter caused by all the functional modules in each processing batch in the process of simultaneously executing reset or reset is within the electrical parameter range, wherein each processing batch contains at least one functional module, and different processing batches execute the reset instruction or the reset instruction at different times; and controlling the functional modules in the functional module set to realize resetting or resetting based on the processing batch.
In one implementation, the power sums of the functional modules corresponding to the processing batches are the same or different.
In one implementation, the set of function modules includes a first processing batch, a second processing batch and a third processing batch, the difference between the processing time of the first processing batch and the processing time of the second processing batch is a first interval time, the difference between the processing time of the second processing batch and the processing time of the third processing batch is a second interval time, and the first interval time and the second interval time are the same or different.
In one implementation, the instruction execution module is specifically configured to: controlling the functional module corresponding to the first processing batch in the functional module set to realize resetting or resetting; and controlling the functional module corresponding to the second processing batch in the functional module set to realize resetting or resetting, wherein the priority of the functional module corresponding to the second processing batch is lower than that of the functional module corresponding to the first processing batch.
In one implementation, the function implementation of the functional module corresponding to the second processing batch is performed based on the processing result of the functional module corresponding to the first processing batch.
Further, the present application also discloses an electronic device, including:
a processor;
a memory for storing executable instructions of the processor;
wherein the executable instructions comprise: determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules; and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
The power control method and apparatus for any programmable logic device in the foregoing embodiments include a processor and a memory, where the set determining module, the instruction executing module, the decoupling processing module, and the like in the foregoing embodiments are all stored in the memory as program modules, and the processor executes the program modules stored in the memory to implement corresponding functions.
The processor comprises a kernel, and the kernel calls the corresponding program module from the memory. The kernel can be provided with one or more, and the processing of the return visit data is realized by adjusting the kernel parameters.
The memory may include volatile memory in a computer readable medium, Random Access Memory (RAM) and/or nonvolatile memory such as Read Only Memory (ROM) or flash memory (flash RAM), and the memory includes at least one memory chip.
Embodiments of the present application provide a storage medium on which a program is stored, and the program implements the power control method of the programmable logic device described in the above embodiments when executed by a processor.
The embodiment of the present application provides a processor, where the processor is configured to execute a program, where the program executes the power control method of the programmable logic device in the foregoing embodiment when running.
Further, the present embodiment provides an electronic device, which includes a processor and a memory. Wherein the memory is used for storing executable instructions of the processor, and the processor is configured to execute the power control method of the programmable logic device described in the above embodiment through executing the executable instructions.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A method of power control for a programmable logic device, comprising:
determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules;
and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
2. The method for controlling power of a programmable logic device according to claim 1, wherein the functional modules in the set of functional modules are functional modules with a rated power greater than a first set value, or the set of functional modules includes all the functional modules in the programmable logic device.
3. The power control method of the programmable logic device according to claim 1, before the controlling the functional modules in the set of functional modules to gradually implement resetting or resetting in batches, further comprising:
and decoupling the functional modules in the functional module set, so that the decoupled functional modules can realize resetting or resetting at different times in batches under the condition of receiving a resetting instruction or a resetting instruction.
4. The power control method of the programmable logic device according to claim 1, wherein the controlling the function modules in the set of function modules to implement resetting or resetting in batches comprises:
determining a range of electrical parameters that the power module is capable of withstanding, the range of electrical parameters including at least one of a voltage float range and a current float range;
determining processing batches of functional modules in the set of functional modules based on the electrical parameter range, so that the change of the electrical parameter caused by all the functional modules in each processing batch in the process of simultaneously executing reset or reset is within the electrical parameter range, wherein each processing batch contains at least one functional module, and different processing batches execute the reset instruction or the reset instruction at different times;
and controlling the functional modules in the functional module set to realize resetting or resetting based on the processing batch.
5. The method according to claim 4, wherein the power sums of the functional modules corresponding to different processing batches are the same or different.
6. The method of claim 4, wherein the set of functional blocks comprises a first processing batch, a second processing batch, and a third processing batch, the first processing batch differs from the second processing batch by a first interval time, the second processing batch differs from the third processing batch by a second interval time, and the first interval time is the same as or different from the second interval time.
7. The power control method of the programmable logic device according to claim 1, wherein the controlling the function modules in the set of function modules to implement resetting or resetting in batches comprises:
controlling the functional module corresponding to the first processing batch in the functional module set to realize resetting or resetting;
and controlling the functional module corresponding to the second processing batch in the functional module set to realize resetting or resetting, wherein the priority of the functional module corresponding to the second processing batch is lower than that of the functional module corresponding to the first processing batch.
8. The power control method of a programmable logic device according to claim 7, wherein the function implementation of the functional module corresponding to the second processing batch is performed based on the processing result of the functional module corresponding to the first processing batch.
9. A power control apparatus for a programmable logic device, comprising:
the set determining module is used for determining a functional module set in the programmable logic device, wherein the functional module set comprises a plurality of functional modules;
and the instruction execution module is used for controlling the functional modules in the functional module set to realize resetting or resetting releasing in batches under the condition of receiving a resetting instruction or a resetting releasing instruction.
10. An electronic device, comprising:
a processor;
a memory for storing executable instructions of the processor;
wherein the executable instructions comprise: determining a functional module set in a programmable logic device, wherein the functional module set comprises a plurality of functional modules; and under the condition of receiving a reset instruction or a reset-releasing instruction, controlling the functional modules in the functional module set to realize reset or reset-releasing in batches.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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