CN113078104A - Method for manufacturing microelectronic integrated circuit element - Google Patents
Method for manufacturing microelectronic integrated circuit element Download PDFInfo
- Publication number
- CN113078104A CN113078104A CN202110334525.9A CN202110334525A CN113078104A CN 113078104 A CN113078104 A CN 113078104A CN 202110334525 A CN202110334525 A CN 202110334525A CN 113078104 A CN113078104 A CN 113078104A
- Authority
- CN
- China
- Prior art keywords
- layer
- underfill material
- integrated circuit
- flow underfill
- carrier substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000004377 microelectronic Methods 0.000 title claims abstract description 34
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 13
- 238000000034 method Methods 0.000 title claims description 9
- 239000010410 layer Substances 0.000 claims abstract description 47
- 239000000463 material Substances 0.000 claims abstract description 28
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 239000011241 protective layer Substances 0.000 claims abstract description 12
- 238000009736 wetting Methods 0.000 claims abstract description 4
- 238000002161 passivation Methods 0.000 description 11
- 239000004065 semiconductor Substances 0.000 description 3
- 238000011161 development Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 239000011800 void material Substances 0.000 description 2
- 241000282414 Homo sapiens Species 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 230000007812 deficiency Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- QJGQUHMNIGDVPM-UHFFFAOYSA-N nitrogen group Chemical group [N] QJGQUHMNIGDVPM-UHFFFAOYSA-N 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76837—Filling up the space between adjacent conductive structures; Gap-filling properties of dielectrics
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Ceramic Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
A method of manufacturing a microelectronic integrated circuit element includes preparing a carrier substrate, a microelectronic die having an integrated circuit; preparing a no-flow underfill material between the carrier substrate and the die; improving the wetting and flow characteristics of the no-flow underfill material by preheating the no-flow underfill material; forming a protective layer to cover the carrier substrate to form a mask layer; removing part of the protective layer, and leaving part on the protective layer to form a sacrificial layer; a height-defining layer is formed, the height-defining layer being located on a lower surface of the upper surface of the sacrificial layer.
Description
Technical Field
The invention relates to the technical field of microelectronics, in particular to a method for manufacturing a microelectronic integrated circuit element.
Background
Microelectronics is the subject of a microminiature integrated circuit system that acts on semiconductors. The key to microelectronics is the study of how integrated circuits operate and how they are actually fabricated.
The development of integrated circuits relies on the constant evolution of semiconductor devices. The micro-electronic technology can realize the processing and the transmission of information through the micro-electronic motion in a solid in a nano-scale ultra-small area and has good integration.
Essentially, the heart of microelectronics is the integrated circuit that is formed during the development of various types of semiconductor devices. In the information age, the micro-electronic technology brings great influence to the production and life of human beings.
Disclosure of Invention
Technical problem to be solved
To overcome the deficiencies of the prior art, a method for fabricating a microelectronic integrated circuit device is proposed to solve the above-mentioned problems in the background art.
(II) technical scheme
The invention is realized by the following technical scheme: the invention provides a method for manufacturing a microelectronic integrated circuit element, which is characterized in that: the method comprises the following steps:
s1: preparing a carrier substrate, a microelectronic die having an integrated circuit;
s2: preparing a no-flow underfill material between the carrier substrate and the die;
s3: improving the wetting and flow characteristics of the no-flow underfill material by preheating the no-flow underfill material;
s4: forming a protective layer to cover the carrier substrate to form a mask layer;
s5: removing part of the protective layer, and leaving part on the protective layer to form a sacrificial layer;
s6: a height-defining layer is formed, the height-defining layer being located on a lower surface of the upper surface of the sacrificial layer.
Further, the no-flow underfill material is preheated prior to contacting the microelectronic die or the carrier substrate.
Further, the structure is assembled by dispensing a no-flow underfill material onto the carrier substrate and then adjacent to the no-flow underfill material.
Further, the structure is assembled by dispensing a no-flow underfill material onto the microelectronic die and then adjacent to the no-flow underfill material.
Further, a gate dielectric layer is formed over the gate dielectric layer.
Further, a gate electrode layer is formed thereon.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The invention provides a method for manufacturing a microelectronic integrated circuit element, which is characterized in that: the method comprises the following steps:
s1: preparing a carrier substrate, a microelectronic die having an integrated circuit;
s2: preparing a no-flow underfill material between the carrier substrate and the die;
s3: improving the wetting and flow characteristics of the no-flow underfill material by preheating the no-flow underfill material;
s4: forming a protective layer to cover the carrier substrate to form a mask layer;
s5: removing part of the protective layer, and leaving part on the protective layer to form a sacrificial layer;
s6: a height-defining layer is formed, the height-defining layer being located on a lower surface of the upper surface of the sacrificial layer.
The first embodiment:
preferably, the no-flow underfill material is preheated prior to contact with the microelectronic die or the carrier substrate.
Further, the structure is assembled by dispensing a no-flow underfill material onto the carrier substrate and then adjacent to the no-flow underfill material.
Further, the structure is assembled by dispensing a no-flow underfill material onto the microelectronic die and then adjacent to the no-flow underfill material.
Second embodiment:
preferably, a gate dielectric layer is formed over the gate dielectric layer.
Preferably, a gate electrode layer is formed over the gate electrode layer.
Holding the microelectronic die with a chuck while the interconnect element is being reflowed; and releasing the chuck from the microelectronic die, the microelectronic die being held with the chuck while the interconnection element is being reflowed; and releasing the chuck from the microelectronic die, preheating the no-flow underfill material at a temperature between 30 ℃ and 120 ℃, reflowing the interconnect element at a temperature of at least 183 ℃.
Providing a substrate having a passivation layer and a plurality of insulating structures, wherein the passivation layer is disposed in the substrate, and the plurality of insulation structures extend over the passivation layer and at least partially extend over the substrate, a mask is formed on a portion of a plane formed by the passivation layer and the plurality of insulation structures, the portion being a first portion, and the portion of the planar portion not masked by the mask is a second portion, such that the first portion and the second portion share a boundary, removing the sacrificial portion of the passivation layer from the second portion, removing the mask, forming a conformal layer over the remaining portion of the passivation layer, over the insulating structure and in a void formed by removing the sacrificial portion of the passivation layer, planarizing the conformal layer, so that the conformal layer, the insulating structure and the remaining portion of the passivation layer are coplanar, removing the remaining portion of the passivation layer, and forming a transistor in a void created by the removal of the remaining portion of the passivation layer.
The passivation layer includes a dielectric material having a dielectric constant of 5.5-9, the dielectric material is an oxygen-containing layer or a nitrogen-containing layer, the substrate includes at least one memory cell region and at least one peripheral circuit region, and the mask is formed on at least a portion of the peripheral circuit region and at least a portion of the exposed memory cell region.
The above-described embodiments are merely illustrative of the preferred embodiments of the present invention and do not limit the spirit and scope of the present invention. Various modifications and improvements of the technical solutions of the present invention may be made by those skilled in the art without departing from the design concept of the present invention, and the technical contents of the present invention are all described in the claims.
Claims (6)
1. A method of fabricating a microelectronic integrated circuit device, comprising: the method comprises the following steps:
s1: preparing a carrier substrate, a microelectronic die having an integrated circuit;
s2: preparing a no-flow underfill material between the carrier substrate and the die;
s3: improving the wetting and flow characteristics of the no-flow underfill material by preheating the no-flow underfill material;
s4: forming a protective layer to cover the carrier substrate to form a mask layer;
s5: removing part of the protective layer, and leaving part on the protective layer to form a sacrificial layer;
s6: a height-defining layer is formed, the height-defining layer being located on a lower surface of the upper surface of the sacrificial layer.
2. The method of manufacturing a microelectronic integrated circuit element according to claim 1, characterized in that: in step 3, the no-flow underfill material is preheated prior to contacting the microelectronic die or carrier substrate.
3. The method of manufacturing a microelectronic integrated circuit element according to claim 2, characterized in that: the structure is assembled by dispensing a no-flow underfill material onto the carrier substrate and then adjacent to the no-flow underfill material.
4. The method of manufacturing a microelectronic integrated circuit element according to claim 2, characterized in that: the structure is assembled by dispensing a no-flow underfill material onto the microelectronic die and then adjacent to the no-flow underfill material.
5. The method of manufacturing a microelectronic integrated circuit element according to claim 1, characterized in that: in step 6, a gate dielectric layer is formed over the gate dielectric layer.
6. The method of manufacturing a microelectronic integrated circuit element according to claim 1, characterized in that: in step 6, a gate electrode layer is formed over the gate electrode layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110334525.9A CN113078104A (en) | 2021-03-29 | 2021-03-29 | Method for manufacturing microelectronic integrated circuit element |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110334525.9A CN113078104A (en) | 2021-03-29 | 2021-03-29 | Method for manufacturing microelectronic integrated circuit element |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113078104A true CN113078104A (en) | 2021-07-06 |
Family
ID=76611133
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110334525.9A Pending CN113078104A (en) | 2021-03-29 | 2021-03-29 | Method for manufacturing microelectronic integrated circuit element |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113078104A (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| TW200531250A (en) * | 2003-12-15 | 2005-09-16 | Intel Corp | A method of making a microelectronic assembly |
| CN1702851A (en) * | 2003-12-03 | 2005-11-30 | 台湾积体电路制造股份有限公司 | Method for manufacturing microelectronic circuit component and integrated circuit component |
| US8148826B2 (en) * | 2006-12-19 | 2012-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional integrated circuits with protection layers |
| CN105244289A (en) * | 2014-07-08 | 2016-01-13 | 台湾积体电路制造股份有限公司 | Methods of packaging semiconductor devices and packaged semiconductor devices |
| US10446442B2 (en) * | 2016-12-21 | 2019-10-15 | Globalfoundries Inc. | Integrated circuit chip with molding compound handler substrate and method |
| CN111128767A (en) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of formation |
-
2021
- 2021-03-29 CN CN202110334525.9A patent/CN113078104A/en active Pending
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1702851A (en) * | 2003-12-03 | 2005-11-30 | 台湾积体电路制造股份有限公司 | Method for manufacturing microelectronic circuit component and integrated circuit component |
| TW200531250A (en) * | 2003-12-15 | 2005-09-16 | Intel Corp | A method of making a microelectronic assembly |
| CN1890790A (en) * | 2003-12-15 | 2007-01-03 | 英特尔公司 | Method of making a microelectronic assembly |
| US8148826B2 (en) * | 2006-12-19 | 2012-04-03 | Taiwan Semiconductor Manufacturing Co., Ltd. | Three-dimensional integrated circuits with protection layers |
| CN105244289A (en) * | 2014-07-08 | 2016-01-13 | 台湾积体电路制造股份有限公司 | Methods of packaging semiconductor devices and packaged semiconductor devices |
| US10446442B2 (en) * | 2016-12-21 | 2019-10-15 | Globalfoundries Inc. | Integrated circuit chip with molding compound handler substrate and method |
| CN111128767A (en) * | 2018-10-31 | 2020-05-08 | 台湾积体电路制造股份有限公司 | Semiconductor device and method of formation |
Non-Patent Citations (1)
| Title |
|---|
| 周建民: "《集成电路应用》", 1 January 2015 * |
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| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20210706 |
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| WD01 | Invention patent application deemed withdrawn after publication |