CN113077717B - Display panel and display device - Google Patents

Display panel and display device Download PDF

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Publication number
CN113077717B
CN113077717B CN202110306761.XA CN202110306761A CN113077717B CN 113077717 B CN113077717 B CN 113077717B CN 202110306761 A CN202110306761 A CN 202110306761A CN 113077717 B CN113077717 B CN 113077717B
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pixel electrode
segment
pixel
electrically connected
electrode
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CN113077717A (en
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吕晓文
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TCL China Star Optoelectronics Technology Co Ltd
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TCL China Star Optoelectronics Technology Co Ltd
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09F—DISPLAYING; ADVERTISING; SIGNS; LABELS OR NAME-PLATES; SEALS
    • G09F9/00—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements
    • G09F9/30—Indicating arrangements for variable information in which the information is built-up on a support by selection or combination of individual elements in which the desired character or characters are formed by combining individual elements
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device

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  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Liquid Crystal (AREA)
  • Theoretical Computer Science (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Abstract

The embodiment of the application discloses a display panel and a display device, wherein the display panel comprises a plurality of scanning lines, a plurality of data lines and a plurality of pixel units, and the plurality of scanning lines are arranged at intervals along a first direction; the data lines are arranged at intervals along a second direction, and the data lines and the scanning lines are arranged in a crossed mode; the pixel units are arranged in an array, the pixel units in every two adjacent rows are correspondingly and electrically connected to one scanning line, and the pixel units in each column are correspondingly and electrically connected to one data line. The application improves the aperture opening ratio of the display panel and can meet the application requirement of the high-transmittance display screen.

Description

Display panel and display device
Technical Field
The application relates to the technical field of display, in particular to a display panel and a display device.
Background
1K4K is widely used in the field of sports events as a new display mode, and 1K4K is a display screen that improves the display tailing problem by increasing the refresh rate of the display screen by turning on two adjacent scan lines together.
In the conventional 1K4K display panel design, the requirement of high refresh frequency is usually achieved by shorting adjacent odd and even scan lines together. However, in the above design, for the sub-pixels short-circuited to the adjacent odd and even rows of the same scan signal, the pixel aperture ratio of the corresponding display panel is low, and it is difficult to meet the application requirement of the high-penetration display screen.
Disclosure of Invention
The embodiment of the application provides a display panel and a display device, which are used for solving the technical problem that the pixel aperture ratio of the display panel is low in the prior art.
The embodiment of the present application provides a display panel, display panel includes:
the scanning lines are arranged at intervals along a first direction;
the data lines are arranged at intervals along a second direction and are crossed with the scanning lines; and
the pixel units are arranged in an array, the pixel units in every two adjacent rows are correspondingly and electrically connected to one scanning line, and the pixel units in every column are correspondingly and electrically connected to one data line.
Optionally, in some embodiments of the present application, in the pixel units in any column, every two adjacent pixel units share one data signal output terminal, where the data signal output terminal is used to access a data signal.
Optionally, in some embodiments of the present application, two adjacent pixel units electrically connected to one scan line in the first direction are respectively a first pixel unit and a second pixel unit, the scan line is located between the first pixel unit and the second pixel unit, the first pixel unit includes a first main pixel electrode and a first sub-pixel electrode, and the first main pixel electrode is located on a side of the first sub-pixel electrode away from the scan line; the second pixel unit comprises a second main pixel electrode and a second secondary pixel electrode, and the second main pixel electrode is positioned on one side of the second secondary pixel electrode close to/far away from the scanning line;
a first transistor, a second transistor and a third transistor are arranged between the first pixel unit and the second pixel unit; a gate electrode of the first transistor, a gate electrode of the second transistor, and a gate electrode of the third transistor are electrically connected to the scan line, a source electrode of the first transistor and a source electrode of the second transistor are electrically connected to the data line, a drain electrode of the first transistor is electrically connected to the first main pixel electrode and the second main pixel electrode, a drain electrode of the second transistor is electrically connected to the first sub-pixel electrode and the second sub-pixel electrode, a source electrode of the third transistor is electrically connected to a drain electrode of the second transistor, and a drain electrode of the third transistor is electrically connected to a common electrode.
Optionally, in some embodiments of the present application, the display panel further includes a substrate, and the scan line, the data line, the first pixel unit, and the second pixel unit are disposed on the substrate;
the first main pixel electrode and the second main pixel electrode are electrically connected through a first transmission line, and the orthographic projection of the first transmission line on the plane of the substrate is at least partially overlapped with the orthographic projection of the data line on the plane of the substrate.
Optionally, in some embodiments of the present application, the first transmission trace includes a first segment, a second segment, a third segment, and a fourth segment;
the extending direction of the first segment is parallel to the extending direction of the data line, and the orthographic projection of the first segment on the plane of the substrate is positioned in the orthographic projection of the data line on the plane of the substrate; two ends of the second segment are respectively and electrically connected with the first segment and the first main pixel electrode; two ends of the third segment are respectively and electrically connected with the first segment and the second main pixel electrode; the fourth segment is located between the second segment and the third segment, one end of the fourth segment is connected with the first segment, and the other end of the fourth segment is electrically connected with the drain of the first transistor.
Optionally, in some embodiments of the present application, the first main pixel electrode and the second main pixel electrode are electrically connected through a first transmission trace, and the first transmission trace is located on one side of the data line close to the first main pixel electrode.
Optionally, in some embodiments of the present application, the first sub-pixel electrode and the second sub-pixel electrode are electrically connected through a second transmission trace;
the extending direction of the second transmission line is parallel to the extending direction of the data line/the second transmission line is positioned at one side of the first sub-pixel electrode far away from the data line.
Optionally, in some embodiments of the present application, two adjacent pixel units electrically connected to one scan line in the first direction are a first pixel unit and a second pixel unit, respectively, the scan line is located between the first pixel unit and the second pixel unit, the first pixel unit includes a first pixel electrode, and the second pixel unit includes a second pixel electrode;
a transistor is arranged between the first pixel electrode and the second pixel electrode, the grid electrode of the transistor is electrically connected with the scanning line, the source electrode of the transistor is electrically connected with the data line, and the drain electrode of the transistor is electrically connected with the first pixel electrode and the second pixel electrode.
Optionally, in some embodiments of the present application, the display panel further includes a substrate, and the scan line, the data line, the first pixel unit, and the second pixel unit are disposed on the substrate;
the first pixel electrode and the second pixel electrode are electrically connected through a transmission line, the orthographic projection of the transmission line on the plane of the substrate is at least partially overlapped with the orthographic projection of the data line on the plane of the substrate/the transmission line is positioned on one side of the data line close to the first pixel electrode.
The embodiment of the present application further provides a display device, which includes the display panel described in any one of the foregoing embodiments.
Compare in display panel among the prior art, the display panel that this application provided corresponds the electricity through the pixel unit that makes every adjacent two lines and connects in a scanning line for the quantity of scanning line is halved on the display panel, has saved the panel space, and then has improved display panel's pixel aperture ratio, can satisfy the application demand of high transmissivity display screen.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic plan view of a display panel in the prior art.
Fig. 2 is a schematic plan view of a display panel provided in the present application.
Fig. 3 is a schematic structural diagram of a first pixel unit and a second pixel unit in a first embodiment of a display panel provided in the present application.
Fig. 4 is an equivalent circuit diagram of a first embodiment of a display panel provided in the present application.
Fig. 5 is a schematic structural diagram of a first pixel unit and a second pixel unit in a second embodiment of a display panel provided in the present application.
Fig. 6 is a schematic structural diagram of a first pixel unit and a second pixel unit in a third embodiment of a display panel provided in the present application.
Fig. 7 is an equivalent circuit diagram of a third embodiment of a display panel provided in the present application.
Fig. 8 is a schematic structural diagram of a first pixel unit and a second pixel unit in a fourth embodiment of a display panel provided in the present application.
Fig. 9 is a schematic structural diagram of a first pixel unit and a second pixel unit in a fifth embodiment of a display panel provided by the present application.
Fig. 10 is a schematic structural diagram of a first pixel unit and a second pixel unit in a sixth embodiment of a display panel provided in the present application.
Fig. 11 is a schematic structural diagram of a first pixel unit and a second pixel unit in a seventh embodiment of a display panel provided by the present application.
Fig. 12 is a schematic structural diagram of a first pixel unit and a second pixel unit in an eighth embodiment of a display panel provided by the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described clearly and completely with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only some embodiments of the present application, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application. Furthermore, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the present application, are given by way of illustration and explanation only, and are not intended to limit the present application. In the present application, unless indicated to the contrary, the use of the directional terms "upper" and "lower" generally refer to the upper and lower positions of the device in actual use or operation, and more particularly to the orientation of the figures of the drawings; while "inner" and "outer" are with respect to the outline of the device.
It should be noted that the transistors used in all the embodiments of the present application may be thin film transistors or field effect transistors or other devices with the same characteristics. Since the source and the drain of the transistor adopted by the application are symmetrical, the source and the drain can be interchanged. In the embodiments of the present application, to distinguish two electrodes of a transistor except for a gate, one of the two electrodes is referred to as a source and the other is referred to as a drain. The form of the figure provides that the middle end of the transistor is a grid, the signal input end is a source, and the output end is a drain.
Referring to fig. 1, in the design of the display panel 10 ' of the conventional 1K4K display screen, the scan lines 1a ' of the adjacent odd rows and the scan lines 1a ' of the even rows are shorted together, so that the adjacent two scan lines 1a ' are connected to the same scan signal Gate ', thereby increasing the refresh frequency of the display screen and improving the problem of display tailing.
However, although the above design shorts the scan line 1a 'of the adjacent odd row and the scan line 1 a' of the even row, the sub-pixel 3 'of each row is still electrically connected to one scan line 1 a'. Since the scan lines 1 a' occupy the panel space, the pixel aperture ratio in the display panel is sacrificed by the above circuit design, and thus it is difficult to meet the application requirement of the high transmittance display panel.
In view of the above technical problems in the prior art, embodiments of the present invention provide a display panel and a display device, which are described in detail below. It should be noted that the following description of the embodiments is not intended to limit the preferred order of the embodiments.
Referring to fig. 2, the present application provides a display panel 10. The display panel 10 includes a substrate 10a, and a plurality of scan lines 1, a plurality of data lines 2, and a plurality of pixel units 3 disposed on the substrate 10 a. The plurality of scanning lines 1 are arranged at intervals in the first direction X. The plurality of data lines 2 are arranged at intervals in the second direction Y. The plurality of data lines 2 are disposed to cross the plurality of scan lines 1. The plurality of pixel units 3 are arranged in an array. The pixel units 3 in every two adjacent rows are correspondingly electrically connected to a scan line 1. The pixel units 3 of each row are correspondingly electrically connected to a data line 2.
Therefore, the display panel 10 provided by the application is electrically connected to one scanning line 1 through the pixel units 3 in every two adjacent rows, so that the number of the scanning lines 1 on the display panel 10 is halved, the panel space is saved, the pixel aperture opening ratio can be improved in the pixel design of the display panel 10, and the application requirement of the high-transmittance display screen can be met.
Referring to fig. 3 and 4, in a first embodiment of the display panel of the present application, two adjacent pixel units 3 electrically connected to a scan line 1 in a first direction X are a first pixel unit 31 and a second pixel unit 32, respectively. The scanning line 1 is located between the first pixel unit 31 and the second pixel unit 32. The first pixel unit 31 includes a first pixel electrode 31 a. The second pixel unit 32 includes a second pixel electrode 32 a.
It should be noted that, in this embodiment, each of the first pixel electrode 31a and the second pixel electrode 32a includes four pixel partitions (not labeled in the figure), and the specific structure of the pixel partitions may refer to the prior art, which is not described herein again.
Specifically, a transistor T is disposed between the first pixel electrode 31a and the second pixel electrode 32 a. The Gate of the transistor T is electrically connected to the scan line 1 for receiving the scan signal Gate. The source of the transistor T is electrically connected to the data line 2. The drain of the transistor T is electrically connected to the first pixel electrode 31a and the second pixel electrode 32 a.
In the present embodiment, the first pixel unit 31 and the second pixel unit 32 share one data signal output terminal 2 a. The Data signal output terminal 2a is used for accessing the Data signal Data. The data signal output terminal 2a is electrically connected to the source of the transistor T.
In addition, in the equivalent circuit diagram of the display panel 10 of the present embodiment, as shown in fig. 4, a first storage capacitor Cst 1 is formed between the first pixel electrode 31a and a first common electrode (not shown in the figure). The first common electrode is connected with a first common electrode signal A COM. A first liquid crystal capacitor Clc 1 is formed between the first pixel electrode 31a and a second common electrode (not shown). The second common electrode is connected with a second common electrode signal CF COM. A second storage capacitor Cst2 is formed between the second pixel electrode 32a and the first common electrode, and a second liquid crystal capacitor Clc 2 is formed between the second storage capacitor Cst and the second common electrode.
The first common electrode is located on the array substrate of the display panel 10, the second common electrode is located on the color film substrate of the display panel 10, and routing of the first common electrode and routing of the second common electrode are not illustrated.
In the present embodiment, the first pixel electrode 31a and the second pixel electrode 32a are electrically connected by the transmission line 33. The transmission trace 33 is used for transmitting the pixel voltage V. The orthographic projection of the transmission trace 33 on the plane of the substrate 10a at least partially overlaps the orthographic projection of the data line 2 on the plane of the substrate 10 a.
The transmission trace 33, the first pixel electrode 31a and the second pixel electrode 32a are disposed in the same layer in the pixel electrode layer of the display panel 10, and are integrally formed with the first pixel electrode 31a and the second pixel electrode 32a, so that the process can be simplified, and the process cost can be saved.
Specifically, the transmission trace 33 includes a first segment 33a, a second segment 33b, a third segment 33c, and a fourth segment 33 d.
The extending direction of the first segment 33a is parallel to the extending direction of the data line 2. The orthographic projection of the first segment 33a on the plane of the substrate 10a is located in the orthographic projection of the data line 2 on the plane of the substrate 10 a. The arrangement reduces the occupied space of the transmission line 33, and can further save the panel space, thereby improving the pixel aperture ratio of the display panel 10.
The second segment 33b is positioned between the first segment 33a and the first pixel electrode 31 a. Both ends of the second segment 33b are electrically connected to the first segment 33a and the first pixel electrode 31a, respectively. Wherein one end of the second section 33b is connected to the first section 33 a. The other end of the second segment 33b is connected to the first pixel electrode 31 a.
The third segment 33c is located between the first segment 33a and the second pixel electrode 32 a. Both ends of the third segment 33c are electrically connected to the first segment 33a and the second pixel electrode 32a, respectively. One end of the third section 33c is connected to the first section 33 a. The other end of the third segment 33c is connected to the second pixel electrode 32 a.
Fourth section 33d is located between second section 33b and third section 33 c. One end of the fourth section 33d is connected to the first section 33 a. The other end of the fourth segment 33d is electrically connected to the drain of the transistor T through a via 33A.
It should be noted that the via 33A may be disposed in the insulating film layer of the display panel 10 to implement conduction between the corresponding traces, which is not described herein again.
Referring to fig. 5, a second embodiment of the display panel 10 provided in the present application is different from the display panel 10 provided in the first embodiment in that: the transmission trace 33 is located on a side of the data line 2 close to the first pixel electrode 31 a. The above arrangement can prevent the generation of parasitic capacitance between the transmission line 33 and the data line 2.
Referring to fig. 6 and 7, in a third embodiment of the display panel 10 provided in the present application, the display panel 10 includes a substrate 10a, and a plurality of scan lines 1, a plurality of data lines 2, and a plurality of pixel units 3 disposed on the substrate 10 a. The plurality of scanning lines 1 are arranged at intervals in the first direction X. The plurality of data lines 2 are arranged at intervals in the second direction Y. The plurality of data lines 2 are disposed to cross the plurality of scan lines 1. The plurality of pixel units 3 are arranged in an array. The pixel units 3 in every two adjacent rows are correspondingly electrically connected to a scan line 1. The pixel units 3 of each row are correspondingly electrically connected to a data line 2.
In the present embodiment, two adjacent pixel units 3 electrically connected to a scan line 1 in the first direction X are the first pixel unit 31 and the second pixel unit 32, respectively. The scanning line 1 is located between the first pixel unit 31 and the second pixel unit 32. The first pixel unit 31 includes a first main pixel electrode 311 and a first sub pixel electrode 312. The first main pixel electrode 311 is located on a side of the first sub-pixel electrode 312 away from the scan line 1. The second pixel unit 32 includes a second main pixel electrode 321 and a second sub pixel electrode 322. The second main pixel electrode 321 is located on a side of the second sub pixel electrode 322 close to the scan line 1.
In the embodiment, the first pixel unit 31 is configured to include the first main pixel electrode 311 and the first sub-pixel electrode 312, and the second pixel unit 32 is configured to include the second main pixel electrode 321 and the second sub-pixel electrode 322, so that the pixel electrodes in the display panel have a main part and a sub-part, and thus, the pixel aperture ratio is improved while the pixel viewing angle is maintained unchanged.
It should be noted that, in this embodiment, each of the first main pixel electrode 311, the first sub-pixel electrode 312, the second main pixel electrode 321, and the second sub-pixel electrode 322 includes four pixel partitions (not identified in the figure), and specific structures of the pixel partitions may refer to the prior art, which is not described herein again.
In addition, in some embodiments, the positions of the first main pixel electrode 311 and the first sub-pixel electrode 312 may be interchanged, and correspondingly, the positions of the first sub-pixel electrode 312 and the second sub-pixel electrode 322 are also interchanged, which is not described herein again.
Specifically, a first transistor T1, a second transistor T2, and a third transistor T3 are disposed between the first pixel unit 31 and the second pixel unit 32. The Gate of the first transistor T1, the Gate of the second transistor T2, and the Gate of the third transistor T3 are electrically connected to the scan line 1, and are used for receiving a scan signal Gate. The source of the first transistor T1 and the source of the second transistor T2 are electrically connected to the Data line 2 for receiving the Data signal Data. The drain electrode of the first transistor T1 is electrically connected to the first main pixel electrode 311 and the second main pixel electrode 321. The drain electrode of the second transistor T2 is electrically connected to the first sub-pixel electrode 312 and the second sub-pixel electrode 322 through the first via 323A. The source of the third transistor T3 is electrically connected to the drain of the second transistor T2. The drain of the third transistor T3 is electrically connected to the first common electrode (not shown in the figure) for receiving the first common electrode signal acom.
In addition, in the equivalent circuit diagram of the display panel 10 of the present embodiment, as shown in fig. 7, a first storage capacitor Cst 1 is formed between the first main pixel electrode 311 and the first common electrode, and a first liquid crystal capacitor Clc 1 is formed between the first storage capacitor Cst 1 and the second common electrode (not shown in the figure). The second common electrode is connected with a second common electrode signal CF COM. A second storage capacitor Cst2 is formed between the second sub-pixel electrode 322 and the first common electrode, and a second liquid crystal capacitor Clc 2 is formed between the second storage capacitor Cst2 and the second common electrode. A third storage capacitor Cst 3 is formed between the second main pixel electrode 321 and the first common electrode, and a third liquid crystal capacitor Clc 3 is formed between the second main pixel electrode and the second common electrode. A fourth storage capacitor Cst 4 is formed between the second sub-pixel electrode 322 and the first common electrode, and a fourth liquid crystal capacitor Clc 4 is formed between the second sub-pixel electrode and the second common electrode.
The first common electrode is located on the array substrate of the display panel 10, the second common electrode is located on the color film substrate of the display panel 10, and routing of the first common electrode and routing of the second common electrode are not illustrated.
In the present embodiment, the first main pixel electrode 311 and the second main pixel electrode 321 are electrically connected by the first transmission trace 313. The first transmission wiring 313 is used to transmit a first pixel voltage V1 (main area pixel voltage). The orthographic projection of the first transmission trace 313 on the plane of the substrate 10a is at least partially overlapped with the orthographic projection of the data line 2 on the plane of the substrate 10 a.
The first transmission trace 313, the first main pixel electrode 311 and the second main pixel electrode 321 are disposed in the same layer in the pixel electrode layer of the display panel 10, and are integrally formed with the first main pixel electrode 311 and the second main pixel electrode 321, so that the process can be simplified, and the process cost can be saved.
Specifically, the first transmission trace 313 includes a first segment 313a, a second segment 313b, a third segment 313c and a fourth segment 313 d.
The extending direction of the first segment 313a is parallel to the extending direction of the data line 2. The orthographic projection of the first segment 313a on the plane of the substrate 10a is located in the orthographic projection of the data line 2 on the plane of the substrate 10 a. The arrangement reduces the occupied space of the first transmission line 313, and can further save the panel space, thereby improving the pixel aperture ratio of the display panel 10.
The second segment 313b is positioned between the first segment 313a and the first main pixel electrode 311. Both ends of the second segment 313b are electrically connected to the first segment 313a and the first main pixel electrode 311, respectively. Wherein one end of the second segment 313b is connected to the first segment 313 a. The other end of the second segment 313b is connected to the first main pixel electrode 311.
The third segment 313c is positioned between the first segment 313a and the second main pixel electrode 321. Both ends of the third segment 313c are electrically connected to the first segment 313a and the second main pixel electrode 321, respectively. One end of the third segment 313c is connected to the first segment 313 a. The other end of the third segment 313c is connected to the second main pixel electrode 321.
Fourth segment 313d is located between second segment 313b and third segment 313 c. One end of the fourth segment 313d is connected to the first segment 313 a. The other end of the fourth segment 313d is electrically connected to the drain of the first transistor T1 through the second via 313A.
It should be noted that the second via hole 313A may be disposed in an insulating film layer of the display panel 10 to implement conduction between the traces, which is not described herein again.
In the present embodiment, the first sub-pixel electrode 312 and the second sub-pixel electrode 322 are electrically connected by the second transmission trace 323. The second transmission trace 323 is used for transmitting a second pixel voltage V2 (sub-pixel voltage). The second transmission trace 323 is located on a side of the first sub-pixel electrode 312 away from the data line 2.
Specifically, the second transmission trace 323 and the first transmission trace 313 are disposed on the same layer and are integrally formed. One end of the second transmission trace 323 is electrically connected to the first sub-pixel electrode 312. The other end of the second transmission trace 323 is electrically connected to the second sub-pixel electrode 322.
In the present embodiment, in the pixel unit 3 of any one column, each adjacent two pixel units 3 share one data signal output terminal 2 a. The Data signal output terminal 2a is used for accessing the Data signal Data.
Specifically, the first pixel unit 31 and the second pixel unit 32 share one data signal output terminal 2 a. That is, the source of the first transistor T1 is electrically connected to a data signal output terminal 2 a. A source of the second transistor T2 is electrically connected to a source of the first transistor T1 to receive the Data signal Data in the Data line 2.
In the display panel 10 ' shown in fig. 1, the data line 2 ' corresponding to the two sub-pixels 3 ' of the adjacent odd-numbered row and even-numbered row has two data signal output terminals 2a ', and the pixel aperture ratio in the display panel is sacrificed due to the extra wiring for transmitting the data signal required by the data signal output terminals 2a '.
In the pixel unit 3 of any column in this embodiment, each two adjacent pixel units 3 share one Data signal output end 2a, so that the number of the Data signal output ends 2a on the Data line 2 in the display panel 10 is also halved, that is, the number of the routing lines required for transmitting the Data signal Data is halved, thereby further saving the panel space and further improving the pixel aperture ratio in the design of the display panel 10.
The display panel 10 provided by this embodiment electrically connects the pixel units 3 in every two adjacent rows to one scan line 1, and in any column of the pixel units 3, every two adjacent pixel units 3 share one data signal output end 2a, so that the number of the scan lines 1 and the number of the data signal output ends 2a on the display panel 10 are both halved, and further the panel space can be saved to the greatest extent, the pixel aperture ratio of the display panel 10 is improved, and the application requirement of the high transmittance display screen is met.
Referring to fig. 8, a fourth embodiment of the display panel 10 provided in the present application is different from the display panel 10 provided in the third embodiment in that: in any column of pixel units 3, each two adjacent pixel units 3 respectively correspond to one data signal output end 2 a.
The first pixel unit 31 and the second pixel unit 32 respectively correspond to one Data signal output end 2a, that is, the source of the first transistor T1 and the source of the second transistor T2 are respectively electrically connected to one Data signal output end 2a to receive the Data signal Data in the Data line 2.
In the embodiment, the source of the first transistor T1 and the source of the second transistor T2 are electrically connected to one Data signal output terminal 2a, respectively, so that the delay effect in the Data signal Data process can be reduced, which is beneficial to improving the transmission efficiency of the Data signal.
Referring to fig. 9, a fifth embodiment of the display panel 10 provided in the present application is different from the display panel 10 provided in the third embodiment in that: the first transmission trace 313 is located on one side of the data line 2 close to the first main pixel electrode 311. The embodiment can avoid the generation of parasitic capacitance between the first transmission trace 313 and the data line 2.
Referring to fig. 10, a sixth embodiment of a display panel 10 provided in the present application is different from the display panel 10 provided in the third embodiment in that: the extending direction of the second transmission trace 323 is parallel to the extending direction of the data line 2.
Specifically, the orthogonal projection of the second transmission trace 323 on the plane of the substrate 10a sequentially crosses the scan line 1 and the second main pixel electrode 321 along the first direction X. One end of the second transmission trace 323 is electrically connected to the first sub-pixel electrode 312 through the first via 323A. The other end of the second transmission trace 323 is electrically connected to the second sub-pixel electrode 322 through the third via 323B.
In this embodiment, the second transmission trace 323 can avoid occupying a panel space, thereby being beneficial to improving the pixel aperture ratio of the display panel 10.
The second transmission trace 323 and the scan line 1 are disposed in the same layer in the first metal layer (not shown) of the display panel 10, and the second transmission trace 323 and the scan line 1 are integrally formed, so that the process can be simplified, and the process cost can be saved.
Referring to fig. 11, a seventh embodiment of the display panel 10 provided in the present application is different from the display panel 10 provided in the third embodiment in that: the second main pixel electrode 321 is located on a side of the second sub pixel electrode 322 far from the scan line 1.
Referring to fig. 12, in an eighth embodiment of the display panel 10 provided in the present application, the difference from the display panel 10 provided in the seventh embodiment is that: the extending direction of the second transmission trace 323 is parallel to the extending direction of the data line 2. The orthogonal projection of the second transmission trace 323 on the plane of the substrate 10a crosses the scan line 1 along the first direction X. One end of the second transmission trace 323 is electrically connected to the first sub-pixel electrode 312 through the first via 323A. The other end of the second transmission trace 323 is electrically connected to the second sub-pixel electrode 322 through the third via 323B.
In this embodiment, the second transmission trace 323 can avoid occupying a panel space, thereby being beneficial to improving the pixel aperture ratio of the display panel 10.
The second transmission trace 323 and the scan line 1 are disposed in the same layer in the first metal layer of the display panel 10, and the second transmission trace 323 and the scan line 1 are integrally formed, so that the process can be simplified, and the process cost can be saved.
The embodiment of the application also provides a display device which comprises a display panel. The display panel may be the display panel 10 according to any of the previous embodiments. The specific structure of the display panel 10 can refer to the description of the foregoing embodiments, and is not repeated herein.
Compared with a display panel in the prior art, the display panel provided by the application has the advantages that the number of the scanning lines on the display panel is halved by correspondingly electrically connecting the pixel units of every two adjacent lines to one scanning line, the panel space is saved, the pixel aperture opening ratio of the display panel is improved, and the application requirement of a high-transmittance display screen can be met.
The display panel and the display device provided by the embodiments of the present application are described in detail above, and the principles and embodiments of the present application are described herein by applying specific examples, and the description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.

Claims (7)

1. A display panel, comprising:
the scanning lines are arranged at intervals along a first direction;
the data lines are arranged at intervals along a second direction and are crossed with the scanning lines; and
the pixel units are arranged in an array, the pixel units in every two adjacent rows are correspondingly and electrically connected to one scanning line, and the pixel units in every column are correspondingly and electrically connected to one data line;
two adjacent pixel units electrically connected to a scanning line in the first direction are respectively a first pixel unit and a second pixel unit, the scanning line is located between the first pixel unit and the second pixel unit, the first pixel unit comprises a first main pixel electrode and a first sub-pixel electrode, and the first main pixel electrode is located on one side of the first sub-pixel electrode, which is far away from the scanning line; the second pixel unit comprises a second main pixel electrode and a second secondary pixel electrode, and the second main pixel electrode is positioned on one side of the second secondary pixel electrode close to/far away from the scanning line;
a first transistor, a second transistor and a third transistor are arranged between the first pixel unit and the second pixel unit; a gate electrode of the first transistor, a gate electrode of the second transistor, and a gate electrode of the third transistor are electrically connected to the scan line, a source electrode of the first transistor and a source electrode of the second transistor are electrically connected to the data line, a drain electrode of the first transistor is electrically connected to the first main pixel electrode and the second main pixel electrode, a drain electrode of the second transistor is electrically connected to the first sub-pixel electrode and the second sub-pixel electrode, a source electrode of the third transistor is electrically connected to a drain electrode of the second transistor, and a drain electrode of the third transistor is electrically connected to a common electrode.
2. The display panel according to claim 1, wherein in the pixel units in any column, each two adjacent pixel units share a data signal output terminal, and the data signal output terminal is used for receiving a data signal.
3. The display panel according to claim 1, wherein the display panel further comprises a substrate, and the scan lines, the data lines, the first pixel units, and the second pixel units are disposed on the substrate;
the first main pixel electrode and the second main pixel electrode are electrically connected through a first transmission line, and the orthographic projection of the first transmission line on the plane of the substrate is at least partially overlapped with the orthographic projection of the data line on the plane of the substrate.
4. The display panel of claim 3, wherein the first transmission trace comprises a first segment, a second segment, a third segment, and a fourth segment;
the extending direction of the first segment is parallel to the extending direction of the data line, and the orthographic projection of the first segment on the plane of the substrate is positioned in the orthographic projection of the data line on the plane of the substrate; two ends of the second segment are respectively and electrically connected with the first segment and the first main pixel electrode; two ends of the third segment are respectively and electrically connected with the first segment and the second main pixel electrode;
the fourth segment is located between the second segment and the third segment, one end of the fourth segment is connected with the first segment, and the other end of the fourth segment is electrically connected with the drain of the first transistor.
5. The display panel of claim 1, wherein the first main pixel electrode and the second main pixel electrode are electrically connected by a first transmission trace, and the first transmission trace is located on a side of the data line close to the first main pixel electrode.
6. The display panel according to claim 1, wherein the first sub-pixel electrode and the second sub-pixel electrode are electrically connected by a second transmission trace;
the extending direction of the second transmission line is parallel to the extending direction of the data line/the second transmission line is positioned on one side of the first sub-pixel electrode far away from the data line.
7. A display device characterized by comprising the display panel according to any one of claims 1 to 6.
CN202110306761.XA 2021-03-23 2021-03-23 Display panel and display device Active CN113077717B (en)

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