CN113076141A - Acceleration card power-on initialization method and device and acceleration card - Google Patents
Acceleration card power-on initialization method and device and acceleration card Download PDFInfo
- Publication number
- CN113076141A CN113076141A CN202110342293.1A CN202110342293A CN113076141A CN 113076141 A CN113076141 A CN 113076141A CN 202110342293 A CN202110342293 A CN 202110342293A CN 113076141 A CN113076141 A CN 113076141A
- Authority
- CN
- China
- Prior art keywords
- power
- working frequency
- accelerator card
- powered
- modules
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
- G06F13/4291—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus using a clocked protocol
Abstract
The invention discloses an accelerating card power-on initialization method, a device and an accelerating card, in the proposal, a pin of a control module is defined as a working frequency configuration pin, and a corresponding relation between the working frequency configuration pin and a preset working frequency of a memory module is established, so that the preset working frequency can be determined according to the level state of the working frequency configuration pin, at the moment, a user can adjust the current working frequency of the memory module by adjusting the level state of the working frequency configuration pin, and then a reference clock corresponding to the level state of the working frequency configuration pin adjusted by the user can be output after the accelerating card is powered on, so that the memory module works under the corresponding working frequency, the accelerating card containing the memory module can be applied to scenes with different frequencies, and clock configuration parameters and plug and burn hard wires in a software program do not need to be modified, the speed of modifying the working frequency is fast and the steps are simple.
Description
Technical Field
The present invention relates to the field of power-on initialization, and in particular, to a power-on initialization method and apparatus for an accelerator card, and an accelerator card.
Background
In a conventional power-on initialization mode of an accelerator card, a mode for initializing a clock of a memory module in the accelerator card is as follows:
and controlling the clock generator to output a reference clock corresponding to the clock configuration parameters according to the clock configuration parameters in the software program, so that the memory module works at a working frequency corresponding to the reference clock after being electrified. However, when the above initialization method is used, after the memory module is powered on, a fixed reference clock is provided for the memory module according to the clock configuration parameters, that is, the memory module works at a fixed working frequency after being powered on, if the accelerator card is to be applied to scenes with different working frequencies, the clock configuration parameters in the software program need to be modified each time the working frequency is changed, and the software program including the modified clock configuration parameters is burned into the clock generator corresponding to the memory module through the burning hard wire. Therefore, in order to adapt to scenes with various working frequencies, a user needs to modify clock configuration parameters in a software program and plug and unplug a burning hard wire each time the working frequency is changed, so that the speed is low, the steps are complicated, and the use of the user is inconvenient.
Disclosure of Invention
The invention aims to provide an accelerator card power-on initialization method, a device and an accelerator card, which can apply the accelerator card comprising a memory module to scenes with different frequencies, do not need to modify clock configuration parameters in a software program and plug and unplug a burning hard wire, and have higher speed of modifying the working frequency and simple steps.
In order to solve the above technical problem, the present invention provides a power-on initialization method for an accelerator card, which is applied to a control module, and comprises:
defining a selected pin of the control module as a working frequency configuration pin in advance;
establishing a corresponding relation between the level state of the working frequency configuration pin and a preset working frequency of a memory module;
after the accelerator card is powered on, acquiring the current level state of the working frequency pin, and determining the current working frequency of the memory module based on the current level state and the corresponding relation;
and controlling a clock generator to output a reference clock corresponding to the current working frequency based on the current working frequency so that the memory module works at the current working frequency based on the reference clock after being electrified.
Preferably, controlling the clock generator to output the reference clock corresponding to the current operating frequency based on the current operating frequency includes:
generating a clock configuration parameter corresponding to the current working frequency based on the current working frequency;
and controlling the clock generator to output a reference clock corresponding to the clock configuration parameter based on the clock configuration parameter.
Preferably, the accelerator card comprises a plurality of working modules and power modules corresponding to the working modules one to one;
after controlling the clock generator to output the reference clock corresponding to the clock configuration parameter based on the clock configuration parameter, the method further includes:
and controlling a plurality of power supply modules to be powered on.
Preferably, controlling the power supply modules to be powered up includes:
acquiring preset power-on time sequences of a plurality of power modules;
and controlling the plurality of power supply modules to be powered on according to the preset power-on time sequence based on the preset power-on time sequence so as to enable the plurality of power supply modules to be powered on and finish the power-on of the accelerator card.
Preferably, after the plurality of power modules are all powered on, the method further includes:
detecting whether the power supplies of the plurality of power supply modules are abnormal in real time;
and if so, controlling the plurality of power supply modules to be powered down.
Preferably, after the plurality of power modules are all powered on, the method further includes:
receiving a control instruction sent by a host end;
and controlling a plurality of working modules of the accelerator card to operate based on the control instruction.
Preferably, the preset working frequencies are N, the working frequency configuration pins are M, N is an integer greater than 1, and N is not greater than 2 to the power of M;
establishing a corresponding relationship between the level state of the working frequency configuration pin and a preset working frequency of the memory module, including:
and establishing a corresponding relation between the combination of the level states of the M working frequency configuration pins and the N preset working frequencies of the memory module.
In order to solve the above technical problem, the present invention further provides an accelerator card power-on initialization apparatus, including:
a memory for storing a computer program;
and the control module is used for realizing the steps of the acceleration card power-on initialization method when the computer program is executed.
Preferably, the method further comprises the following steps:
and the level adjusting module is connected with a working frequency configuration pin of the control module and is used for controlling the working frequency configuration pin to output a level corresponding to the user instruction according to the user instruction.
In order to solve the above technical problem, the present invention further provides an accelerator card, including the above power-on initialization apparatus for an accelerator card.
The application provides a method for initializing the power-on of an accelerator card, in the scheme, by defining a pin of a control module as a working frequency configuration pin and establishing a corresponding relation between the working frequency configuration pin and a preset working frequency, therefore, the preset working frequency can be determined according to the level state of the working frequency configuration pin, at the moment, a user can adjust the preset working frequency of the memory module by adjusting the level state of the working frequency configuration pin, and then the reference clock corresponding to the level state of the working frequency configuration pin adjusted by the user can be output after the accelerator card is powered on, further, the memory module is operated under the corresponding operating frequency, so that the accelerator card comprising the memory module can be applied to scenes with different frequencies, and the clock configuration parameters in the software program do not need to be modified and the burning hardwire does not need to be plugged and unplugged, so that the working frequency modification speed is high and the steps are simple.
The application also provides an accelerator card power-on initialization device and an accelerator card, and the accelerator card power-on initialization device and the accelerator card have the same beneficial effects as the accelerator card power-on initialization method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
Fig. 1 is a schematic flowchart of a power-on initialization method for an accelerator card according to the present invention;
FIG. 2 is a block diagram of an initialization apparatus for power-on of an accelerator card according to the present invention;
fig. 3 is a control schematic diagram of the power-on initialization device for the FPGA accelerator card according to the present invention.
Detailed Description
The core of the invention is to provide an accelerator card power-on initialization method, a device and an accelerator card, which can apply the accelerator card comprising the memory module to scenes with different frequencies, and do not need to modify clock configuration parameters in a software program and plug and unplug a burning hard wire, thereby having higher speed of modifying the working frequency and simple steps.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a schematic flow chart of a power-on initialization method for an accelerator card according to the present invention, where the method is applied to a control module, and includes:
s11: defining a selected pin of a control module as a working frequency configuration pin in advance;
s12: establishing a corresponding relation between the level state of the working frequency configuration pin and the preset working frequency of the memory module;
s13: after the accelerator card is powered on, acquiring the current level state of a working frequency pin, and determining the current working frequency of the memory module based on the current level state and the corresponding relation;
s14: and controlling the clock generator to output a reference clock corresponding to the current working frequency based on the current working frequency so that the memory module works at the current working frequency based on the reference clock after being electrified.
With increasing application requirements, the requirement for flexibility of hardware design of the accelerator card is also increasing, wherein a power supply and a clock are necessary conditions for stable operation of the accelerator card, the accelerator card usually has a strict power-on time sequence, and meanwhile, in order to be capable of adapting the accelerator card to different scenes, initialization needs to be performed when the accelerator card is powered on, but in the prior art, the speed of a clock initialization mode is slow, and the steps are complex.
In order to solve the technical problem, the design idea of the application is as follows: when the accelerator card is powered on, the current working frequency of the memory module preset by a user can be automatically identified, and then the control module of the accelerator card can generate a corresponding reference clock according to the identified current working frequency after being powered on, so that the memory module works at the current working frequency after being powered on, and therefore the user can adjust the preset working frequency to change the working frequency of the memory module, so that the memory module can be applied to application scenes with different frequencies, and the applicability of the accelerator card is improved.
Based on this, the method includes firstly selecting a pin of a control module and defining the pin as a working frequency configuration pin, then establishing a corresponding relation between a level state of the pin and a preset working frequency of a memory module, after the accelerator card is powered on, identifying a current level state of the working frequency configuration pin, and determining a current working frequency corresponding to the current level state after the memory module is powered on according to the corresponding relation, so that the memory module works at the current working frequency after being powered on, and then a user can adjust the working frequency after the memory module is powered on by adjusting the level state of the working frequency configuration pin, so that the accelerator card including the memory module can be applied to application scenes with different frequencies, and the phenomenon that the accelerator card is interrupted or powered on is abnormal due to clock adjustment is avoided, and the applicability of the accelerator card is improved.
It should be noted that, the accelerator card in the present application may be provided with a level adjustment module, configured to adjust a level state of the operating frequency configuration pin according to a user instruction, and a specific implementation of the level adjustment module may be implemented by, but is not limited to, a switch, a pull-up resistor, a pull-down resistor, or a rotary encoder switch.
Specifically, assuming that there are two preset operating frequencies, which are a first operating frequency and a second operating frequency, respectively, and at this time, one pin of the memory module is selected as the operating frequency configuration pin, the function of switching between the first operating frequency and the second operating frequency is realized by switching the high-low level state of the operating frequency configuration pin, for example, the user establishes a correspondence relationship between the level operating state of the operating frequency configuration pin and the operating frequency as follows: first operating frequency-high level, second operating frequency-low level; when the user outputs the high level to the operating frequency configuration pin through the level adjustment module, the memory module works at the first operating frequency after being powered on, and when the user outputs the low level to the operating frequency configuration pin through the level adjustment module, the memory module works at the second operating frequency after being powered on.
It should be noted that, in the present application, the step of defining the selected pin of the control module as the operating frequency configuration pin and the step of establishing the corresponding relationship between the level state of the operating frequency configuration pin and the preset operating frequency of the memory module need only be executed once at the beginning, or the step is executed again when the operating frequency is adjusted according to the actual application requirement, and the two steps do not need to be executed each time.
In summary, in the present application, a user can adjust the current operating frequency of the memory module by adjusting the level state of the operating frequency configuration pin, and then the accelerator card can output the reference clock corresponding to the level state of the operating frequency configuration pin adjusted by the user after being powered on, so that the memory module operates at the corresponding operating frequency, so that the accelerator card including the memory module and the control module is applied to scenes with different frequencies, and the clock configuration parameters in the software program do not need to be modified and the burning hard wire does not need to be plugged and unplugged, so that the speed of modifying the operating frequency is fast and the steps are simple.
On the basis of the above-described embodiment:
as a preferred embodiment, the preset working frequencies are N, the working frequency configuration pins are M, N is an integer greater than 1, and N is not greater than 2 to the power of M;
establishing a corresponding relation between the level state of the working frequency configuration pin and the preset working frequency of the memory module, including:
and establishing a corresponding relation between the combination of the level states of the M working frequency configuration pins and the N preset working frequencies.
Considering that the memory module can work in a scene corresponding to multiple operating frequency modes, for example, DDR4(Double Data Rate) is divided into four operating frequency modes of 2133Mbps, 2400Mbps, 2666Mbps, and 3200Mbps, of course, the memory module may also define the memory module as other operating frequency modes according to practical applications, and when one pin of the control module is selected and defined as an operating frequency configuration pin, the requirement of adjusting multiple operating frequencies cannot be met.
In order to solve the above technical problem, in the present application, a plurality of pins of the control module are defined as operating frequency configuration pins, where the number N of preset operating frequencies of the memory module is not greater than 2 to the M-th power, and at this time, the combinations of the level states of the M operating frequency configuration pins are respectively in one-to-one correspondence with a plurality of preset operating frequencies to establish a corresponding relationship, so as to implement adjustment of a plurality of operating frequencies of the memory module.
For example, when N is 16, M is not less than 4, when a user sets the level state combination of the 4 operating frequency configuration pins to 0000 through the level adjustment module, the memory module operates at the first operating frequency after being powered on; when the level state combination of the 4 working frequency configuration pins is set to 0001, the memory module works at the second working frequency corresponding to the second preset working frequency after being powered on, and so on, when the level state combination of the 4 working frequency configuration pins is set to 1111, the memory module works at the sixteenth preset working frequency corresponding to the sixteenth preset working frequency after being powered on. At this time, the level adjustment module may include a plurality of rotary encoder switch combinations, the rotary encoder switch combinations correspond to the sixteen operating frequencies one by one, and may also be combinations of other switches, which is not limited herein.
Of course, the specific implementation of the present application is not limited to the above examples, and the present application is not particularly limited herein.
In summary, in the present application, the plurality of pins of the control module are defined as the operating frequency configuration pins, and then the combined level state of the plurality of operating frequency configuration pins can be adjusted, so that the memory module can operate at a plurality of different operating frequencies after being powered on, thereby further improving the applicability of the accelerator card.
As a preferred embodiment, controlling the clock generator to output the reference clock corresponding to the current operating frequency based on the current operating frequency includes:
generating a clock configuration parameter corresponding to the current working frequency based on the current working frequency;
and controlling the clock generator to output a reference clock corresponding to the clock configuration parameter based on the clock configuration parameter.
Specifically, after the current working frequency of the memory module is identified through the working frequency configuration pin, the constant parameter is adjusted to be the clock configuration parameter corresponding to the current working frequency, and then the clock configuration parameter is sent to the clock generator inside the accelerator card, so that the clock generator outputs the reference clock corresponding to the clock configuration parameter, and the memory module works at the working frequency corresponding to the reference clock after being powered on.
It should be noted that, the control module 1 in this application includes a clock configuration unit 12, where the clock configuration unit 12 is connected to the clock generator through an I2C (Inter-Integrated Circuit) interface, specifically, the clock configuration unit 12 is configured to identify a level state of an operating frequency configuration pin, generate a clock configuration parameter corresponding to the level state, output the clock configuration parameter to the clock generator through an I2C interface, and output a reference clock corresponding to the clock configuration parameter to the controller portion of the memory module after the clock generator is reset.
Therefore, through the specific implementation mode, the memory module can be configured with the reference clock corresponding to the level state of the working frequency configuration pin, so that the memory module works at the working frequency corresponding to the reference clock after being electrified, and the implementation mode is simple and reliable.
As a preferred embodiment, the accelerator card includes a plurality of working modules and power modules corresponding to the plurality of working modules one to one;
after controlling the clock generator to output the reference clock corresponding to the clock configuration parameter based on the clock configuration parameter, the method further includes:
and controlling the plurality of power supply modules to be powered on.
The embodiments of the present application aim to provide a specific step of power-on initialization of an accelerator card, specifically, after the accelerator card is powered on, a reference clock of a memory module is initialized first, and after the initialization is completed, power modules corresponding to respective working modules in the accelerator card are controlled to be powered on, so that the accelerator card starts to work normally after the power modules are powered on.
As a preferred embodiment, controlling the power-on of a plurality of power modules includes:
acquiring preset power-on time sequences of a plurality of power modules;
and controlling the plurality of power supply modules to be powered on according to a preset power-on time sequence based on the preset power-on time sequence so as to enable the plurality of power supply modules to be powered on and finish the power-on of the accelerator card.
Specifically, when the accelerator card includes a plurality of operating modules, it is considered that when the plurality of operating modules are powered on simultaneously, there may be a certain inrush current, which may damage one or some operating modules or power supply modules in the accelerator card.
In order to solve the technical problem, in the present application, when a plurality of power modules are controlled to be powered on, a preset power-on time sequence set in advance by a user is obtained first, and then the plurality of power modules complete power-on according to the preset power-on time sequence.
Specifically, the control module 1 includes a timing control unit 11, in this application, a manner of controlling the power-on of the plurality of power modules may be to enable the power module of the previous stage, so that the power module of the previous stage completes power-on, and feed back a signal of completing power-on to the timing control unit 11, after the unit receives the signal of completing power-on of the power module of the previous stage, perform logic judgment to output an enable signal of the power module of the next stage, so that the power module corresponding to the power module completes power-on, and so on, until all the power modules complete power-on.
It should be noted that the number of each stage of power modules in the present application may be one, or may be multiple, and the present application is not limited herein, as long as it can ensure that the inrush current value corresponding to the multiple power modules being powered on at the same time is within the tolerable range of the accelerator card.
In addition, when a plurality of power modules are provided in the present application, the manner of controlling the power-on of the plurality of power modules may also be to control the power modules of each stage to be turned on in a staggered manner with different delay times, for example, after the power modules receive a power-on signal, the power module of the first stage is powered on immediately, the power module of the second stage is powered on in a delayed manner for 1 second, the power module of the third stage is powered on in a delayed manner for 2 seconds, and so on, until all the power modules are powered on, of course, the specific implementation manner of the power module power-on is not limited to the above example, and the present application is not limited thereto.
In summary, the mode of controlling the power-on of the plurality of power modules in the application can ensure the power-on safety and reliability of the power modules, and further improve the initialization safety of the accelerator card.
As a preferred embodiment, after the plurality of power modules are powered on, the method further includes:
detecting whether the power supplies of the plurality of power supply modules are abnormal in real time;
and if so, controlling the plurality of power supply modules to be powered down.
In consideration of the fact that after all the power modules are powered on, there may be abnormality of the power modules, or abnormality of the power supplies, or abnormality of the output power supplies of the power modules due to abnormality of circuits inside the working modules, and at this time, damage of the power modules or damage of the corresponding working modules may be caused.
In order to solve the technical problem, if the power module of a certain level is abnormal, all the power modules are controlled to be powered off, so that the safety of the accelerator card in the live state is improved as much as possible.
It should be noted that the anomaly in the present application may include, but is not limited to, a combination of one or more of an over-voltage, an over-current, an under-voltage, and an under-current, and the present application is not limited thereto.
Therefore, the mode of detecting the power supply in real time can further ensure the electrification safety of the accelerator card and prevent the power supply module or the corresponding working module from being damaged.
As a preferred embodiment, after the plurality of power modules are powered on, the method further includes:
receiving a control instruction sent by a host end;
and controlling a plurality of working modules of the accelerator card to operate based on the control instruction.
Specifically, the control module 1 includes an out-of-band management unit 13, which is used to receive a control instruction from a host, so as to ensure safe and reliable operation of the accelerator card. In addition, after the power modules are powered on, the out-of-band management unit 13 is further configured to acquire an operating state of the accelerator card in real time, and send the operating state to the host through an independent channel, so as to implement information interaction between the accelerator card and the host, where the operating state of the accelerator card includes one or a combination of more of factory information, a voltage state, a current state, a power state, a temperature state, and an alarm state of the memory module and the accelerator card, and this application is not limited herein. Then, the host generates a control command according to the received operation state to control the safe and reliable operation of the accelerator card,
Referring to fig. 2, fig. 2 is a block diagram of a power-on initialization apparatus for an accelerator card according to the present invention, the apparatus includes:
a memory 2 for storing a computer program;
the control module 1 is configured to implement the steps of the above-mentioned accelerator card power-on initialization method when executing a computer program.
When the accelerator card is an FPGA (Field Programmable Gate Array), please refer to fig. 3, and fig. 3 is a control schematic diagram of the power-on initialization device of the FPGA accelerator card provided by the present invention. The control module 1 may include, but is not limited to, a timing control unit 11, a clock configuration unit 12, and an out-of-band management unit 13, which are respectively connected to each power module, a clock generator, a detection accelerator card, and each sensor of the memory module through a communication interface, where the timing control unit 11 is configured to control each power module to be sequentially powered on according to a correct power-on timing sequence, and the power module may include, but is not limited to, a power module of a main chip FPGA and other auxiliary circuits in addition to the power module of each memory module; the clock configuration unit 12 is configured to identify a preset operating frequency and output a corresponding clock configuration parameter to the clock generator; the out-of-band management unit 13 is configured to receive detection results of the sensors, implement information interaction with the host through an independent channel according to the detection results, and control safe and reliable operations of the accelerator card and the memory module through a control instruction of the host, where the control instruction may be, but is not limited to, controlling a power module of the accelerator card to be powered off.
As a preferred embodiment, the method further comprises the following steps:
and the level adjusting module is connected with the working frequency configuration pin of the control module and is used for controlling the working frequency configuration pin to output a level corresponding to the user instruction according to the user instruction.
Specifically, the level adjustment module connected to the operating frequency configuration pin of the control module is provided in the application, and the operating frequency configuration pin is controlled according to the user instruction to output a level corresponding to the user instruction. At this time, the user can adjust the level state of the working frequency configuration pin through the level adjustment module to adjust the working frequency of the memory module after being powered on, so that the accelerator card can be applied to application scenes with different frequencies.
The specific implementation of the level adjustment module may be, but is not limited to, implemented by a switch or a pull-up and pull-down resistor, or a rotary encoder switch, etc., and the present application is not limited thereto, and when the preset operating frequency is N and the operating frequency configuration pins are M, the level adjustment module may include a plurality of rotary encoder switch combinations, and the combined result corresponds to the N preset operating frequencies one-to-one, respectively, or may be a combination of other switches.
For other descriptions of the accelerator card power-on initialization device provided in the present application, please refer to the above embodiments, which are not described herein again.
An accelerator card comprises the above accelerator card power-on initialization device.
For the description of the accelerator card provided in the present application, please refer to the above embodiments, which are not described herein again.
The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
1. A power-on initialization method for an accelerator card is applied to a control module and is characterized by comprising the following steps:
defining a selected pin of the control module as a working frequency configuration pin in advance;
establishing a corresponding relation between the level state of the working frequency configuration pin and a preset working frequency of a memory module;
after the accelerator card is powered on, acquiring the current level state of the working frequency pin, and determining the current working frequency of the memory module based on the current level state and the corresponding relation;
and controlling a clock generator to output a reference clock corresponding to the current working frequency based on the current working frequency so that the memory module works at the current working frequency based on the reference clock after being electrified.
2. The accelerator card power-on initialization method according to claim 1, wherein controlling a clock generator to output a reference clock corresponding to the current operating frequency based on the current operating frequency comprises:
generating a clock configuration parameter corresponding to the current working frequency based on the current working frequency;
and controlling the clock generator to output a reference clock corresponding to the clock configuration parameter based on the clock configuration parameter.
3. The power-on initialization method for an accelerator card according to claim 1, wherein the accelerator card includes a plurality of working modules and power modules corresponding to the plurality of working modules one to one;
after controlling the clock generator to output the reference clock corresponding to the clock configuration parameter based on the clock configuration parameter, the method further includes:
and controlling a plurality of power supply modules to be powered on.
4. The power-on initialization method for an accelerator card according to claim 3, wherein controlling a plurality of power modules to be powered on comprises:
acquiring preset power-on time sequences of a plurality of power modules;
and controlling the plurality of power supply modules to be powered on according to the preset power-on time sequence based on the preset power-on time sequence so as to enable the plurality of power supply modules to be powered on and finish the power-on of the accelerator card.
5. The power-on initialization method for an accelerator card according to claim 4, wherein after the plurality of power modules are all powered on, the method further comprises:
detecting whether the plurality of power supply modules are abnormal in real time;
and if so, controlling the plurality of power supply modules to be powered down.
6. The power-on initialization method for an accelerator card according to claim 3, wherein after each of the plurality of power modules is powered on, the method further comprises:
receiving a control instruction sent by a host end;
and controlling a plurality of working modules of the accelerator card to operate based on the control instruction.
7. The accelerator card power-on initialization method according to any one of claims 1 to 6, wherein the preset operating frequency is N, the operating frequency configuration pins are M, N is an integer greater than 1, and N is not greater than 2 to the power of M;
establishing a corresponding relationship between the level state of the working frequency configuration pin and a preset working frequency of the memory module, including:
and establishing a corresponding relation between the combination of the level states of the M working frequency configuration pins and the N preset working frequencies of the memory module.
8. An accelerator card power-on initialization device, comprising:
a memory for storing a computer program;
a control module for implementing the steps of the accelerator card power-on initialization method according to any one of claims 1 to 7 when executing said computer program.
9. The accelerator-card power-on initialization apparatus according to claim 8, further comprising:
and the level adjusting module is connected with a working frequency configuration pin of the control module and is used for controlling the working frequency configuration pin to output a level corresponding to the user instruction according to the user instruction.
10. An accelerator card comprising the accelerator card power-on initialization apparatus according to any one of claims 8 to 9.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110342293.1A CN113076141A (en) | 2021-03-30 | 2021-03-30 | Acceleration card power-on initialization method and device and acceleration card |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110342293.1A CN113076141A (en) | 2021-03-30 | 2021-03-30 | Acceleration card power-on initialization method and device and acceleration card |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113076141A true CN113076141A (en) | 2021-07-06 |
Family
ID=76611974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110342293.1A Pending CN113076141A (en) | 2021-03-30 | 2021-03-30 | Acceleration card power-on initialization method and device and acceleration card |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113076141A (en) |
Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090210687A1 (en) * | 2008-02-18 | 2009-08-20 | Ming-Lung Lee | Computer motherboard |
| CN102073504A (en) * | 2011-01-21 | 2011-05-25 | 深圳创维数字技术股份有限公司 | Multi-scene operating method, multi-scene operating system and intelligent device |
| CN102640078A (en) * | 2009-11-13 | 2012-08-15 | 马维尔国际贸易有限公司 | Clock turn-on strategy for power management |
| CN103593235A (en) * | 2013-11-01 | 2014-02-19 | 浪潮电子信息产业股份有限公司 | Internal-memory active protection method based on software implementation |
| CN107346170A (en) * | 2017-07-20 | 2017-11-14 | 郑州云海信息技术有限公司 | A kind of FPGA Heterogeneous Computings acceleration system and method |
| CN109062715A (en) * | 2018-07-05 | 2018-12-21 | Oppo（重庆）智能科技有限公司 | The determination method, apparatus and terminal of memory clock frequency |
| CN110265075A (en) * | 2018-03-12 | 2019-09-20 | 龙芯中科技术有限公司 | A kind of control method and system of memory interface |
| CN111324196A (en) * | 2020-02-03 | 2020-06-23 | Oppo广东移动通信有限公司 | Memory operation frequency adjusting method and device, storage medium and electronic equipment |
| CN111857308A (en) * | 2019-04-26 | 2020-10-30 | 鸿富锦精密电子(天津)有限公司 | Server power management method and system |
-
2021
- 2021-03-30 CN CN202110342293.1A patent/CN113076141A/en active Pending
Patent Citations (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090210687A1 (en) * | 2008-02-18 | 2009-08-20 | Ming-Lung Lee | Computer motherboard |
| CN102640078A (en) * | 2009-11-13 | 2012-08-15 | 马维尔国际贸易有限公司 | Clock turn-on strategy for power management |
| CN102073504A (en) * | 2011-01-21 | 2011-05-25 | 深圳创维数字技术股份有限公司 | Multi-scene operating method, multi-scene operating system and intelligent device |
| CN103593235A (en) * | 2013-11-01 | 2014-02-19 | 浪潮电子信息产业股份有限公司 | Internal-memory active protection method based on software implementation |
| CN107346170A (en) * | 2017-07-20 | 2017-11-14 | 郑州云海信息技术有限公司 | A kind of FPGA Heterogeneous Computings acceleration system and method |
| CN110265075A (en) * | 2018-03-12 | 2019-09-20 | 龙芯中科技术有限公司 | A kind of control method and system of memory interface |
| CN109062715A (en) * | 2018-07-05 | 2018-12-21 | Oppo（重庆）智能科技有限公司 | The determination method, apparatus and terminal of memory clock frequency |
| CN111857308A (en) * | 2019-04-26 | 2020-10-30 | 鸿富锦精密电子(天津)有限公司 | Server power management method and system |
| CN111324196A (en) * | 2020-02-03 | 2020-06-23 | Oppo广东移动通信有限公司 | Memory operation frequency adjusting method and device, storage medium and electronic equipment |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US7566987B2 (en) | Method of powering up a plurality of loads in sequence | |
| WO2019113732A1 (en) | Electronic device and charging control method | |
| CN111697663A (en) | Charging circuit and charging cable | |
| CN104578277B (en) | For the method for charging for electronic equipment and electronic equipment | |
| US7741732B2 (en) | Method of configuring a startup sequence of a load control system | |
| US7781919B2 (en) | Method of controlling a load control module as part of a startup sequence | |
| KR101604014B1 (en) | Autonomous multi-device event synchronization and sequencing technique eliminating master and slave assignments | |
| CN105098718B (en) | Power supply device and over-voltage protection method | |
| CN104467109A (en) | Method for supplying power to electronic equipment and electronic equipment | |
| CN103237189A (en) | Electronic equipment, MHL (mobile high-definition link) connector, MHL system and connector detection method | |
| CN103983894A (en) | Jack detector and jack detecting method | |
| CN102033502B (en) | Programmable controller | |
| CN111103827B (en) | Server working mode switching device | |
| CN104836209A (en) | Digital power supply protection circuit and apparatus | |
| CN104485712A (en) | Charging method and electronic equipment | |
| CN113076141A (en) | Acceleration card power-on initialization method and device and acceleration card | |
| US20110313700A1 (en) | Voltage detection system and controlling method of the same | |
| CN110459260B (en) | Automatic test switching device, method and system | |
| US4320386A (en) | Selection and power reset circuit | |
| CN109375089A (en) | A kind of switching method and apparatus of power supply | |
| CN104467395A (en) | Hot-plug power source system and power source control device and method | |
| CN111245273B (en) | Power frequency synchronization circuit for parallel operation of inverters and power frequency synchronization method for parallel operation of multiple inverters | |
| JP4280544B2 (en) | Electronic circuit configuration or electronic circuit | |
| CN113568340A (en) | Switch control method, device, electronic equipment and storage medium | |
| CN110209546A (en) | A kind of apparatus control method and apparatus control system |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20210706 |
|
| RJ01 | Rejection of invention patent application after publication |