CN111245273B - Power frequency synchronization circuit for parallel operation of inverters and power frequency synchronization method for parallel operation of multiple inverters - Google Patents
Power frequency synchronization circuit for parallel operation of inverters and power frequency synchronization method for parallel operation of multiple inverters Download PDFInfo
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- CN111245273B CN111245273B CN201911416338.4A CN201911416338A CN111245273B CN 111245273 B CN111245273 B CN 111245273B CN 201911416338 A CN201911416338 A CN 201911416338A CN 111245273 B CN111245273 B CN 111245273B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/493—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode the static converters being arranged for operation in parallel
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0012—Control circuits using digital or numerical techniques
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Abstract
The invention discloses an inverter parallel operation frequency synchronization circuit and a multi-inverter parallel operation frequency synchronization method, wherein the circuit comprises the following components: the system comprises a DSP module, a state output module, a state input module, a clock output module, a clock input module and a clock synchronization bus; wherein the clock synchronization bus comprises a status bus and a clock bus; the state output pin and the state input pin of the DSP module are respectively connected with a state bus through the state output module and the state input module; the DSP module clock output pin and the clock input pin are respectively connected with a clock bus through the clock output module and the clock input module; the DSP module detects whether a low-level signal exists on a state bus through a state input module; if so, judging that the host is present, detecting the clock signal of the host on the clock bus through the clock input module, regulating the clock signal output by the inverter to be consistent with the clock signal on the clock bus through the DSP module, and outputting the clock signal to the clock bus through the clock output module.
Description
Technical Field
The invention relates to the technical field of parallel operation of inverters, in particular to an inverter parallel operation frequency synchronization circuit and a power frequency synchronization method of multi-inverter parallel operation.
Background
In the conventional inverter parallel operation method, an inverter is required to be used as a host, a master-slave machine is required to be strictly distinguished in the parallel operation process, a host is required to be determined in the synchronization process, only the host in the parallel system sends out a synchronization signal, if the host fails, other inverters in the parallel system lose the synchronization signal, and the reliability of the system is low.
Disclosure of Invention
The invention mainly aims to provide an inverter parallel operation frequency synchronization circuit and a multi-inverter parallel operation frequency synchronization method, which aim to solve the problem that synchronous hosts need to be strictly distinguished in the system.
In order to achieve the above object, the present invention provides an inverter parallel operation frequency synchronization circuit, which includes:
the DSP module is used for sending out a first state signal of the inverter and receiving a second state signal on the state bus; and, for generating and issuing a first clock signal and receiving a second clock signal on the clock bus; when the DSP module detects that the second state signal has a preset level signal, the first clock signal is adjusted to be consistent with the second clock signal; when the DSP module detects that the second state signal does not have a preset level signal, the host is preempted to become a synchronous host;
the state output module is used for amplifying the first state signal and then sending the amplified first state signal to the state bus;
the state input module is used for amplifying the second state signal and then sending the second state signal to the DSP module;
the clock output module is used for amplifying the first clock signal and then sending the amplified first clock signal to the clock bus;
and the clock input module is used for amplifying the second clock signal and then sending the amplified second clock signal to the DSP module.
Further, the DSP module further comprises a PWM module;
the PWM module is used for generating a preset first state signal and a first clock signal.
Further, the state output module includes: resistor R1, resistor R2, resistor R3, triode Q1, diode D1 and first input source;
one end of the resistor R1 is connected with the state output pin of the DSP module, and the other end of the resistor R1 is connected with one end of the resistor R2 and the base electrode of the triode Q1; the other end of the resistor R2 and the emitter grounding pin of the triode Q1;
the collector electrode of the triode Q1 is connected with one end of the resistor R3 and the anode of the diode D1; the other end of the resistor R3 is connected with a first input source; the cathode of the diode D1 is connected with the state bus.
Further, the status input module includes: resistor R5, resistor R6, resistor R7, triode Q2, diode D2 and a second input source;
one end of the resistor R5 is connected with the state input pin of the DSP module, and the other end of the resistor R6 is connected with one end of the resistor R6 and the collector electrode of the triode Q2; the other end of the resistor R6 is connected with a second input source;
the base electrode of the triode Q2 is connected with one end of the resistor R7 and the cathode of the diode D2; the other end of the resistor R7 and the emitter grounding pin of the triode Q2; the anode of the diode D2 is connected with the status bus.
Further, the clock output module includes: resistor R9, resistor R10, resistor R11, triode Q3, diode D3 and third input source;
one end of the resistor R9 is connected with the clock output pin of the DSP module, and the other end of the resistor R9 is connected with one end of the resistor R10 and the base electrode of the triode Q3; the other end of the resistor R10 and the emitter grounding pin of the triode Q3;
the collector electrode of the triode Q3 is connected with one end of the resistor R11 and the anode of the diode D3; the other end of the resistor R11 is connected with a third input source; the cathode of the diode D3 is connected with the clock bus.
Further, the clock input module includes: resistor R13, resistor R14, resistor R15, transistor Q4, diode D4, and a fourth input source;
one end of the resistor R13 is connected with a clock input pin of the DSP module, and the other end of the resistor R14 is connected with one end of the resistor R14 and a collector electrode of the triode Q4; the other end of the resistor R14 is connected with a fourth input source;
the base electrode of the triode Q4 is connected with one end of the resistor R15 and the cathode of the diode D4; the other end of the resistor R15 and the emitter grounding pin of the triode Q4; the positive electrode of the diode D4 is connected with a clock bus.
The invention also provides a power frequency synchronization method for parallel operation of multiple inverters, which is based on any one of the circuits, and comprises the following steps:
the DSP module generates a first state signal and a first clock signal, outputs the first state signal to the state bus through the state output module, and outputs the first clock signal to the clock bus through the clock output module;
receiving a second state signal on a state bus through a state input module, and detecting whether the second state signal has a preset level signal or not; receiving a second clock signal on the clock bus through the clock input module;
and if the second state signal has the preset level signal, adjusting the first clock signal to be consistent with the second clock signal in phase.
Further, the pass state input module receives a second state signal on a state bus and detects whether the second state signal has a preset level signal or not; after the step of receiving, by the clock input module, the second clock signal on the clock bus, the method further comprises:
and if the second state signal does not have the preset level signal, the state output pin is adjusted to output the preset level signal, and the first clock signal is output to the clock bus to become a host.
Further, the step of adjusting the first clock signal to be consistent with the second clock signal, if any, includes:
if the second state signal is detected to have a preset level signal, judging that a host is on the state bus, and entering into interruption and waiting for n period times, wherein n is a natural number;
controlling the state output pin to output high level at the moment of rising edge or falling edge of the first state signal after waiting for finishing; the method comprises the steps that a second clock signal on a clock bus is obtained through a clock input module, the time difference T between the preset phase of a first clock signal and the preset phase of the second clock signal is captured, the first clock signal is controlled to enter into interruption, the first clock signal is output to the clock bus after the time of T-T, synchronization is completed, and the state output pin is arranged at a preset position; where T is the period of the clock signal.
Further, if the second status signal has no preset level signal, the step of adjusting the status output pin to output the preset level signal and outputting a second clock signal to a clock bus to become a host includes:
if the second state signal is detected to have no preset level signal, judging that the state bus has no host, controlling the first state signal to enter a state of being interrupted to the rising edge or the falling edge of the next first state signal, placing the state output pin at a preset position, outputting a second clock signal to a clock bus, adjusting the output of the inverter to be at a preset frequency to become the host, and ending the synchronous flow.
The invention discloses an inverter parallel operation frequency synchronization circuit, which comprises: the system comprises a DSP module, a state output module, a state input module, a clock output module, a clock input module and a clock synchronization bus; wherein the clock synchronization bus comprises a status bus and a clock bus; the state output pin and the state input pin of the DSP module are respectively connected with a state bus through the state output module and the state input module; the DSP module clock output pin and the clock input pin are respectively connected with a clock bus through the clock output module and the clock input module; the DSP module detects whether a low-level signal exists on a state bus through a state input module; if so, judging that the host exists, detecting the clock signal of the host on the clock bus through the clock input module, adjusting the clock signal to be consistent with the clock signal of the host on the clock bus through the DSP module, and outputting the clock signal to the clock bus through the clock output module. According to the invention, the identical clock synchronization circuits are built in the inverters, so that the master-slave relation is not strictly distinguished, the master-slave relation exists only in the stage before the power frequency synchronization, the clock synchronization control method of each inverter is identical, one inverter fails or is withdrawn, or the inverter is added in the normal use process, and no influence is caused on other inverters.
Drawings
FIG. 1 is a schematic block diagram of an inverter parallel operation frequency synchronization circuit according to an embodiment of the present application;
fig. 2 is a schematic diagram of an inverter parallel operation frequency synchronization circuit according to an embodiment of the present disclosure;
FIG. 3 is a schematic flow chart of a power frequency synchronization method for parallel operation of multiple inverters according to an embodiment of the present application;
fig. 4 is a flow chart of a power frequency synchronization method of parallel operation of multiple inverters according to another embodiment of the present application.
The achievement of the objects, functional features and advantages of the present invention will be further described with reference to the accompanying drawings, in conjunction with the embodiments.
Detailed Description
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the invention.
In the several embodiments provided in the present application, it should be understood that the disclosed systems, apparatuses, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other forms.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.
Those of ordinary skill in the art will appreciate that all or a portion of the steps in implementing the methods of the above embodiments may be implemented by a program to instruct related hardware, where the program may be stored in a computer readable storage medium, where the storage medium may be a read only memory, a magnetic disk, etc.
Referring to fig. 1, the invention proposes an inverter parallel operation frequency synchronization circuit, comprising:
the DSP module 1 is used for sending a first state signal of the inverter and receiving a second state signal on the state bus; and, for generating and issuing a first clock signal and receiving a second clock signal on the clock bus; when the DSP module 1 detects that the second state signal has a preset level signal, the first clock signal is adjusted to be consistent with the second clock signal; when the DSP module 1 detects that the second state signal does not have a preset level signal, the host is preempted to become a synchronous host;
the state output module 2 is used for amplifying the first state signal and then sending the amplified first state signal to the state bus;
the state input module 3 is configured to amplify the second state signal and send the amplified second state signal to the DSP module 1;
the clock output module 4 is used for amplifying the first clock signal and then sending the amplified first clock signal to the clock bus;
and the clock input module 5 is used for amplifying the second clock signal and then sending the second clock signal to the DSP module 1.
In this embodiment, the status bus refers to Sync1 in the figure, and the clock bus refers to Sync2. The first clock signal refers to a power frequency synchronous clock signal sent by the DSP module 1, and the second clock signal refers to a power frequency synchronous clock signal on the clock bus. The DSP module 1 is a digital signal processor, and performs processes such as acquisition, transformation, filtering, estimation, enhancement, compression, and recognition on signals in digital form. The clock synchronization bus further includes: ground GND; the power frequency synchronous grounding bus is used for connecting the grounding pins of the power frequency synchronous circuits of all the inverters together so that the power frequency synchronous circuits are commonly grounded, and if the power frequency synchronous grounding bus is not commonly grounded, the inverters are in a floating state for other inverters. For example, if the transistor Q1 of the inverter 1 is turned on, the potential of R4 is 0 for the inverter 1 and is transferred to the inverter 2 through the status bus, but this signal is not necessarily 0V for the inverter 2 due to floating ground, possibly 5V or other, which eventually results in abnormal signals of the status bus, as shown in fig. 2. The above-mentioned abnormal situation is avoided in common. In this embodiment, by detecting a signal on the status bus, it is determined to preempt the host bit or synchronize according to the signal on the clock bus according to the detection result. The above-mentioned preempting host position becomes the process of the synchronous host computer, after other inverters finish synchronizing, become the host computer, can have a plurality of host computers to coexist, become the inverter of the host computer, has stated that has finished the synchronous process.
In one embodiment, the DSP module 1 further comprises a PWM module;
the PWM module is used for generating a preset first state signal and a first clock signal.
In the present embodiment, the PWM (pulse width modulation ) is a technique of controlling an analog circuit by using a digital output of a microprocessor, and the PWM module is a part of the DSP module 1.
Referring to fig. 2, in one embodiment, the status output module 2 includes: resistor R1, resistor R2, resistor R3, triode Q1, diode D1 and first input source;
one end of the resistor R1 is connected with the state output pin of the DSP module 1, and the other end of the resistor R2 is connected with one end of the resistor R2 and the base electrode of the triode Q1; the other end of the resistor R2 and the emitter grounding pin of the triode Q1;
the collector electrode of the triode Q1 is connected with one end of the resistor R3 and the anode of the diode D1; the other end of the resistor R3 is connected with a first input source; the cathode of the diode D1 is connected with the state bus.
In this embodiment, the status output module 2 may further include: a resistor R4 and a capacitor C1; the resistor R4 is used for limiting the magnitude of the branch current so as to prevent the components connected in series from being burnt out due to overlarge current, and mainly plays a role in protecting the diode D1, and meanwhile, the current-limiting resistor can also play a role in dividing voltage; the capacitor C1 is used for smoothing direct current input or output, and can absorb current fluctuation generated in the working process of the electronic circuit and interference caused by serial connection of an alternating current power supply, so that the working performance of the electronic circuit is more stable. Specifically, after the resistor R4 and the capacitor C1 are added, the circuit connection relationship is as follows:
one end of the resistor R1 is connected with the first output pin of the DSP module 1, and the other end of the resistor R1 is connected with one end of the resistor R2, the anode of the capacitor C1 and the base electrode of the triode Q1; the other end of the resistor R2, the negative electrode of the capacitor C1 and the grounded pin of the emitter electrode of the triode Q1;
the collector of the triode Q1 is connected with one end of a resistor R3 and one end of a resistor R4; the other end of the resistor R3 is connected with a first input source; the other end of the resistor R4 is connected with the anode of the diode D1; the cathode of the diode D1 is connected to the status bus.
In one embodiment, the status input module 3 includes: resistor R5, resistor R6, resistor R7, triode Q2, diode D2 and a second input source;
one end of the resistor R5 is connected with the state input pin of the DSP module 1, and the other end of the resistor R6 is connected with one end of the resistor R6 and the collector electrode of the triode Q2; the other end of the resistor R6 is connected with a second input source;
the base electrode of the triode Q2 is connected with one end of the resistor R7 and the cathode of the diode D2; the other end of the resistor R7 and the emitter grounding pin of the triode Q2; the anode of the diode D2 is connected with the status bus.
In this embodiment, the status input module 3 may further include: resistor R8 and capacitor C2; the resistor R8 is used for limiting the magnitude of the branch current so as to prevent the components connected in series from being burnt out due to overlarge current, and mainly plays a role in protecting the diode D2, and meanwhile, the current-limiting resistor can also play a role in dividing voltage; the capacitor C2 is used for smoothing direct current input or output, and can absorb current fluctuation generated in the working process of the electronic circuit and interference caused by the serial connection of an alternating current power supply, so that the working performance of the electronic circuit is more stable. Specifically, after the resistor R8 and the capacitor C2 are added, the circuit connection relationship is as follows:
one end of the resistor R5 is connected with the first input pin of the DSP module 1, and the other end of the resistor R6 is connected with one end of the resistor and the collector electrode of the triode Q2; the other end of the resistor R6 is connected with a second input source;
the base electrode of the triode Q2 is connected with the anode of the capacitor C2, one end of the resistor R7 and one end of the resistor R8; the other end of the resistor R7, the negative electrode of the capacitor C2 and the grounded pin of the emitter electrode of the triode Q2; the other end of the resistor R8 is connected with the cathode of the diode D2; the anode of diode D2 is connected to the status bus.
In one embodiment, the clock output module 4 includes: resistor R9, resistor R10, resistor R11, triode Q3, diode D3 and third input source;
one end of the resistor R9 is connected with the clock output pin of the DSP module 1, and the other end of the resistor R9 is connected with one end of the resistor R10 and the base electrode of the triode Q3; the other end of the resistor R10 and the emitter grounding pin of the triode Q3;
the collector electrode of the triode Q3 is connected with one end of the resistor R11 and the anode of the diode D3; the other end of the resistor R11 is connected with a third input source; the cathode of the diode D3 is connected with the clock bus.
In this embodiment, the clock output module 4 may further include: a resistor R12 and a capacitor C3; the resistor R12 is used for limiting the magnitude of the branch current so as to prevent the components connected in series from being burnt out due to overlarge current, and mainly plays a role in protecting the diode D3, and meanwhile, the current-limiting resistor can also play a role in dividing voltage; the capacitor C3 is used for smoothing direct current input or output, and can absorb current fluctuation generated in the working process of the electronic circuit and interference caused by the serial connection of an alternating current power supply, so that the working performance of the electronic circuit is more stable. Specifically, after the resistor R12 and the capacitor C3 are added, the circuit connection relationship is as follows:
one end of the resistor R9 is connected with the second output pin of the DSP module 1, and the other end of the resistor R9 is connected with one end of the resistor R10, the anode of the capacitor C3 and the base electrode of the triode Q3; the other end of the resistor R10, the negative electrode of the capacitor C3 and the grounded pin of the emitter electrode of the triode Q3;
the collector of the triode Q3 is connected with one end of a resistor R11 and one end of a resistor R12; the other end of the resistor R11 is connected with a third input source; the other end of the resistor R12 is connected with the anode of the diode D3; the cathode of the diode D3 is connected to the status bus.
In one embodiment, the clock input module 5 includes: resistor R13, resistor R14, resistor R15, transistor Q4, diode D4, and a fourth input source;
one end of the resistor R13 is connected with the clock input pin of the DSP module 1, and the other end of the resistor R14 is connected with one end of the resistor R14 and the collector electrode of the triode Q4; the other end of the resistor R14 is connected with a fourth input source;
the base electrode of the triode Q4 is connected with one end of the resistor R15 and the cathode of the diode D4; the other end of the resistor R15 and the emitter grounding pin of the triode Q4; the positive electrode of the diode D4 is connected with a clock bus.
In this embodiment, the clock input module 5 may further include: resistor R16 and capacitor C4; the resistor R16 is used for limiting the magnitude of the branch current so as to prevent the components connected in series from being burnt out due to overlarge current, and mainly plays a role in protecting the diode D4, and meanwhile, the current-limiting resistor can also play a role in dividing voltage; the capacitor C4 is used for smoothing direct current input or output, and can absorb current fluctuation generated in the working process of the electronic circuit and interference caused by the serial connection of an alternating current power supply, so that the working performance of the electronic circuit is more stable. Specifically, after the resistor R16 and the capacitor C4 are added, the circuit connection relationship is as follows:
one end of the resistor R13 is connected with the second input pin of the DSP module 1, and the other end of the resistor R14 is connected with one end of the resistor R14 and the collector electrode of the triode Q4; the other end of the resistor R14 is connected with a fourth input source;
the base electrode of the triode Q4 is connected with the anode of the capacitor C4, one end of the resistor R15 and one end of the resistor R16; the other end of the resistor R15, the negative electrode of the capacitor C4 and the grounded pin of the emitter electrode of the triode Q4; the other end of the resistor R16 is connected with the cathode of the diode D4; the anode of the diode D4 is connected to the status bus and the output of the status output module 2.
Referring to fig. 3, the invention also provides a power frequency synchronization method for parallel operation of multiple inverters, based on any one of the circuits, the method comprises the following steps:
s1, a DSP module 1 generates a first state signal and a first clock signal, the first state signal is output to a state bus through a state output module 2, and the first clock signal is output to a clock bus through a clock output module 4;
s2, receiving a second state signal on a state bus through a state input module 3, and detecting whether the second state signal has a preset level signal or not; receiving a second clock signal on the clock bus through the clock input module 5;
and S3, if the second state signal has a preset level signal, adjusting the first clock signal to be consistent with the second clock signal in phase.
In this embodiment, the DSP module 1 detects the signal on the status bus, and determines to preempt the host bit or synchronize according to the signal on the clock bus according to the detection result. The above-mentioned preempting host position becomes the process of the synchronous host computer, after other inverters finish synchronizing, become the host computer, can have a plurality of host computers to coexist, become the inverter of the host computer, has stated that has finished the synchronous process. The master-slave relation is not strictly distinguished in the method, the master-slave relation exists only in the phase before the power frequency synchronization, the clock synchronization control method of each inverter is completely the same, one inverter is out of order or added in the normal use process, and the other inverters are not influenced.
In one embodiment, the pass state input module 3 receives a second state signal on a state bus and detects whether the second state signal has a preset level signal; after the step of receiving the second clock signal on the clock bus by the clock input module 5, it further comprises:
and if the second state signal does not have the preset level signal, the state output pin is adjusted to output the preset level signal, and the first clock signal is output to the clock bus to become a host.
In this embodiment, when there is no host in the synchronization process, the state output pin is adjusted to output a preset level signal, after the current is amplified and inverted by the triode after passing through the circuit shown in fig. 2, the state output pin is a stable level signal (when the preset level signal is high, the state bus is a stable low level signal, when the preset level signal is low, the state bus is a stable high level signal), and during the synchronization process, the inverter completing synchronization outputs the preset level signal on the synchronization bus, and the other inverter not completing synchronization can acquire the clock signal of the synchronization host on the clock bus again by detecting the preset level signal, and complete synchronization according to the clock signal of the synchronization host.
In one embodiment, the step of adjusting the first clock signal to be consistent with the second clock signal, if any, includes:
if the second state signal is detected to have a preset level signal, judging that a host is on the state bus, and entering into interruption and waiting for n period times, wherein n is a natural number;
controlling the state output pin to output high level at the moment of rising edge or falling edge of the first state signal after waiting for finishing; the clock input module 5 is used for acquiring a second clock signal on the clock bus, capturing a time difference T between a preset phase of the first clock signal and a preset phase of the second clock signal, controlling the first clock signal to enter into interruption, outputting the first clock signal to the clock bus after T-T time, completing synchronization, and placing the state output pin at a preset position; where T is the period of the clock signal.
In this embodiment, the above-mentioned entry interrupts and waits for n period times, ensuring accurate synchronization. The time difference T between the preset phase of the first clock signal and the preset phase of the second clock signal is captured, so that after the phase of the first clock signal is static, the second clock signal is synchronous after the time of T-T. In the synchronization process, if one synchronization is unsuccessful because of the difference of the machines, repeating the process until the synchronization is successful; synchronization may be considered successful when the phase difference is within a predetermined range (e.g., the error is 1%, 2%, 3%, 4%, 5%, etc.). The DSP module 1 completes the synchronization by controlling this off system. The state output pin is placed at a preset position, namely the state output pin can be placed high or low, a stable high-level signal or a stable low-level signal can be output, and the state output pin is a stable level signal when being output to the state bus, and other inverters identify the host through detecting the stable level signal.
In one embodiment, the step of adjusting the state output pin to output the preset level signal and outputting the second clock signal to the clock bus to become the host if the second state signal has no preset level signal includes:
if the second state signal is detected to have no preset level signal, judging that the state bus has no host, controlling the first state signal to enter a state of being interrupted to the rising edge or the falling edge of the next first state signal, placing the state output pin at a preset position, outputting a second clock signal to a clock bus, adjusting the output of the inverter to be at a preset frequency to become the host, and ending the synchronous flow.
In this embodiment, the state output pin is placed at a preset position at the time of the rising edge or the falling edge of the first state signal, so that the clock signal generated by the PWM module is just at the rising edge or the falling edge, which is beneficial to capturing the phase during synchronization.
In one embodiment, as shown in fig. 4, the method for synchronizing power frequency of parallel operation of multiple inverters according to the present invention is based on the circuit shown in fig. 1, and the method includes:
the DSP module 1 controls the starting of the PWM module, generates a first state signal and a first clock signal, outputs the first state signal to a state bus through the state output module 2, and outputs the first clock signal to a clock bus through the clock output module 4;
receiving a second state signal on the state bus through the state input module 3, and detecting whether the second state signal has a low level signal or not;
if yes, entering into interruption and waiting for n period times, wherein n is a natural number; preferably n <5; the clock input module 5 is used for acquiring a second clock signal on the clock bus, capturing a time difference T between a preset phase of the first clock signal and a preset phase of the second clock signal, controlling the first clock signal to enter into interruption, outputting the first clock signal to the clock bus after the time of T-T, completing synchronization, and setting a state output pin to be high; wherein T is the period of the clock signal;
if the second state signal is detected to have no preset level signal, judging that the state bus has no host, starting to occupy the host bit, controlling the first state signal to enter the rising edge time of the next first state signal, setting the state output pin high, outputting the second clock signal to the clock bus to become the host, adjusting the output of the inverter to the preset frequency, and ending the synchronization flow.
The invention discloses an inverter parallel operation frequency synchronization circuit, which comprises: the system comprises a DSP module 1, a state output module 2, a state input module 3, a clock output module 4, a clock input module 5 and a clock synchronous bus; wherein the clock synchronization bus comprises a status bus and a clock bus; the state output pin and the state input pin of the DSP module 1 are respectively connected with a state bus through a state output module 2 and a state input module 3; the clock output pin and the clock input pin of the DSP module 1 are respectively connected with a clock bus through a clock output module 4 and a clock input module 5; the DSP module 1 detects whether a low-level signal exists on a state bus through a state input module 3; if so, the host is judged to exist, the clock signal of the host on the clock bus is detected through the clock input module 5, the clock signal is regulated to be consistent with the clock signal of the host on the clock bus through the DSP module 1, and the clock signal is output to the clock bus through the clock output module 4. According to the invention, the identical clock synchronization circuits are built in the inverters, so that the master-slave relation is not strictly distinguished, the master-slave relation exists only in the stage before the power frequency synchronization, the clock synchronization control method of each inverter is identical, one inverter fails or is withdrawn, or the inverter is added in the normal use process, and no influence is caused on other inverters.
The foregoing description is only of the preferred embodiments of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes using the descriptions and drawings of the present invention or directly or indirectly applied to other related technical fields are included in the scope of the invention.
Claims (7)
1. An inverter parallel operation frequency synchronization circuit, the circuit comprising:
the DSP module is used for sending out a first state signal of the inverter and receiving a second state signal on the state bus; and, for generating and issuing a first clock signal and receiving a second clock signal on the clock bus; when the DSP module detects that the second state signal has a preset level signal, the first clock signal is adjusted to be consistent with the second clock signal; when the DSP module detects that the second state signal does not have a preset level signal, the host is preempted to become a synchronous host;
the state output module is used for amplifying the first state signal and then sending the amplified first state signal to the state bus;
the state input module is used for amplifying the second state signal and then sending the second state signal to the DSP module;
the clock output module is used for amplifying the first clock signal and then sending the amplified first clock signal to the clock bus;
the clock input module is used for amplifying the second clock signal and then sending the amplified second clock signal to the DSP module;
the clock synchronization bus further includes: the ground wire is used for connecting the ground pins of the power frequency synchronous circuits of all the inverters together so that all the inverters are grounded;
the state output module includes: resistor R1, resistor R2, resistor R3, triode Q1, diode D1 and first input source;
one end of the resistor R1 is connected with the state output pin of the DSP module, and the other end of the resistor R1 is connected with one end of the resistor R2 and the base electrode of the triode Q1; the other end of the resistor R2 and the emitter grounding pin of the triode Q1;
the collector electrode of the triode Q1 is connected with one end of the resistor R3 and the anode of the diode D1; the other end of the resistor R3 is connected with a first input source; the cathode of the diode D1 is connected with the state bus;
the clock output module includes: resistor R9, resistor R10, resistor R11, triode Q3, diode D3 and third input source;
one end of the resistor R9 is connected with the clock output pin of the DSP module, and the other end of the resistor R9 is connected with one end of the resistor R10 and the base electrode of the triode Q3; the other end of the resistor R10 and the emitter grounding pin of the triode Q3;
the collector electrode of the triode Q3 is connected with one end of the resistor R11 and the anode of the diode D3; the other end of the resistor R11 is connected with a third input source; the cathode of the diode D3 is connected with the clock bus;
the clock input module includes: resistor R13, resistor R14, resistor R15, transistor Q4, diode D4, and a fourth input source;
one end of the resistor R13 is connected with a clock input pin of the DSP module, and the other end of the resistor R14 is connected with one end of the resistor R14 and a collector electrode of the triode Q4; the other end of the resistor R14 is connected with a fourth input source;
the base electrode of the triode Q4 is connected with one end of the resistor R15 and the cathode of the diode D4; the other end of the resistor R15 and the emitter grounding pin of the triode Q4; the positive electrode of the diode D4 is connected with a clock bus.
2. The inverter parallel operation frequency synchronization circuit of claim 1, wherein the DSP module further comprises a PWM module;
the PWM module is used for generating a preset first state signal and a first clock signal.
3. The inverter parallel operation frequency synchronization circuit of claim 1, wherein the status input module comprises: resistor R5, resistor R6, resistor R7, triode Q2, diode D2 and a second input source;
one end of the resistor R5 is connected with the state input pin of the DSP module, and the other end of the resistor R6 is connected with one end of the resistor R6 and the collector electrode of the triode Q2; the other end of the resistor R6 is connected with a second input source;
the base electrode of the triode Q2 is connected with one end of the resistor R7 and the cathode of the diode D2; the other end of the resistor R7 and the emitter grounding pin of the triode Q2; the anode of the diode D2 is connected with the status bus.
4. A method of power frequency synchronization for a multiple inverter parallel operation, based on the circuit of any one of claims 1-3, the method comprising:
the DSP module generates a first state signal and a first clock signal, outputs the first state signal to the state bus through the state output module, and outputs the first clock signal to the clock bus through the clock output module;
receiving a second state signal on a state bus through a state input module, and detecting whether the second state signal has a preset level signal or not; receiving a second clock signal on the clock bus through the clock input module;
and if the second state signal has a preset level signal, adjusting the first clock signal to be consistent with the second clock signal in phase.
5. The method for synchronizing power frequency of parallel operation of multiple inverters according to claim 4, wherein the receiving, by the state input module, a second state signal on a state bus, and detecting whether the second state signal has a preset level signal; after the step of receiving, by the clock input module, the second clock signal on the clock bus, the method further comprises:
and if the second state signal does not have the preset level signal, the state output pin is adjusted to output the preset level signal, and the first clock signal is output to the clock bus to become a host.
6. The method according to claim 4, wherein the step of adjusting the first clock signal to be identical to the second clock signal if the second status signal has a preset level signal comprises:
if the second state signal is detected to have a preset level signal, judging that a host is on the state bus, and entering into interruption and waiting for n period times, wherein n is a natural number;
controlling the state output pin to output high level at the moment of rising edge or falling edge of the first state signal after waiting for finishing; the method comprises the steps that a second clock signal on a clock bus is obtained through a clock input module, the time difference T between the preset phase of a first clock signal and the preset phase of the second clock signal is captured, the first clock signal is controlled to enter into interruption, the first clock signal is output to the clock bus after the time of T-T, synchronization is completed, and the state output pin is arranged at a preset position; where T is the period of the clock signal.
7. The method for synchronizing power frequency of parallel operation of multiple inverters according to claim 5, wherein the step of adjusting the state output pin to output a preset level signal and outputting a second clock signal to a clock bus as a master if the second state signal has no preset level signal comprises:
if the second state signal is detected to have no preset level signal, judging that the state bus has no host, controlling the first state signal to enter a state of being interrupted to the rising edge or the falling edge of the next first state signal, placing the state output pin at a preset position, outputting a second clock signal to a clock bus, adjusting the output of the inverter to be at a preset frequency to become the host, and ending the synchronous flow.
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| CN101494383B (en) * | 2008-01-23 | 2011-12-14 | 力博特公司 | Control method for parallel connection system of inverter |
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