CN113076066B - High-capacity high-speed storage device and operation method thereof - Google Patents
High-capacity high-speed storage device and operation method thereof Download PDFInfo
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- CN113076066B CN113076066B CN202110401567.XA CN202110401567A CN113076066B CN 113076066 B CN113076066 B CN 113076066B CN 202110401567 A CN202110401567 A CN 202110401567A CN 113076066 B CN113076066 B CN 113076066B
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- 230000003139 buffering effect Effects 0.000 claims abstract description 3
- 230000003287 optical effect Effects 0.000 claims description 9
- 239000000872 buffer Substances 0.000 claims description 8
- 238000012544 monitoring process Methods 0.000 claims description 4
- 108010028984 3-isopropylmalate dehydratase Proteins 0.000 description 6
- 230000005540 biological transmission Effects 0.000 description 2
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- 238000011160 research Methods 0.000 description 2
- 238000012360 testing method Methods 0.000 description 2
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- 238000012935 Averaging Methods 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 238000004364 calculation method Methods 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0611—Improving I/O performance in relation to response time
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
- G06F3/0613—Improving I/O performance in relation to throughput
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0656—Data buffering arrangements
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0683—Plurality of storage devices
- G06F3/0689—Disk arrays, e.g. RAID, JBOD
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
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Abstract
The invention discloses a high-capacity high-speed memory device and an operation method thereof, wherein the device comprises a FPGA, DDR, FPGA connected with a DDR (double data rate) for buffering data; the N electronic discs are respectively connected with the FPGA through a controller and are used for forming an array hard disc structure for parallel reading and writing by the N electronic discs; the FPGA is connected with the data transceiving interface and used for transceiving data; and the FPGA is connected with the main control circuit to receive the control command. When the data is accessed, the FPGA distributes the data to N electronic discs in an average mode in a parallel mode; when reading data, the FPGA simultaneously issues a read command request to the N electronic disks, and the buffered data is sent out through the data receiving and transmitting interface. The invention can break through the bottleneck of the read-write speed of the electronic disk in a parallel mode, realizes the multiple improvement of the read-write speed, and meets the high-speed storage requirement of large capacity.
Description
Technical Field
The invention relates to the field of storage equipment, in particular to high-capacity high-speed storage equipment and an operation method thereof.
Background
In scientific research or daily life, a storage device is often required to record massive data in real time so as to facilitate subsequent analysis and research. The current data storage system on the market is usually composed of N hard disks to meet the requirement of mass storage, but the system can only read one hard disk at a time, and the access speed of a single hard disk is limited, for example, the conventional SATA hard disk has a read speed of 600MB/S at maximum, that is, the access speed of the system is 600MB/S, which cannot meet the current requirement of mass storage and high speed.
Disclosure of Invention
The present invention aims to solve at least one of the technical problems existing in the prior art. Therefore, the invention provides the high-capacity high-speed storage equipment and the operation method thereof, which can break through the bottleneck of the read-write speed of a single hard disk and meet the current high-capacity high-speed storage requirement.
A high-capacity high-speed storage device according to an embodiment of the first aspect of the present invention includes:
the FPGA is connected with the DDR and used for buffering data; the N electronic disks are respectively connected with the FPGA through a SATA interface and are used for forming an array type hard disk structure for parallel reading and writing; the FPGA is connected with the data receiving and transmitting interface and used for receiving and transmitting data; and the FPGA is connected with the main control circuit to receive the control command.
The high-capacity high-speed storage device according to the embodiment of the first aspect of the present invention has at least the following technical effects: in the embodiment of the invention, the FPGA forms an array type hard disk structure for parallel reading and writing by N electronic disks. When accessing data, the FPGA receives mass data through a data receiving and transmitting interface, firstly buffers the data to DDR, and then evenly distributes the data to N electronic discs in a parallel mode; when data is read, the FPGA simultaneously issues a read command request to the N electronic disks, the read data is buffered to DDR according to a defined data format and sequence through the controller, and finally the buffered data is sent out through the data receiving and transmitting interface. The bottleneck of the read-write speed of the electronic disk can be broken through in a parallel mode, the multiple improvement of the read-write speed is realized, and the high-speed storage requirement of large capacity is met.
According to some embodiments of the invention, the data transceiver interface includes an MPO optical port and a Serial RapidIO port.
According to some embodiments of the invention, the main control circuit includes a CPU, a PCIE interface, an ethernet port, and an IPMI module, where the CPU is connected to the ethernet interface for connection to a host computer, the CPU is connected to the FPGA through the PCIE interface, and the CPU is connected to the IPMI module for monitoring temperature, voltage, and current data.
According to some embodiments of the invention, the number of electronic disks is 10.
A method of operating a high-capacity high-speed memory device according to an embodiment of the second aspect of the present invention includes the steps of data writing and data reading:
and (3) data writing:
after receiving external data from the data receiving and transmitting interface, the FPGA adopts an average algorithm and a conditional triggering mode to buffer the data to the DDR;
after the buffered data volume reaches the specified condition, the FPGA simultaneously issues a write command request to N electronic disks in a parallel mode, equally divides the buffered data in the DDR into N equal parts and writes the N equal parts into the N electronic disks respectively;
reading data:
indexing to a starting sector position in the electronic disk from the file system according to the read parameters;
the FPGA simultaneously issues a read command request to the N electronic disks, and the read data are buffered to DDR according to a defined data format and sequence through the controller;
and forwarding the buffered data to a data receiving and transmitting interface to be sent out after the specified condition is met.
According to some embodiments of the invention, the specific steps of the averaging algorithm are
The main control circuit converts the byte number into the sector number according to the byte number of the total data quantity;
the main control circuit calculates the number of sectors required by a single disk = total number of sectors/(number of electronic disks), configures the number of sectors required by the single disk to the FPGA,
writing data into the memory by the memory control circuit according to the number of sectors required by a single disk
According to some embodiments of the present invention, the conditional triggering manner is that the FPGA sets the time for issuing the write to the electronic disc according to the configured data amount of the burst write or the timeout time.
According to some embodiments of the invention, the specified conditions for the buffered data volume to be reached are: the amount of data to be written reaches 512 x, where x is the number of sectors.
The high-capacity high-speed storage device according to the embodiment of the second aspect of the present invention has at least the following technical effects: in the embodiment of the invention, the FPGA forms an array type hard disk structure for parallel reading and writing by N electronic disks. When accessing data, the FPGA receives mass data through a data receiving and transmitting interface, firstly buffers the data to DDR, and then evenly distributes the data to N electronic discs in a parallel mode; when data is read, the FPGA simultaneously issues a read command request to the N electronic disks, the read data is buffered to DDR according to a defined data format and sequence through the controller, and finally the buffered data is sent out through the data receiving and transmitting interface. The bottleneck of the read-write speed of the electronic disk can be broken through in a parallel mode, the multiple improvement of the read-write speed is realized, and the high-speed storage requirement of large capacity is met.
Additional aspects and advantages of the invention will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The foregoing and/or additional aspects and advantages of the invention will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic block diagram of an electronic disk, an FPGA, a data transceiver interface and a DDR in an embodiment of the invention;
FIG. 2 is a schematic block diagram of a main control circuit in an embodiment of the invention;
FIG. 3 is a flow chart of data writing in an embodiment of the invention;
FIG. 4 is a flow chart of reading data according to an embodiment of the invention.
Detailed Description
Embodiments of the present invention are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the invention.
In the description of the present invention, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present invention can be reasonably determined by a person skilled in the art in combination with the specific contents of the technical scheme.
Referring to fig. 1 and 2, a high-capacity high-speed storage device includes: the data transmission and reception device comprises an FPGA100, a DDR200, N electronic discs 300, a data transmission and reception interface and a main control circuit; the FPGA100 is connected to the DDR200, in this embodiment, the type of the FPGA100 is Xilinx V7-FPGA100 XC7VX485T, the number of the electronic disks 300 is 10, all SATA electronic disks 300 are adopted, of course, other numbers of electronic disks 300 may also be adopted, the 10 electronic disks 300 are respectively connected to the FPGA100 through a SATA interface, SATA controllers are configured on the SATA interfaces, and the FPGA100 forms an array hard disk structure for parallel reading and writing with the 10 electronic disks 300. The FPGA100 is connected to a data transceiver interface, which is used to connect to a peer device to transmit mass data. Preferably, the data transceiver interface in this embodiment includes an MPO optical port 410 and a Serial RapidIO port 420, where the opposite end device connected to the MPO optical port 410 is an MPO optical port 410 device, and uses optical fiber to connect and communicate; the opposite terminal equipment connected with the Serial rapidIO is equipment of a Serial rapidIO interface, and is communicated by using electric signal connection; the speed of the MPO optical port 410 and the Serial Rapid IO port 420 can reach 6.25Gbps, and the MPO optical port and the Serial Rapid IO port can be configured to be 1.25Gbps, 3.125Gbps, 5Gbps and the like, so that the high-capacity data receiving and transmitting requirements are met.
The FPGA100 is connected to a main control circuit to receive a control command, referring to fig. 2, the main control circuit includes a CPU510, a PCIE interface 520, an ethernet port 530, and an IPMI module 540, where the CPU510 is connected to the ethernet interface, and connects to the internet through the ethernet port 530 to communicate with other devices, such as an upper computer; CPU510 runs the VxWorks operating system, and recognizes the array hard disk structure consisting of 10 electronic disks 300 as 1 large-capacity SATA electronic disk 300 through a driver and a file system. CPU510 receives control, query commands, and upload status data, such as query device processor temperature, motherboard temperature, supply voltage, voltage current commands, through Ethernet port 530; setting a MPO light port 410 link speed command; querying the electronic disc 300 for status commands; a query file data command; control commands such as start data recording, start data playback, stop data recording, stop data playback, etc. The CPU510 is connected to the FPGA100 through a PCIE interface 520, so as to implement communication between the storage unit and the control unit.
The CPU510 is connected to the IPMI module 540, the IPMI module 540 adopts a main chip with the model PIC32MX564F128, and the IPMI module 540 provides monitoring functions for monitoring temperature, voltage, current data, and the like, so as to monitor the operation of each circuit and the electronic disc 300, and perform feedback and processing even when an abnormal state occurs.
The invention also relates to an operation method of the high-capacity high-speed storage device, which comprises the steps of data writing and data reading:
referring to fig. 3, the specific steps of data writing are as follows: the external mass data are transmitted to the FPGA through the MPO optical port and the Serial Rapid IO port, the FPGA buffers the data into the DDR after receiving the data, when the conditions are met, a write command request is issued to 10 SATA electronic discs simultaneously in a parallel mode, the buffered data in the DDR are equally divided into 10 equal parts, and the 10 equal parts are respectively written into the 10 electronic discs. The FPGA adopts an average algorithm and a condition triggering mode to buffer data to be written, and after the data volume reaches the condition, the data are written into 10 electronic discs, and a received packet of data is distributed to the 10 electronic discs in an average mode.
The average algorithm in this embodiment, i.e. arithmetic average calculation, comprises the following specific steps of
S101, the FPGA transmits the information of the total data quantity to a CPU in the main control circuit, and the CPU converts the byte number into the sector number according to the byte number of the total data quantity, namely, the total sector number = total byte number/512.
S102, the CPU calculates the number of sectors required by the single disk = total number of sectors/(number of electronic disks), and then configures the number of sectors required by the single disk to the FPGA.
And S103, finally, writing data into the FPGA according to the number of sectors required by the single disk.
When writing into the storage device, the data volume of the single disk=the total data volume input +..
When the storage device reads, the data amount of the read single disk=the total data amount output/(the number of electronic disks).
The user can adjust the buffer data amount through setting, so that the writing speed of the single electronic disk is improved. Through test verification, the writing speed can reach 3.2GB/s, and the integral speed of writing into the electronic disk is obviously improved.
The definition of the conditional triggering mode is as follows: when the FPGA needs to write data into the electronic disk, the FPGA firmware sets the time for issuing the data to be written into the electronic disk according to the data quantity of one burst writing or the overtime time configured by the CPU, namely the trigger condition.
For example, when the burst write-once data amount is 1024 bytes, if the actual input data is less than 1024 bytes, the FPGA has timeout setting, and after the timeout setting time is exceeded, a write command is issued to write the data to the electronic disk.
When the burst write-once data amount is configured to be 1024 bytes, if the actual input data satisfies the multiple of 1024 bytes, the FPGA will write once the electronic disk in 1024 bytes.
Wherein, the meaning of the data volume reaching the condition is: the electronic disks are all addressed by sectors, the FPGA firmware is in sectors as data units, and 1 sector is 512 bytes in size. When the data volume to be written reaches 10 x 512 x bytes (bytes/sector), the firmware logic issues and writes the data into 10 electronic discs, x is the number of sectors, and each disc writes 512 x bytes. x is configured by the system software of the master circuit. The larger the configuration value is, the larger the data amount is when burst writing is performed at one time, the higher the utilization rate of the electronic disc is, and the faster the rate is.
Referring to fig. 4, the steps for reading data are as follows: indexing to a starting sector position in the electronic disk from the file system according to the read parameters;
the CPU regards the data and the files in a file system formed by a plurality of electronic disks as a whole, but the actual data is distributed to the electronic disks for storage. When the data is read out, the CPU indexes to the initial sector position in the electronic disk from the file system according to the parameters transmitted by the upper computer, the FPGA simultaneously issues a read command request to 10 SATA electronic disks, the read data is buffered to the DDR according to the defined data format and sequence by the SATA controller, and the buffered data is forwarded to the MPO optical port or the Serial Rapid IO port when the conditions are met. This condition can be set to adjust the amount of buffered data to increase the single electronic disc reading speed.
By adopting the method, the overall speed of storing/reading the electronic disk can be obviously improved, and the test verification can reach 3.2GB/s.
In summary, the embodiment of the invention forms an array type hard disk structure for parallel reading and writing by N electronic disks. When accessing data, the FPGA receives mass data through a data receiving and transmitting interface, firstly buffers the data to DDR, and then evenly distributes the data to N electronic discs in a parallel mode; when data is read, the FPGA simultaneously issues a read command request to the N electronic disks, the read data is buffered to DDR according to a defined data format and sequence through the controller, and finally the buffered data is sent out through the data receiving and transmitting interface. The bottleneck of the read-write speed of the electronic disk can be broken through in a parallel mode, the multiple improvement of the read-write speed is realized, and the high-speed storage requirement of large capacity is met.
The embodiments of the present invention have been described in detail with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present invention.
Claims (6)
1. A high-capacity high-speed storage device, comprising:
FPGA(100)；
DDR (200), the FPGA (100) is connected with the DDR (200) for buffering data;
the N electronic disks (300) are respectively connected with the FPGA (100) through a controller, and are used for forming an array type hard disk structure for parallel reading and writing by the N electronic disks (300);
the FPGA (100) is connected with the data transceiving interface and is used for transceiving data;
the FPGA (100) is connected with the main control circuit to receive a control command;
the main control circuit operates the steps of data writing and data reading, and the steps are as follows:
and (3) data writing:
after receiving external data from a data receiving and transmitting interface, the FPGA buffers the data to the DDR by adopting an average algorithm and a condition triggering mode, wherein the condition triggering mode is that the FPGA sets the time for issuing and writing the data into the electronic disk according to the configured data quantity written in one burst or the timeout time;
after the buffered data volume reaches the specified condition, the FPGA simultaneously issues a write command request to N electronic disks in a parallel mode, equally divides the buffered data in the DDR into N equal parts and writes the N equal parts into the N electronic disks respectively;
reading data:
indexing to a starting sector position in the electronic disk from the file system according to the read parameters;
the FPGA simultaneously issues a read command request to the N electronic disks, and the read data are buffered to DDR according to a defined data format and sequence through the controller;
and forwarding the buffered data to a data receiving and transmitting interface to be sent out after the specified condition is met.
2. The mass storage device of claim 1, wherein: the data transceiver interface comprises an MPO optical port (410) and a Serial rapidIO port (420).
3. The mass storage device of claim 1, wherein: the main control circuit comprises a CPU (510), a PCIE interface (520), an Ethernet port (530) and an IPM I module (540), wherein the CPU (510) is connected with the Ethernet port (530) for connecting an upper computer, the CPU (510) is connected with the FPGA (100) through the PCIE interface (520), and the CPU (510) is connected with the IPM I module (540) for monitoring temperature, voltage and current data.
4. The mass storage device of claim 1, wherein: the number of the electronic disks (300) is 10.
5. The mass storage device of claim 1, wherein: the specific steps of the average algorithm are as follows
The main control circuit converts the byte number into the sector number according to the byte number of the total data quantity;
the main control circuit calculates the number of sectors required by a single disk = total number of sectors/(number of electronic disks), and configures the number of sectors required by the single disk to the FPGA;
the memory control circuit writes data according to the number of sectors required by a single disk.
6. The mass storage device of claim 1, wherein: the specified conditions for the buffered data amount are: the amount of data to be written reaches 512 x, where x is the number of sectors.
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