CN112416830B - NVME and SATA protocol conversion realization circuit - Google Patents
NVME and SATA protocol conversion realization circuit Download PDFInfo
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- CN112416830B CN112416830B CN202011428627.9A CN202011428627A CN112416830B CN 112416830 B CN112416830 B CN 112416830B CN 202011428627 A CN202011428627 A CN 202011428627A CN 112416830 B CN112416830 B CN 112416830B
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- 238000006243 chemical reaction Methods 0.000 title claims description 19
- 230000005540 biological transmission Effects 0.000 claims abstract description 18
- 238000004806 packaging method and process Methods 0.000 claims description 6
- 238000009432 framing Methods 0.000 claims 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/382—Information transfer, e.g. on bus using universal interface adapter
- G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F2213/0026—PCI express
Abstract
The invention relates to the technical field of electronic disks, in particular to an implementation circuit for converting NVME and SATA protocols, which can enable wide-temperature SATA electronic disk products to be connected into a system needing the NVME electronic disk; the circuit comprises a SATA electronic disk, a SATA physical layer, a SATA transmission layer, a SATA application layer, a command/address translation module, an NVME protocol module, a data circulation buffer zone, a data DMA engine, a PCIE Hard Block and a host, wherein the SATA electronic disk is connected with the SATA physical layer, the SATA physical layer is connected with the SATA transmission layer, the SATA transmission layer is connected with the SATA application layer, the SATA application layer is connected with the command/address translation module, the command/address translation module is connected with the NVME protocol module, the SATA application layer is connected with the data circulation buffer zone through data flow, the data circulation buffer zone is connected with the data DMA engine, the data DMA engine and the NVME protocol module are both connected with the PCIE Hard Block, and the PCIE Hard Block is connected with the host.
Description
Technical Field
The invention relates to the technical field of electronic disks, in particular to a circuit for realizing conversion between NVME and SATA protocols.
Background
Electronic disc products supporting NVME protocol at present can be generally used only in a commercial grade temperature range, and even can only work in a temperature range of 10-60 degrees. While many special industry products require the use of wider temperature range NVME protocol electronic disc products.
Disclosure of Invention
In order to solve the technical problems, the invention provides a circuit for realizing the conversion between NVME and SATA protocols, which can enable wide-temperature SATA electronic disk products to be connected into a system requiring NVME electronic disks.
The invention relates to a circuit for realizing conversion between NVME and SATA protocol, which comprises a SATA electronic disk, a SATA physical layer, a SATA transmission layer, a SATA application layer, a command/address translation module, a NVME protocol module, a data circulation buffer area, a data DMA engine, a PCIE Hard Block and a host.
The invention relates to a circuit for realizing conversion between NVME and SATA protocol, wherein an NVME protocol module comprises a management queue circulation buffer zone with variable length: the management command is used for caching the management command issued by the host for processing by a subsequent module;
variable length IO command queue circular buffer: the system is used for caching high-speed read, write, erase and other IO operation commands for subsequent command and address translation module analysis and processing;
variable length IO completion queue circular buffer: the address translation module is used for caching commands, processing completed commands and finishing information of the DMA engine.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a data DMA engine: under the drive of a command and address translation module, high-speed data movement is realized;
variable length data circular buffer: for caching read and write data at high speed.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a command/address translation module: the translation of information such as read, write commands, addresses, data length, read-write priority and the like is realized, and read-write requests under the NVMe protocol are translated into corresponding SATA operations; the response (correct completion, exception) of SATA is transferred to state information under NVMe protocol and filled into IO completion queue circular buffer.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a SATA application layer: the NCQ protocol (optimizing order, executing multiple commands) is implemented to send and execute commands.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a SATA transmission layer: assembling the command and address transmitted by the application layer into FIS (or reverse analysis) (FIS is a mechanism for information transmission between Host and device, and the FIS format has 14 types and maximum length 8192 bits); the data accompanying the command is assembled into a FIS (or reverse parse).
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a SATA physical layer: the method comprises the steps of packaging the GTX of the FPGA to realize the OOB and other functions, calculating CRC value, scrambling, carrying out 8bit/10bit coding on FIS transmitted by a transmission layer, packaging a Frame signal and transmitting the Frame signal to the GTX; or reversely carrying out 8bit/10bit decoding, descrambling, CRC checking and the like on the data transmitted by the GTX, and transmitting the FIS to a transmission layer module.
Compared with the prior art, the invention has the beneficial effects that: through the SATA electronic disk, the SATA physical layer, the SATA transmission layer, the SATA application layer, the command/address translation module, the NVME protocol module, the data circulation buffer, the data DMA engine, the PCIE Hard Block and the host, all the functional modules are realized by adopting an FPGA with a PCIE Hard core and a high-speed GTX transceiver, the circuit is realized by adopting XC7K325T, and a wide-temperature SATA electronic disk product can be accessed into a system needing the NVME electronic disk.
Drawings
FIG. 1 is a schematic diagram of the structure of the present invention;
the reference numerals in the drawings: 1. SATA electronic disks; 2. SATA physical layer; 3. a SATA transport layer; 4. a SATA application layer; 5. a command/address translation module; 6. a data circular buffer; 7. a data DMA engine; 8. PCIE Hard Block; 9. a host; 10. managing a queue circular buffer; 11. IO command queue circular buffer; 12. IO completion queue circular buffer.
Detailed Description
The following describes in further detail the embodiments of the present invention with reference to the drawings and examples. The following examples are illustrative of the invention and are not intended to limit the scope of the invention.
All the functional modules are realized by adopting an FPGA with PCIE Hard Block8 and a high-speed GTX transceiver, and particularly, the realizing circuit of the invention is realized by adopting XC7K 325T.
As shown in fig. 1, an implementation circuit for converting NVME and SATA protocols of the present invention includes a SATA electronic disk 1, a SATA physical layer 2, a SATA transport layer 3, a SATA application layer 4, a command/address translation module 5, an NVME protocol module, a data circulation buffer 6, a data DMA engine 7, a PCIE Hard Block8, and a host 9, wherein the SATA electronic disk 1 is connected to the SATA physical layer 2, the SATA physical layer 2 is connected to the SATA transport layer 3, the SATA transport layer 3 is connected to the SATA application layer 4, the SATA application layer 4 is connected to the command/address translation module 5, the command/address translation module 5 is connected to the NVME protocol module, the SATA application layer 4 is connected to the data circulation buffer 6 through a data stream, the data circulation buffer 6 is connected to the data DMA engine 7, the data DMA engine 7 and the NVME protocol module are connected to the PCIE Hard Block8, and the PCIE Hard Block8 is connected to the host 9.
The invention relates to a circuit for realizing conversion between NVME and SATA protocol, wherein an NVME protocol module comprises a management queue circulating buffer zone 10 with variable length: the management command issued by the host 9 is used for caching the management command for processing by a subsequent module;
variable length IO command queue circular buffer 11: the system is used for caching high-speed read, write, erase and other IO operation commands for subsequent command and address translation module analysis and processing;
variable length IO completion queue circular buffer 12: the address translation module is used for caching commands, processing completed commands and finishing information of the DMA engine.
The invention relates to a circuit for realizing conversion between NVME and SATA protocols, which comprises a data DMA engine 7: under the drive of a command and address translation module, high-speed data movement is realized;
variable length data circular buffer 6: for caching read and write data at high speed.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a command/address translation module 5: the translation of information such as read, write commands, addresses, data length, read-write priority and the like is realized, and read-write requests under the NVMe protocol are translated into corresponding SATA operations; the SATA response (correct completion, exception) is transferred to state information under NVMe protocol and filled into IO completion queue circular buffer 12.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a SATA application layer 4: the NCQ protocol (optimizing order, executing multiple commands) is implemented to send and execute commands.
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a SATA transmission layer 3: assembling the command and address transmitted by the application layer into FIS (or reverse analysis) (FIS is a mechanism for information transmission between Host and device, and the FIS format has 14 types and maximum length 8192 bits); the data accompanying the command is assembled into a FIS (or reverse parse).
The invention relates to a circuit for realizing NVME and SATA protocol conversion, which comprises a SATA physical layer 2: the method comprises the steps of packaging the GTX of the FPGA to realize the OOB and other functions, calculating CRC value, scrambling, carrying out 8bit/10bit coding on FIS transmitted by a transmission layer, packaging a Frame signal and transmitting the Frame signal to the GTX; or reversely carrying out 8bit/10bit decoding, descrambling, CRC checking and the like on the data transmitted by the GTX, and transmitting the FIS to a transmission layer module.
In the circuit for realizing the conversion between the NVME and the SATA protocol, all the power consumption modules and the power consumption devices are common electric devices in the market, the power consumption modules and the power consumption devices can be used only by mutually and electrically connecting the power consumption modules and the power consumption devices according to the use instruction purchased together when the power consumption devices are purchased, and the control modules are common self-contained modules, so that the details are not repeated herein.
The foregoing is merely a preferred embodiment of the present invention, and it should be noted that it will be apparent to those skilled in the art that modifications and variations can be made without departing from the technical principles of the present invention, and these modifications and variations should also be regarded as the scope of the invention.
Claims (2)
1. The circuit is characterized by comprising a SATA electronic disk, a SATA physical layer, a SATA transmission layer, a SATA application layer, a command/address translation module, a NVME protocol module, a data circulation buffer area, a data DMA engine, a PCIE Hard Block and a host, wherein the SATA electronic disk is connected with the SATA physical layer, the SATA physical layer is connected with the SATA transmission layer, the SATA transmission layer is connected with the SATA application layer, the SATA application layer is connected with the command/address translation module, the command/address translation module is connected with the NVME protocol module, the SATA application layer is connected with the data circulation buffer area through data flow, the data circulation buffer area is connected with the data DMA engine, the data DMA engine and the NVME protocol module are connected with the PCIE Hard Block, and the PCIE Hard Block is connected with the host;
the NVME protocol module includes a variable length management queue circular buffer: the management command is used for caching the management command issued by the host for processing by a subsequent module;
variable length IO command queue circular buffer: the system is used for caching high-speed read, write, erase and other IO operation commands for subsequent command and address translation module analysis and processing;
variable length IO completion queue circular buffer: the address translation module is used for caching commands, processing completed commands and finishing information of the DMA engine;
command/address translation module: translation of read and write commands, addresses, data length and read and write priority information is realized, and read and write requests under the NVMe protocol are translated into corresponding SATA operations; transferring the response of the SATA into state information under the NVMe protocol, and filling the state information into an IO completion queue circulation buffer area;
SATA application layer: realizing sending and executing command and NCQ protocol;
SATA transport layer: assembling the command and the address transmitted by the application layer into FIS or reverse analysis; assembling data accompanied by the command into FIS or reverse parsing;
SATA physical layer: packaging the GTX of the FPGA to realize the OOB function, calculating CRC value, scrambling, 8bit/10bit coding for FIS transmitted by a transmission layer, packaging a framing signal and transmitting the framing signal to the GTX; or reversely decoding 8bit/10bit data transmitted from the GTX, descrambling and CRC, and transmitting the FIS to a transmission layer module.
2. The implementation circuit for NVME and SATA protocol conversion as recited in claim 1 wherein said data DMA engine: under the drive of a command and address translation module, high-speed data movement is realized;
variable length data circular buffer: for caching read and write data at high speed.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202011428627.9A CN112416830B (en) | 2020-12-09 | 2020-12-09 | NVME and SATA protocol conversion realization circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202011428627.9A CN112416830B (en) | 2020-12-09 | 2020-12-09 | NVME and SATA protocol conversion realization circuit |
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| CN112416830A CN112416830A (en) | 2021-02-26 |
| CN112416830B true CN112416830B (en) | 2024-03-26 |
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| CN114721984B (en) * | 2022-03-30 | 2024-03-26 | 湖南长城银河科技有限公司 | SATA interface data transmission method and system for low-delay application |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101008931A (en) * | 2005-11-18 | 2007-08-01 | 伊诺瓦科技股份有限公司 | Cryptographic serial ATA apparatus and method |
| CN102902489A (en) * | 2012-08-17 | 2013-01-30 | 杭州华澜微科技有限公司 | Dual-interface memory controller and system thereof |
| CN103415085A (en) * | 2013-07-15 | 2013-11-27 | 同济大学 | Automatic generation method of general MAC protocol processor |
| CN109240952A (en) * | 2018-08-27 | 2019-01-18 | 北京计算机技术及应用研究所 | A kind of high-speed data encryption NVMe-SATA converter circuit |
-
2020
- 2020-12-09 CN CN202011428627.9A patent/CN112416830B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101008931A (en) * | 2005-11-18 | 2007-08-01 | 伊诺瓦科技股份有限公司 | Cryptographic serial ATA apparatus and method |
| CN102902489A (en) * | 2012-08-17 | 2013-01-30 | 杭州华澜微科技有限公司 | Dual-interface memory controller and system thereof |
| CN103415085A (en) * | 2013-07-15 | 2013-11-27 | 同济大学 | Automatic generation method of general MAC protocol processor |
| CN109240952A (en) * | 2018-08-27 | 2019-01-18 | 北京计算机技术及应用研究所 | A kind of high-speed data encryption NVMe-SATA converter circuit |
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| CN112416830A (en) | 2021-02-26 |
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