CN113067581B - Decoding system, decoding method, electronic device, and storage medium - Google Patents
Decoding system, decoding method, electronic device, and storage medium Download PDFInfo
- Publication number
- CN113067581B CN113067581B CN202110267992.4A CN202110267992A CN113067581B CN 113067581 B CN113067581 B CN 113067581B CN 202110267992 A CN202110267992 A CN 202110267992A CN 113067581 B CN113067581 B CN 113067581B
- Authority
- CN
- China
- Prior art keywords
- decoding
- message
- data
- module
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/30—Compression; Expansion; Suppression of unnecessary data, e.g. redundancy reduction
Abstract
The invention relates to a decoding system, a decoding method, an electronic device and a storage medium, wherein the decoding system comprises: the data merging module and at least two message decoding modules, each message decoding module corresponds to a decoding message type; each message decoding module is used for decoding FAST stream data of a corresponding decoding message type by using XML template data corresponding to the decoding message type of the message decoding module to obtain decoding data of the corresponding decoding message type; and the data merging module is used for merging the decoding data aiming at each decoding message type to obtain merged decoding data. In the embodiment of the invention, at least two message decoding modules decode FAST stream data of different decoding message types in parallel, and then merge decoded data obtained by decoding to obtain merged decoded data. Through the parallel decoding of at least two message decoding modules, the data decoding speed is improved, and the data decoding delay is reduced.
Description
Technical Field
The present application relates to the field of computer technologies, and in particular, to a decoding system, a decoding method, an electronic device, and a storage medium.
Background
In an actual service scenario, the requirements for low-delay transmission and low-delay processing are increasing, and the requirements for real-time performance of data calculation are also more urgent. The lower the processing delay of the service system is, the better the performance is, the higher the real-time performance is, the faster and faster the processing speed is, and more service processing and information acquisition can be completed in the same time.
At present, most of transaction systems in the domestic financial industry are based on the traditional general CPU architecture, the bottleneck exists in transaction speed increase, and the transaction requirements of ultra-low time delay cannot be met. With the development of financial science and technology, various algorithm transactions and quantitative transactions are started, and the competition of pursuing lower transaction delay time in the financial industry is continuously upgraded, so that the competition becomes one of the core challenges of various financial institutions. Especially, in recent years, the comprehensive application of programmed trading in the capital market, the traditional software technology or the acceleration technology taking software as the core has difficulty in meeting the requirements of real-time processing and real-time response in the microsecond level.
Disclosure of Invention
To solve the technical problem or at least partially solve the technical problem, the present application provides a decoding system, a decoding method, an electronic device, and a storage medium.
In a first aspect, the present application provides a decoding system comprising: the device comprises a data merging module and at least two message decoding modules, wherein each message decoding module corresponds to a decoding message type;
each message decoding module is used for decoding FAST stream data of a corresponding decoding message type by using XML template data corresponding to the decoding message type of the message decoding module to obtain decoding data of the corresponding decoding message type;
and the data merging module is used for merging the decoding data aiming at each decoding message type to obtain merged decoding data.
Optionally, the decoding system further comprises: a decoding control module as a pre-stage input of the message decoding module, wherein the decoding control module comprises a first storage area for storing FAST stream data and a second storage area for storing XML template data;
the decoding control module is used for writing FAST stream data of different decoding message types into a preset first storage area and writing XML template data of different decoding message types into a preset second storage area;
the message decoding module is further configured to generate, according to a decoded message type of the message decoding module, a first read-write control signal for reading FAST stream data of a corresponding decoded message type in the first storage area and a second read-write control signal for reading XML template data of a corresponding decoded message type in the second storage area;
the decoding control module is further configured to read FAST stream data in the first storage area according to the first read-write control signal of each message decoding module, send the read FAST stream data to the message decoding module, read XML template data in the second storage area according to the second read-write control signal of each message decoding module, and send the read XML template data to the message decoding module.
Optionally, the decoding system further comprises: a stop bit detection module as a preceding stage input of the decoding control module;
the stop bit detection module is used for receiving FAST stream data of at least two decoding message types, identifying the stop bit in the FAST stream data, removing the stop bit in the FAST stream data to obtain new FAST stream data, and writing the obtained FAST stream data into a first storage area of the decoding control module.
Optionally, the decoding system further comprises: a command multiplexing module located between the decoding control module and the message decoding module;
the command multiplexing module is configured to perform arbitration selection on the first read-write control signal and the second read-write control signal according to a type of a decoding message, and send the arbitrated first read-write control signal and the arbitrated second read-write control signal to the decoding control module;
and sending the FAST stream data and the XML template data read by the decoding control module to the corresponding message decoding module.
Optionally, the command multiplexing module is further configured to select a first read-write control signal and a second read-write control signal that request to read the same decoding message type, and send the selected first read-write control signal and the selected second read-write control signal to the decoding control module;
and sending the FAST stream data and the XML template data of the same decoding message type read by the decoding control module to the corresponding message decoding module.
Optionally, the decoding system further comprises: a configuration table, wherein the configuration table contains offsets of fields of FAST operators in None in the XML template data of a plurality of decoding message types in PMap, and base addresses of the XML template data of each decoding message type in the second storage area and interface addresses of the second storage area;
the message decoding module is further configured to generate the second read/write control signal according to the configuration table;
the decoding control module is further configured to write XML template data of different decoding message types into a preset second storage area according to the configuration table.
In a second aspect, the present application provides a decoding method, including:
controlling at least two message decoding modules to decode FAST stream data of corresponding decoding message types by using XML template data corresponding to the decoding message types of the message decoding modules to obtain decoding data of corresponding decoding message types;
and the control data merging module merges the decoding data aiming at each decoding message type to obtain merged decoding data.
Optionally, the decoding method further comprises:
in response to a trigger operation for adding or deleting a message decoding module of any decoded message type, creating or deleting a message decoding module of the decoded message type;
or, in response to a modification operation for modifying any decoded message type, modifying XML template data associated with the decoded message type.
In a third aspect, the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete mutual communication through the communication bus;
a memory for storing a computer program;
a processor for implementing the decoding method according to any one of the second aspect when executing the program stored in the memory.
In a fourth aspect, the present application provides a computer-readable storage medium having a program of the decoding method stored thereon, the program of the decoding method implementing the steps of the decoding method of any one of the second aspects when executed by a processor.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the following advantages:
in the embodiment of the invention, FAST stream data of different decoding message types are decoded in parallel by at least two message decoding modules, and then the decoded data obtained by decoding are combined to obtain combined decoded data. Through the parallel decoding of at least two message decoding modules, the data decoding speed is improved, and the data decoding delay is reduced.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the invention and together with the description, serve to explain the principles of the invention.
In order to more clearly illustrate the embodiments or technical solutions in the prior art of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly described below, and it is obvious for those skilled in the art to obtain other drawings without inventive labor.
Fig. 1 is a block diagram of a decoding system according to an embodiment of the present application;
fig. 2 is a flowchart of a decoding method according to an embodiment of the present application;
fig. 3 is a structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
At present, most of transaction systems in the domestic financial industry are based on the traditional general CPU architecture, the bottleneck exists in transaction speed increase, and the transaction requirement of ultralow time delay cannot be met. With the development of financial science and technology, various algorithm transactions and quantitative transactions are started, and the competition of pursuing lower transaction delay time in the financial industry is continuously upgraded, so that the competition becomes one of the core challenges of various financial institutions. Especially, in recent years, the comprehensive application of programmed trading in the capital market, the traditional software technology or the acceleration technology taking software as the core has difficulty in meeting the requirements of real-time processing and real-time response in the microsecond level. To this end, embodiments of the present invention provide a decoding system, a decoding method, an electronic device, and a storage medium, where the decoding system is configured to perform FAST decoding on FAST stream data, that is, decode data in FAST format into data similar to Financial Information eXchange protocol (FIX) format.
The decoding system of the embodiment of the invention can be applied to an FPGA (Field Programmable Gate Array), namely a Field Programmable Gate Array, and is an editable and customizable device. Due to the editable characteristic, the FPGA can almost realize any logic function, so that the FPGA has high parallelism and can simultaneously complete a plurality of operations in one clock cycle. Due to the customizable characteristic of the FPGA, the system can accurately control the processing time delay and has higher reaction speed. These features make FPGAs an important tool in the low latency requirements of the financial technology industry. The FPGA hardware acceleration platform is rapidly developed in the financial transaction market and accepted by the industry, and more functions, services and requirements need to be developed on the FPGA.
As shown in fig. 1, the decoding system includes: a data merging module 11 and at least two message decoding modules 12, wherein each message decoding module 12 corresponds to a decoding message type;
each message decoding module 12 is configured to decode FAST stream data of a corresponding decoding message type by using XML template data corresponding to a decoding message type of the message decoding module, so as to obtain decoding data of the corresponding decoding message type;
in practical application, the decoding system receives stream data of different decoding message types, and may distribute the stream data of different decoding message types to the message decoding modules 12 of corresponding decoding message types, and different decoding message modules may obtain XML template data of corresponding decoding message types, and further, when receiving a FAST stream data of the same type as its own decoding message, decode the FAST stream data according to the XML template data.
FAST Streaming data refers to Streaming data encoded using the FAST protocol, and the FAST (FIX attached for Streaming) protocol (Streaming FIX) is a binary encoding method for message-oriented Streaming data. To optimize FIX messages, the FAST encoding method reduces the size of the data stream in two levels. First, the concept of "domain operators" makes it possible to exploit the dependencies of data in a stream, eliminating redundant data. Second, the self-describable field length and a bitmap indicating whether a field exists are utilized in the serialization of the remaining data by binary encoding. The encoding is done according to a control structure called "template" (i.e. XML template data in embodiments of the invention). The template controls the encoding of a portion of the stream by specifying the order and structure of the fields, the field operators, and the binary encoding representation methods used by them.
The data merging module 11 is configured to merge the decoded data for each decoded message type to obtain merged decoded data (FIX data).
The data merging module 11 multiplexes the decoded data decoded by each message decoding module 12 into a message containing a set of tag + value merged decoded data, and outputs the message to the data processing module at the next stage (outside the decoding system).
In the embodiment of the present invention, at least two message decoding modules 12 decode FAST stream data of different decoding message types in parallel, and then merge decoded data obtained by decoding, so as to obtain merged decoded data. By parallel decoding of at least two message decoding modules 12, the data decoding speed is increased, the data decoding delay is reduced, and the decoding decoder optimally has 20 clock cycles for encoding delay under the condition of processing normal FAST data by benefiting from the parallel processing advantage of FPGA.
In still another embodiment of the present invention, the decoding system further includes: a decoding control module 13 as a previous stage input of the message decoding module 12, where the decoding control module 13 includes a first storage area for storing FAST stream data and a second storage area for storing XML template data, where the first storage area and the second storage area are both RAMs;
the first memory area is used for storing 64-bit data spliced after the stop bit of each decoded message type is removed by the stop bit detection module 14. The Sop and Eop signals are used for indicating the first beat data and the last beat data of a piece of message data; vld _ byte represents how many bytes in a beat of data are valid data; msg _ type is the message type number, and Sop is the data of PMap.
The second storage area mainly stores XML template data of each decoding message type, and stores control information such as domain operators, data type occupation in bitmaps, parameter indication domains (necessary domains or optional domains) and the like in the FAST protocol; xml _ verison stores the version of the whole XML, template ID is stored by template ID, and the configuration of each domain of several bits of Data stored in Data is stored, wherein 15-0 bit stores the domain ID, namely tag; 19-16 bits store decimal digits; 23-20 bits store the data type of the domain; 27-24 bit stores the operational character of the domain; 28 bits indicate that the field does not occupy a place in the PMap, and 30 bits and 29 bits are respectively a start mark and an end mark of the sequence; 31bit indicates whether the field is a required field or an optional field. Each starting address corresponds to the storage base address of each message in the XML RAM.
The decoding control module 13 is configured to write FAST stream data of different decoding message types into a preset first storage area, and write XML template data of different decoding message types into a preset second storage area;
in this embodiment of the present invention, after receiving FAST stream data of different decoding message types, the decoding control module 13 may write the FAST stream data of different decoding message types into the first storage area; furthermore, the decoding control module 13 may also write the XML template data into the second storage area in advance or in real time.
The FAST stream data and the XML template data are written into a first storage area and a second storage area for caching, so that the subsequent message decoding modules 12 can process the data as required, on one hand, the FAST stream data and the XML template data correspond to each other, and each message decoding module 12 decodes the data according to the domain sequence and the domain operational characters in the template; on the other hand, the decoding speed can be controlled.
The message decoding module 12 is further configured to generate, according to a decoding message type of the message decoding module, a first read/write control signal for reading FAST stream data of a corresponding decoding message type in the first storage area and a second read/write control signal for reading XML template data of a corresponding decoding message type in the second storage area;
in the embodiment of the present invention, the first read-write control signal and the second read-write control signal are used to control the output of the PMap bitmap data, FAST stream data and XML template data after the large end is converted into the small end.
Since FAST data is stream data, only one message decoding module 12 controls the first storage area and the second storage area at the same time, and different message types are decoded by one message decoding module 12.
The decoding control module 13 is further configured to read FAST stream data in the first storage area according to the first read-write control signal of each message decoding module 12, send the read FAST stream data to the message decoding module 12, read XML template data in the second storage area according to the second read-write control signal of each message decoding module 12, and send the read XML template data to the message decoding module 12.
The embodiment of the invention can realize the reading and writing of the FAST stream data in the first storage area and the XML template data in the second storage area through the decoding control module 13, realize the independent processing of the FAST stream data and the XML template data of different decoding message types, avoid the problem of decoding errors caused by confusion of different types of FAST stream data or XML template data, and improve the decoding efficiency of the FAST stream data of different message decoding types.
In still another embodiment of the present invention, the decoding system further includes: a stop bit detection module 14 as a preceding stage input of the decoding control module 13;
the stop bit detection module 14 is configured to receive FAST stream data of at least two decoding message types, identify a stop bit in the FAST stream data, remove the stop bit in the FAST stream data to obtain new FAST stream data, and write the obtained FAST stream data into the first storage area of the decoding control module 13.
In the embodiment of the present invention, the FAST stream data may be, for example, 128 bits, including 16 bytes, and may cover the length of each data type of FAST, so as to facilitate uniform processing of the invalid data types inside the FPGA.
The stop bit detection module 14 may identify the stop bit of each field data according to the highest bit of each byte in the 128-bit data, and store each data segment obtained after removing the stop bit into the first storage area through the decoding control module 13 according to the specific position of the stop bit, where the identifier of the first storage area may be, for example, FAST _ RAM, and the type is dual-port RAM.
In the embodiment of the present invention, the stop bit detection module 14 may detect and remove the stop bit in the FAST stream data, and write the FAST stream data with the stop bit removed into the first storage area, so as to store and decode the FAST stream data in the following process.
In still another embodiment of the present invention, the decoding system further includes: a command multiplexing module 15 located between the decoding control module 13 and the message decoding module 12;
the command multiplexing module 15 is configured to arbitrate and select the first read-write control signal and the second read-write control signal according to a type of a decoding message, and send the arbitrated and selected first read-write control signal and the arbitrated and selected second read-write control signal to the decoding control module 13;
the FAST stream data and the XML template data read by the decoding control module 13 are sent to the corresponding message decoding module 12.
Specifically, the command multiplexing module 15 is further configured to select a first read-write control signal and a second read-write control signal that request to read the same decoding message type, and send the selected first read-write control signal and the selected second read-write control signal to the decoding control module 13;
the FAST stream data and the XML template data of the same decoding message type read by the decoding control module 13 are sent to the corresponding message decoding module 12.
The command multiplexing module 15 provided in the embodiment of the present invention can arbitrate the first read-write control signal and the second read-write control signal to select the first read-write control signal and the second read-write control signal of the same decoding message type, so that the decoding control module 13 can read FAST stream data and XML template data of the same type based on the first read-write control signal and the second read-write control signal, and further decode the FAST stream data according to the XML template data.
In still another embodiment of the present invention, the decoding system further includes: a configuration table 16, where the configuration table 16 includes an offset of a field in the PMap, where the FAST operator is None, in the XML template data of a plurality of decoded message types, a base address of the XML template data of each decoded message type in the second storage area, and an interface address of the second storage area;
the message decoding module 12 is further configured to generate the second read/write control signal according to the configuration table 16;
the decoding control module 13 is further configured to write XML template data of different decoding message types into a preset second storage area according to the configuration table 16.
In the embodiment of the present invention, by setting the configuration table 16, when writing the XML template data in the second storage area, the relevant information of the XML template data can be recorded in the configuration table 16; when the decoding control module 13 needs to write the XML template data into the second storage area, the XML template data may be written into the second storage area according to the configuration table 16, and the embodiment of the present invention may change the working condition of the decoder by changing the configuration table 16.
In another embodiment of the present invention, there is also provided a decoding method, as shown in fig. 2, the decoding method including:
step S101, controlling at least two message decoding modules 12 to decode FAST stream data of corresponding decoding message types by using XML template data corresponding to the decoding message types of the message decoding modules, so as to obtain decoding data of corresponding decoding message types;
step S102, the control data merging module 11 merges the decoded data for each decoded message type to obtain merged decoded data.
In addition, since some fields in the FAST protocol are sometimes modified by the exchange or message types of different services are added, in order to quickly compatible and upgrade the existing system and not introduce new problems, in another embodiment of the present invention, the decoding method further includes:
in response to a trigger operation of a message decoding module 12 for adding or deleting any decoded message type, creating, deleting a message decoding module 12 corresponding to the decoded message type;
or, in response to a modification operation for modifying any decoded message type, modifying XML template data associated with the decoded message type.
Because in practical application, the exchange may continuously update the message template and increase the message type, through the embodiment of the invention, each time a message several code types are added, a message decoding module 12 can be added on the original basis and multiplexed into the original message decoding group, thereby enhancing the expansibility of the decoding system; moreover, when one message decoding type is modified, the decoding of the FAST stream data of the latest message decoding type can be completed without modifying the merged decoded data of the original message decoding module 12 before the message decoding type is modified and according to the content of the XML template data after the template modification, so that the addition and the modification of fields in the FAST protocol can be easily adapted, and the maintenance of a transaction system is convenient.
In another embodiment of the present invention, an electronic device is further provided, which includes a processor, a communication interface, a memory, and a communication bus, where the processor, the communication interface, and the memory complete communication with each other through the communication bus;
a memory for storing a computer program;
a processor, configured to implement the decoding method according to any of the foregoing method embodiments when executing a program stored in the memory.
In the electronic device provided in the embodiment of the present invention, the processor implements control of the at least two message decoding modules to decode the FAST stream data of the corresponding decoding message type by using the XML template data corresponding to the decoding message type of the processor by executing the program stored in the memory, so as to obtain the decoding data of the corresponding decoding message type, and the control data merging module merges each of the decoding data for each decoding message type, so as to obtain the merged decoding data. In the embodiment of the invention, at least two message decoding modules decode FAST stream data of different decoding message types in parallel, and then merge decoded data obtained by decoding to obtain merged decoded data. Through the parallel decoding of at least two message decoding modules, the data decoding speed is improved, and the data decoding delay is reduced.
The communication bus 1140 mentioned in the above electronic device may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus 1140 may be divided into an address bus, a data bus, a control bus, and the like. For ease of illustration, only one thick line is shown in FIG. 3, but this does not mean only one bus or one type of bus.
The communication interface 1120 is used for communication between the electronic device and other devices.
The memory 1130 may include a Random Access Memory (RAM), and may also include a non-volatile memory (non-volatile memory), such as at least one disk memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The processor 1110 may be a general-purpose processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; the integrated circuit may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA) or other programmable logic device, discrete gate or transistor logic device, or discrete hardware components.
In a further embodiment of the present invention, a computer-readable storage medium is also provided, on which a program of a decoding method is stored, which program, when being executed by a processor, realizes the steps of the decoding method of any one of the preceding method embodiments.
It is noted that, in this document, relational terms such as "first" and "second," and the like, may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising a … …" does not exclude the presence of another identical element in a process, method, article, or apparatus that comprises the element.
The foregoing are merely exemplary embodiments of the present invention, which enable those skilled in the art to understand or practice the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (9)
1. A decoding system, comprising: the data merging module and at least two message decoding modules, each message decoding module corresponds to a decoding message type;
each message decoding module is used for decoding FAST stream data of a corresponding decoding message type by using XML template data corresponding to the decoding message type of the message decoding module to obtain decoding data of the corresponding decoding message type;
the data merging module is configured to merge the decoding data for each decoding message type to obtain merged decoding data;
the decoding system further comprises: a decoding control module as a pre-stage input of the message decoding module, wherein the decoding control module comprises a first storage area for storing FAST stream data and a second storage area for storing XML template data;
the decoding control module is used for writing FAST stream data of different decoding message types into a preset first storage area and writing XML template data of different decoding message types into a preset second storage area;
the message decoding module is further configured to generate, according to a decoded message type of the message decoding module, a first read-write control signal for reading FAST stream data of a corresponding decoded message type in the first storage area and a second read-write control signal for reading XML template data of a corresponding decoded message type in the second storage area;
the decoding control module is further configured to read FAST stream data in the first storage area according to the first read-write control signal of each message decoding module, send the read FAST stream data to the message decoding module, read XML template data in the second storage area according to the second read-write control signal of each message decoding module, and send the read XML template data to the message decoding module.
2. The decoding system of claim 1, further comprising: a stop bit detection module as a preceding stage input of the decoding control module;
the stop bit detection module is used for receiving FAST stream data of at least two decoding message types, identifying the stop bit in the FAST stream data, removing the stop bit in the FAST stream data to obtain new FAST stream data, and writing the obtained FAST stream data into a first storage area of the decoding control module.
3. The decoding system of claim 1, further comprising: a command multiplexing module located between the decoding control module and the message decoding module;
the command multiplexing module is configured to arbitrate and select the first read-write control signal and the second read-write control signal according to a type of a decoding message, and send the arbitrated and selected first read-write control signal and second read-write control signal to the decoding control module;
and sending the FAST stream data and the XML template data read by the decoding control module to the corresponding message decoding module.
4. The decoding system of claim 3, wherein the command multiplexing module is further configured to select a first read-write control signal and a second read-write control signal that request to read the same decoded message type, and send the selected first read-write control signal and the selected second read-write control signal to the decoding control module;
and sending the FAST stream data and the XML template data of the same decoding message type read by the decoding control module to the corresponding message decoding module.
5. The decoding system of claim 1, further comprising: a configuration table, wherein the configuration table contains offsets of fields of FAST operators in None in the XML template data of a plurality of decoding message types in PMap, and base addresses of the XML template data of each decoding message type in the second storage area and interface addresses of the second storage area;
the message decoding module is further configured to generate the second read/write control signal according to the configuration table;
the decoding control module is further configured to write XML template data of different decoding message types into a preset second storage area according to the configuration table.
6. A decoding method applied to the decoding system according to any one of claims 1 to 5, the decoding method comprising:
controlling at least two message decoding modules to decode FAST stream data of corresponding decoding message types by using XML template data corresponding to the decoding message types of the message decoding modules to obtain decoding data of the corresponding decoding message types;
and the control data merging module merges the decoding data aiming at each decoding message type to obtain merged decoding data.
7. The decoding method of claim 6, further comprising:
in response to a trigger operation for adding or deleting a message decoding module of any decoded message type, creating or deleting a message decoding module of the decoded message type;
or, in response to a modification operation for modifying any decoded message type, modifying XML template data associated with the decoded message type.
8. An electronic device is characterized by comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory are communicated with each other through the communication bus;
a memory for storing a computer program;
a processor for implementing the decoding method according to claim 6 when executing the program stored in the memory.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium has stored thereon a program of a decoding method, which when executed by a processor implements the steps of the decoding method of claim 6.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110267992.4A CN113067581B (en) | 2021-03-11 | 2021-03-11 | Decoding system, decoding method, electronic device, and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110267992.4A CN113067581B (en) | 2021-03-11 | 2021-03-11 | Decoding system, decoding method, electronic device, and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN113067581A CN113067581A (en) | 2021-07-02 |
| CN113067581B true CN113067581B (en) | 2023-02-10 |
Family
ID=76560103
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110267992.4A Active CN113067581B (en) | 2021-03-11 | 2021-03-11 | Decoding system, decoding method, electronic device, and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN113067581B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020054638A1 (en) * | 2000-08-18 | 2002-05-09 | Tsuyoshi Hanamura | Coded signal separating and merging apparatus, method and computer program product |
| CN111625531A (en) * | 2019-02-28 | 2020-09-04 | 阿里巴巴集团控股有限公司 | Merging device based on programmable device, data merging method and database system |
| CN111967244A (en) * | 2020-07-30 | 2020-11-20 | 浪潮(北京)电子信息产业有限公司 | FAST protocol decoding method, device and equipment based on FPGA |
| CN112069772A (en) * | 2020-07-22 | 2020-12-11 | 深圳华云信息系统有限公司 | Data processing method and device based on FPGA, electronic equipment and storage medium |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH1131972A (en) * | 1997-05-15 | 1999-02-02 | Matsushita Electric Ind Co Ltd | Decoding device |
-
2021
- 2021-03-11 CN CN202110267992.4A patent/CN113067581B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020054638A1 (en) * | 2000-08-18 | 2002-05-09 | Tsuyoshi Hanamura | Coded signal separating and merging apparatus, method and computer program product |
| CN111625531A (en) * | 2019-02-28 | 2020-09-04 | 阿里巴巴集团控股有限公司 | Merging device based on programmable device, data merging method and database system |
| CN112069772A (en) * | 2020-07-22 | 2020-12-11 | 深圳华云信息系统有限公司 | Data processing method and device based on FPGA, electronic equipment and storage medium |
| CN111967244A (en) * | 2020-07-30 | 2020-11-20 | 浪潮(北京)电子信息产业有限公司 | FAST protocol decoding method, device and equipment based on FPGA |
Also Published As
| Publication number | Publication date |
|---|---|
| CN113067581A (en) | 2021-07-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US11163850B2 (en) | System, method and computer program product for data transfer management | |
| US9467511B2 (en) | Techniques for use of vendor defined messages to execute a command to access a storage device | |
| CN111930676B (en) | Method, device, system and storage medium for communication among multiple processors | |
| JP2008059554A (en) | Method for embedding protocol to implement system management bus | |
| CN105659274A (en) | Method and device for decoding data streams in reconfigurable platforms | |
| CN109542636B (en) | Data updating method and device | |
| CN111208933B (en) | Method, device, equipment and storage medium for data access | |
| TW200842593A (en) | Content-terminated DMA | |
| CN111131403A (en) | Message coding and decoding method and device for Internet of things equipment | |
| CN113067581B (en) | Decoding system, decoding method, electronic device, and storage medium | |
| JPWO2008068937A1 (en) | Data transfer control device and computer system | |
| CN111857868A (en) | Security data reading and writing method, device, equipment and computer readable storage medium | |
| CN111078294B (en) | Instruction processing method and device of processor and storage medium | |
| CN106033551A (en) | Data parsing method, apparatus and system thereof | |
| JP5341198B2 (en) | Bit inversion in communication interface | |
| CN111857571A (en) | Solid state disk physical block address distribution method, device, equipment and storage medium | |
| US8291270B2 (en) | Request processing device, request processing system, and access testing method | |
| CN110780855A (en) | Method, device and system for uniformly managing and controlling interface | |
| CN113179216B (en) | Remote configuration method of register, computer equipment and storage medium | |
| CN110764710A (en) | Data access method and storage system of low-delay and high-IOPS | |
| CN110548285A (en) | game communication control method and device, medium and electronic device | |
| CN115878351B (en) | Message transmission method and device, storage medium and electronic device | |
| CN117170722B (en) | Address discontinuity firmware upgrading method, device and system | |
| CN110321274B (en) | Application program testing method and device, computing equipment and storage medium | |
| CN114900566A (en) | Data communication method, device, electronic equipment and medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant | ||
| CP03 | Change of name, title or address |
Address after: 9th Floor, Block A, Shenzhen National Engineering Laboratory Building, No. 20, Gaoxin South 7th Road, High-tech Zone Community, Yuehai Street, Nanshan District, Shenzhen, Guangdong 518000 Patentee after: Shenzhen Huayun Information System Technology Co.,Ltd. Address before: No. 904, block a, national engineering laboratory building, Gaoxin South 7th road digital technology park, Yuehai street, Nanshan District, Shenzhen, Guangdong 518000 Patentee before: Shenzhen Huayun Information System Co.,Ltd. |
|
| CP03 | Change of name, title or address |