CN113067476A - ACOT step-down converter - Google Patents

ACOT step-down converter Download PDF

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Publication number
CN113067476A
CN113067476A CN202110252155.4A CN202110252155A CN113067476A CN 113067476 A CN113067476 A CN 113067476A CN 202110252155 A CN202110252155 A CN 202110252155A CN 113067476 A CN113067476 A CN 113067476A
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signal
ramp
capacitor
sawtooth wave
acot
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CN113067476B (en
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袁敏民
汪东
谢凌寒
刘钰
孙元良
孙思兵
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Wuxi Etek Microelectronics Co ltd
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Wuxi Etek Microelectronics Co ltd
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    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M3/00—Conversion of dc power input into dc power output
    • H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
    • H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
    • H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
    • H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
    • H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
    • H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
    • H—ELECTRICITY
    • H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
    • H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
    • H02M1/00—Details of apparatus for conversion
    • H02M1/08—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
    • H02M1/088—Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters for the simultaneous control of series or parallel connected semiconductor devices

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Dc-Dc Converters (AREA)

Abstract

The invention relates to a buck converter, and discloses an ACOT (adaptive Constant On time) buck converter. Comprises a buck converter and an ACOT controller connected with the buck converter; the ACOT controller includes: a voltage divider; the conduction time controller is used for providing conduction time for the high-order power tube; the sawtooth wave generator is used for extracting a sawtooth wave signal and a sawtooth wave valley value signal; a ramp generator for providing a ramp signal and a ramp peak signal; the comparator is used for providing a pulse signal according to the four signals, the feedback voltage and the reference voltage; the trigger is used for generating a high level control signal and a low level control signal according to the pulse number and the time control signal to control the buck converter. The sawtooth wave generator and the ramp generator both comprise a sample and hold circuit for sampling and holding the valley value of the sawtooth wave signal and the peak value of the ramp signal.

Description

ACOT step-down converter
Technical Field
The invention relates to a buck converter, in particular to an ACOT buck-type converter.
Background
In an Adaptive Constant On Time (ACOT) buck converter with a conventional structure, an error amplifier is generally required to improve the accuracy of an output voltage. However, due to the introduction of the error amplifier, the stability of the system becomes complicated, and the design difficulty is increased. In order to stabilize the system, a reasonable frequency compensation network must be added at the output of the error amplifier, where the compensation capacitance is large, thereby increasing the area.
The conventional error-free amplifier ACOT buck converter has a simple structure, and the loop stability is easy to control, but the accuracy of the output voltage is poor. Fig. 1 is a schematic diagram of a conventional error-free amplifier ACOT buck converter.
Disclosure of Invention
In order to solve the technical problems, the invention provides the following technical scheme: an ACOT buck converter comprises an ACOT controller and a buck converter, wherein the ACOT controller is connected with the buck converter and comprises a sawtooth wave generator and a ramp generator, the sawtooth wave generator is used for generating sawtooth wave signals and sawtooth wave valley signals, the ramp generator is used for generating ramp signals and ramp peak signals, the sawtooth wave generator and the ramp generator comprise a sampling and holding circuit, and the sampling and holding circuit is used for sampling and holding the valley values of the sawtooth wave signals and the peak values of the ramp signals.
Further, the ACOT controller further includes:
the voltage divider is connected with the output voltage of the buck converter and used for generating feedback voltage;
the output end of the on-time controller is connected with the trigger and is used for providing a time control signal;
the output end of the comparator is connected with the trigger and used for providing a pulse signal according to the provided sawtooth wave signal, the sawtooth wave valley signal, the ramp peak signal, the feedback voltage and the reference voltage;
and the input end of the trigger is connected with the conduction time controller and the comparator and is used for generating a high-level control signal and a low-level control signal according to the pulse signal and the time control signal to control the buck converter.
Further, the sawtooth generator further includes: sawtooth wave signal generation circuit, third electric capacity, sawtooth wave signal generation circuit receive the shortwave signal and generate the sawtooth wave signal, the sample hold circuit connect the sawtooth wave signal, insert high position quasi control signal and produce the sawtooth wave valley signal, third electric capacity one end connect the sawtooth wave valley signal, the other end ground connection.
Further, the sawtooth wave signal generating circuit includes: signal input part, first resistance, second resistance, third resistance, fourth resistance, first electric capacity, second electric capacity, third electric capacity, signal input part be used for inputing shortwave signal and connect the one end of first resistance, the other end of first resistance connect the one end of second resistance, the other end ground connection of second resistance, third resistance one end connect in the tie point of first resistance and second resistance, the one end of first electric capacity is connected to the other end, first electric capacity other end ground connection, fourth resistance one end connect in the tie point of third resistance and first electric capacity, the one end of second electric capacity is connected to the other end, second electric capacity other end ground connection, the voltage of second electric capacity be sawtooth wave signal.
Further, the ramp generator further comprises: the sampling circuit comprises a ramp signal generating circuit and a fifth capacitor, wherein the ramp signal generating circuit is connected with a high-level control signal to generate a ramp signal, the sampling and holding circuit is connected with the ramp signal and receives the high-level control signal to generate a ramp peak signal, one end of the fifth capacitor is connected with the ramp peak signal, and the other end of the fifth capacitor is grounded.
Further, the ramp signal generating circuit includes: the primary sampling module receives a high-level control signal to generate a high pulse signal, the grid electrode of the NMOS tube is connected with the high pulse signal, the drain electrode of the NMOS tube is connected with the current source, the source electrode of the NMOS tube is grounded, and the current source is connected with a supply voltage. The fourth capacitor is connected between the drain electrode and the source electrode of the NMOS tube, and the voltage of the fourth capacitor is a ramp signal.
Furthermore, the trigger is a set-reset trigger, a set end of the trigger is connected with the pulse signal, a reset end of the trigger is connected with the time control signal, a Q output end generates a high-level control signal, and a non-Q output end generates a low-level control signal.
Further, the voltage divider comprises a plurality of resistors electrically connected in series.
Further, the buck converter comprises: high-order driver, low level driver, high-order power tube, low level power tube, inductance, resistance, electric capacity, high-order driver connect the grid of high-order power tube, the drain of high-order power tube connect input voltage, the drain of low level power tube is connected to the source electrode, the grid of low level power tube connect the low level driver, source electrode ground connection, inductance one end connect in the tie point that high-order power tube source pole connects the low level power tube drain, other end series resistance, resistance parallel capacitance and ground connection, the tie point of inductance and resistance be output voltage.
The invention has the beneficial effects that: aiming at the problem of poor output voltage precision of the traditional error-free amplifier ACOT buck converter, the invention utilizes a sample-and-hold circuit to sample and hold the valley value of a sawtooth wave signal SW _ RAMP and the peak value of a SLOPE signal SLOPE to form a sawtooth wave valley value signal SW _ S _ H and a SLOPE peak value signal SLOPE _ S _ H, at the moment, a comparator is overturned, the sawtooth wave signal SW _ RAMP is equal to the sawtooth wave valley value signal SW _ S _ H, and the SLOPE signal SLOPE is equal to the SLOPE peak value signal SLOPE _ S _ H, so that the feedback voltage VFB is equal to a reference voltage VREF signal, and the precision of the output voltage is improved. Compared with a traditional error-free amplifier ACOT buck converter, the output voltage precision is improved. Compared with an ACOT buck converter with an error amplifier, the system stability is easy to control, and the circuit is relatively simple.
Drawings
FIG. 1 is a schematic diagram of a conventional ACOT buck converter without error amplifier;
FIG. 2 is a waveform diagram of a conventional ACOT buck converter without error amplifier;
FIG. 3 is a schematic structural diagram of an embodiment of the present invention;
FIG. 4 is a schematic structural diagram of a sawtooth generator according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a ramp generator according to an embodiment of the present invention;
FIG. 6 is a waveform diagram of an embodiment of the present invention.
Reference numbers in the figures:
11-ACOT controller; 12-a pressure reducing converter; 111-voltage divider; 112-a ramp generator; 113-a sawtooth generator; 114-a comparator; 115-on time controller; 116-a flip-flop; 121-high driver; 122-low drive; 21-a sawtooth signal generating circuit; 22-a sample-and-hold circuit; 32-a ramp signal generating circuit; rf1, Rf 2-voltage dividing resistors; SW-short wave signal; SW _ RAMP-sawtooth signal; SW _ S _ H-sawtooth valley signal; VFB-feedback voltage; VREF-reference voltage; SLOPE _ S _ H-ramp peak signal; SLOPE-ramp signal; t isON_END-a time control signal; a PWM-pulse signal; HSD _ ON-high level control signal; LSD _ ON-low level control signal; HSD _ FET-high power transistor; LSD _ FET-low level power tube; an L-inductor; RO-resistance; r1 — first resistance; r2 — second resistance; r3 — third resistance; r4-fourth resistor; c0-capacitance; c1 — first capacitance; c2 — second capacitance; c3 — third capacitance; c4-fourth capacitance; c5 — fifth capacitance; VOUT-output voltage; h _ PULSE-high PULSE signal; VDD-supply voltage; IB-current source; SW _ AVG-ramp mean signal; Δ VSW, Δ VFB-difference; VSLOP-E additional voltage.
Detailed Description
In order to make the technical means, the creation characteristics, the achievement purposes and the effects of the invention easy to understand, the invention is further described with the specific embodiments.
In the description of the present invention, it should be noted that the terms "upper", "lower", "inner", "outer", "front", "rear", "both ends", "one end", "the other end", and the like indicate orientations or positional relationships based on those shown in the drawings, and are only for convenience of description and simplicity of description, but do not indicate or imply that the referred device or element must have a specific orientation, be constructed in a specific orientation, and be operated, and thus, should not be construed as limiting the present invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.
In the description of the present invention, it is to be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "disposed," "connected," and the like are to be construed broadly, such as "connected," which may be fixedly connected, detachably connected, or integrally connected; can be mechanically or electrically connected; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
As shown in fig. 1, when the pulse signal PWM outputted from the comparator is high, the high level control signal HSD _ ON is high, the high level power transistor HSD _ FET is turned ON, and the inductor current IL increases. The time control signal T is applied until the time of the on-time controller is overON_ENDWhen the voltage is high, the HSD _ FET of the high-order power tube is turned off, the LSD _ FET of the low-order power tube is turned on, and the inductive current IL is reduced. Therefore, the output voltage VOUT decreases, the feedback voltage VFB decreases, the sawtooth wave signal SW _ RAMP decreases, the RAMP signal SLOPE of the jitter suppressor of the comparator 114 increases, and when the sum of the voltages at the positive phase input terminal of the comparator 114 is slightly higher (or can be considered to be approximately equal to) the sum of the negative phase input voltages, the pulse signal PWM output by the comparator 114 increases, the high level control signal HSD _ ON also increases, the low level power transistor LSD _ FET turns off, and the high level power transistor HSD _ FET turns ON.
In the conventional ACOT buck converter, when the pulse signal PWM becomes high, it means that the sum of the positive phase input voltages of the comparators is already slightly higher than the sum of the negative phase input voltages. As can be seen from fig. 2, the sawtooth wave signal SW _ RAMP at the negative input end is lower than the RAMP average signal SW _ AVG at the positive input end by the difference Δ VSW. In addition, the SLOPE signal SLOPE input at the non-inverting input terminal has an extra voltage VSLOPE (the extra voltage VSLOPE is added at the non-inverting input terminal to suppress the jitter of the SLOPE signal). Therefore, at the moment of comparator flipping, the feedback voltage VFB should be higher than the reference voltage VREF, so that it can be ensured that the sum of the voltages at the positive phase input terminals is equal to the sum of the voltages at the negative phase input terminals at the moment of comparator flipping. That is:
SW_AVG+VREF+VSLOPE＝SW_RAMP+VFB
ΔVFB＝VFB-VREF＝SW_AVG-SW_RAMP+VSLOPE
the value of feedback voltage VFB higher than reference voltage VREF can be found as:
ΔVFB＝ΔVSW+VSLOPE
ideally, the feedback voltage VFB should be equal to the reference voltage VREF. As can be seen from the above equation, the feedback voltage VFB is not equal to the reference voltage VREF. Due to the variation of the input/output voltage, the difference Δ VSW also varies, and the deviation of the feedback voltage VFB becomes uncontrollable.
In order to solve the above problem, the present invention provides an ACOT buck converter, which has a structure as shown in fig. 3, and includes an ACOT controller 11 and a buck converter 12, where the ACOT controller 11 is connected to the buck converter 12. The ACOT controller 11 includes a voltage divider 111, a conduction time controller 115, a sawtooth generator 113, a ramp generator 112, a comparator 114, and a flip-flop 116.
The input end of the voltage divider 111 is connected to the output voltage VOUT of the buck converter 12 for generating the feedback voltage VFB. The voltage divider 111 includes a plurality of resistors electrically connected in series; an output of the on-time controller 115 is connected to the flip-flop 114 for providing the time control signal TON_ENDDetermining the conduction time of the high-order power tube; the input end of the sawtooth wave generator 113 is connected to the trigger 116, and the output end is connected to the comparator 114, and is used for providing a sawtooth wave signal SW _ RAMP and a sawtooth wave valley signal SW _ S _ H; a ramp generator 112 having an input connected to a flip-flop 116, an output connected to a comparator 114,for providing a ramp signal SLOPE and a ramp peak signal SLOPE _ S _ H; the comparator 114 is preferably a six input comparator with three inputs for positive and negative phases. The positive phase input end is connected with the sawtooth wave valley signal SW _ S _ H, the reference voltage VREF and the SLOPE signal SLOPE, the negative phase input end is connected with the sawtooth wave signal SW _ RAMP, the feedback voltage VFB and the SLOPE peak value signal SLOPE _ S _ H, and the output end is connected with the trigger 116 and used for providing a pulse signal PWM according to the sawtooth wave signal SW _ RAMP, the sawtooth wave valley signal SW _ S _ H, the SLOPE signal SLOPE, the SLOPE peak value signal SLOPE _ S _ H, the feedback voltage VFB and the reference voltage VREF; the input terminal of the flip-flop 116 is connected to the on-time controller 115 and the comparator 114 for controlling the signal T according to the pulse signal PWM and the timeON_ENDTo generate a high level control signal HSD _ ON and a low level control signal LSD _ ON for controlling the buck converter. The flip-flop 116 is preferably a set-reset flip-flop, and the set terminal of the flip-flop 116 is connected to the pulse signal PWM and the reset terminal is connected to the time control signal TON_ENDThe Q output terminal generates a high level control signal HSD _ ON, and the non-Q output terminal generates a low level control signal LSD _ ON.
The sawtooth generator 113 and the RAMP generator 112 each include a sample-and-hold circuit 22, and the sample-and-hold circuit 22 is configured to sample and hold a valley value of the sawtooth signal SW _ RAMP and a peak value of the RAMP signal SLOPE. The sample and hold circuit 22 is prior art.
The buck converter 12 includes: the high-order power transistor comprises a high-order driver 121, a low-order driver 122, a high-order power transistor HSD _ FET, a low-order power transistor LSD _ FET, an inductor L, a resistor R0 and a capacitor C0, wherein the high-order driver 121 is connected with the grid electrode of the high-order power transistor HSD _ FET, the drain electrode of the high-order power transistor HSD _ FET is connected with an input voltage VIN, the source electrode of the high-order power transistor is connected with the drain electrode of the low-order power transistor LSD _ FET, the grid electrode of the low-order power transistor LSD _ FET is connected with the low-order driver 122, the source electrode of the low-order power transistor LSD _ FET is grounded, one end of the inductor L is connected with the connection point of the source electrode of the high-order power transistor HSD _ FET and the drain electrode of the low-order power transistor LSD _.
As shown in fig. 4, the sawtooth wave generator 113 further includes a sawtooth wave signal generating circuit 21 and a third capacitor C3, the sawtooth wave signal generating circuit 21 receives the short wave signal SW to generate a sawtooth wave signal SW _ RAMP, the sample-and-hold circuit 22 is connected to the sawtooth wave signal SW _ RAMP and connected to the high level control signal HSD _ ON to generate a sawtooth wave valley signal SW _ S _ H, one end of the third capacitor C3 is connected to the sawtooth wave valley signal SW _ S _ H, and the other end is grounded. The sawtooth wave signal generating circuit 21 includes a signal input terminal, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a first capacitor C1, a second capacitor C2, and a third capacitor C3, where the signal input terminal is used to input a shortwave signal SW and is connected to one end of the first resistor R1, the other end of the first resistor R1 is connected to one end of the second resistor R2, the other end of the second resistor R2 is grounded, one end of the third resistor R3 is connected to a connection point between the first resistor R1 and the second resistor R2, the other end of the third resistor R3 is connected to one end of the first capacitor C1, the other end of the first capacitor C1 is grounded, one end of the fourth resistor R4 is connected to a connection point between the third resistor R3 and the first capacitor C1, the other end of the third resistor R3 is connected to one end of the second capacitor C2, the second capacitor C2 is grounded, and the voltage of the.
When the high-level control signal HSD _ ON is low, the voltage of the second capacitor C2, i.e., the sawtooth wave signal SW _ RAMP, is sampled and held when the high-level control signal HSD _ ON is high, and the valley of the sawtooth wave signal SW _ RAMP is held in the third capacitor C3, forming the sawtooth wave valley signal SW _ S _ H.
As shown in fig. 5, the ramp generator 112 of the present invention further includes a ramp signal generating circuit 32, and a fifth capacitor C5, wherein the ramp signal generating circuit 32 turns ON the high level control signal HSD _ ON to generate the ramp signal SLOPE, the sample-and-hold circuit 22 is connected to the ramp signal SLOPE and receives the high level control signal HSD _ ON to generate the ramp peak signal SLOPE _ S _ H, and one end of the fifth capacitor C5 is connected to the ramp peak signal SLOPE _ S _ H, and the other end is grounded. The ramp signal generating circuit 32 includes: the primary sampling module 31 receives a high-level control signal HSD _ ON to generate a high PULSE signal H _ PULSE, the gate of the NMOS transistor M1 is connected to the high PULSE signal H _ PULSE, the drain is connected to the current source IB, the source is grounded, and the current source IB is connected to the supply voltage VDD. The fourth capacitor C4 is connected between the drain and the source of the NMOS transistor M1, and the junction of the source of the NMOS transistor M1 and the current source IB generates the ramp signal SLOPE.
When the high-level control signal HSD _ ON is high, a high PULSE signal H _ PULSE is generated by the one-time sampling module, and the NMOS transistor M1 is turned ON briefly, so as to clear the voltage of the fourth capacitor C4. Then, the NMOS transistor M1 turns off rapidly, and the voltage of the fourth capacitor C4 starts to rise slowly. The sample-and-hold circuit 22 in fig. 5 samples the signal SLOPE of C1 when the high-level control signal HSD _ ON is low, and holds the sampled signal in the fifth capacitor C5, i.e., the ramp peak signal SLOPE _ S _ H, when the high-level control signal HSD _ ON is high.
The relevant waveforms of the present invention are shown in fig. 6, when the comparator 114 is flipped, the sum of the voltages at the positive phase input terminals is equal to the sum of the voltages at the negative phase input terminals, i.e.:
SW_S_H+VREF+SLOPE＝SW_RAMP+VFB+SLOPE_S_H
as shown in fig. 6, when the high-level control signal HSD _ ON goes high, the sawtooth signal SW _ RAMP is equal to the sawtooth valley signal SW _ S _ H and the RAMP signal SLOPE is equal to the RAMP peak signal SLOPE _ S _ H due to the sample-and-hold technique, so the feedback voltage VFB is equal to the reference voltage VREF, and thus:
Figure BDA0002966496310000091
compared with the traditional error-free amplifier ACOT buck converter, the accuracy of the output voltage is improved.
The foregoing shows and describes the general principles and broad features of the present invention and advantages thereof. It will be understood by those skilled in the art that the present invention is not limited to the embodiments described above, which are described in the specification and illustrated only to illustrate the principle of the present invention, but that various changes and modifications may be made therein without departing from the spirit and scope of the present invention, which fall within the scope of the invention as claimed. The scope of the invention is defined by the appended claims and equivalents thereof.

Claims (9)

1. An ACOT buck converter is characterized by comprising an ACOT controller (11) and a buck converter (12), wherein the ACOT controller (11) is connected with the buck converter (12), the ACOT controller (11) comprises a sawtooth wave generator (113) and a RAMP generator (112), the sawtooth wave generator (113) is used for generating a sawtooth wave signal (SW _ RAMP) and a sawtooth wave valley signal (SW _ S _ H), the RAMP generator (112) is used for generating a RAMP Signal (SLOPE) and a RAMP peak signal (SLOPE _ S _ H), the sawtooth wave generator (113) and the RAMP generator (112) comprise a sample-and-hold circuit (22), and the sample-and-hold circuit (22) is used for sampling and holding the valley value of the sawtooth wave signal (SW _ RAMP) and the peak value of the RAMP Signal (SLOPE).
2. An ACOT buck-type converter according to claim 1, wherein the ACOT controller (11) further comprises:
a voltage divider (111) connected to the output Voltage (VOUT) of the buck converter (12) for generating a feedback Voltage (VFB);
an on-time controller (115) having an output connected to the flip-flop (114) for providing a time control signal (T)ON_END)；
A comparator (114), the output end of which is connected to the trigger (116), for providing a pulse signal (PWM) according to the provided sawtooth wave signal (SW _ RAMP), the sawtooth wave valley signal (SW _ S _ H), the RAMP Signal (SLOPE), the RAMP peak signal (SLOPE _ S _ H), the feedback Voltage (VFB) and the reference Voltage (VREF);
a flip-flop (116) having an input terminal connected to the on-time controller (115) and the comparator (114) for controlling the signal (T) according to the pulse signal (PWM) and the timeON_END) To generate a high level control signal (HSD _ ON) and a low level control signal (LSD _ ON) for controlling the buck converter (12).
3. An ACOT buck-type converter according to claim 1, wherein the sawtooth generator (113) further comprises: the sawtooth wave signal generating circuit (21) receives a short wave Signal (SW) to generate a sawtooth wave signal (SW _ RAMP), the sampling and holding circuit (22) is connected with the sawtooth wave signal (SW _ RAMP) and connected with a high-level control signal (HSD _ ON) to generate a sawtooth wave valley value signal (SW _ S _ H), one end of the third capacitor (C3) is connected with the sawtooth wave valley value signal (SW _ S _ H), and the other end of the third capacitor is grounded.
4. An ACOT buck converter according to claim 3, wherein the sawtooth signal generating circuit (21) comprises: the signal input end is used for inputting a short-wave Signal (SW) and is connected with one end of a first resistor (R1), the other end of the first resistor (R1) is connected with one end of a second resistor (R2), the other end of the second resistor (R2) is grounded, one end of a third resistor (R3) is connected with a connection point of the first resistor (R1) and the second resistor (R2), the other end of the third resistor (R1) is connected with one end of a first capacitor (C1), the other end of the first capacitor (C8) is grounded, one end of a fourth resistor (R6866) is connected with a connection point of the third resistor (R3) and the first capacitor (C1), and the other end of the fourth resistor (R3), the fourth resistor (R4), the first capacitor (R1), the second capacitor (C2) and the third capacitor (C3), the other end of the second capacitor (C2) is grounded, and the voltage of the second capacitor (C2) is a sawtooth wave signal (SW _ RAMP).
5. An ACOT buck-type converter according to claim 1, wherein the ramp generator (112) further comprises: the circuit comprises a ramp signal generating circuit (32) and a fifth capacitor (C5), wherein the ramp signal generating circuit (32) is connected with a high-level control signal (HSD _ ON) to generate a ramp Signal (SLOPE), the sampling and holding circuit (22) is connected with the ramp Signal (SLOPE) and receives the high-level control signal (HSD _ ON) to generate a ramp peak signal (SLOPE _ S _ H), one end of the fifth capacitor (C5) is connected with the ramp peak signal (SLOPE _ S _ H), and the other end of the fifth capacitor is grounded.
6. An ACOT buck-type converter according to claim 5, wherein the ramp signal generating circuit (32) comprises: the circuit comprises a primary sampling module (31), an NMOS tube (M1), a fourth capacitor (C4), a fifth capacitor (C5) and a current source (IB), wherein the primary sampling module (31) receives a high-level control signal (HSD _ ON) to generate a high PULSE signal (H _ PULSE), the grid electrode of the NMOS tube (M1) is connected with the high PULSE signal (H _ PULSE), the drain electrode of the NMOS tube is connected with the current source (IB), the source electrode of the NMOS tube is grounded, and the current source (IB) is connected with a supply Voltage (VDD). The fourth capacitor (C4) is connected between the drain and the source of the NMOS tube (M1), and the voltage of the fourth capacitor (C4) is a ramp Signal (SLOPE).
7. An ACOT buck-type converter according to claim 1, wherein the flip-flop (116) is a set-reset flip-flop having a set terminal connected to a pulse signal (PWM) and a reset terminal connected to a time control signal (T)ON_END) The Q output terminal generates a high-level control signal (HSD _ ON), and the non-Q output terminal generates a low-level control signal (LSD _ ON).
8. An ACOT buck converter according to claim 1, wherein the voltage divider (111) comprises a plurality of resistors electrically connected in series.
9. An ACOT buck-type converter according to any one of claims 1 to 8, wherein the buck converter (12) comprises: a high driver (121), a low driver (122), a high power transistor (HSD _ FET), a low power transistor (LSD _ FET), an inductor (L), a resistor (R0), and a capacitor (C0), the high-order driver (121) is connected with the grid electrode of a high-order power tube (HSD _ FET), the drain electrode of the high-order power tube (HSD _ FET) is connected with an input Voltage (VIN), the source electrode is connected with the drain electrode of a low-order power tube (LSD _ FET), the grid electrode of the low-level power tube (LSD _ FET) is connected with the low-level driver (122), the source electrode is grounded, one end of the inductor (L) is connected with the source electrode of the high-order power tube (HSD _ FET) and the drain electrode of the low-order power tube (LSD _ FET) and the other end is connected with the resistor (R0) in series, the resistor (R0) is connected with the capacitor (C0) in parallel and is grounded, and the connection point of the inductor (L) and the resistor (R0) is output Voltage (VOUT).
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Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110031948A1 (en) * 2009-08-05 2011-02-10 Min Chu Chien Dc-dc converter
US20110304308A1 (en) * 2010-06-14 2011-12-15 Richtek Technology Corporation Adaptive constant on time adjustment circuit and mathod for adaptively adjusting constant on time
US20110316508A1 (en) * 2010-06-28 2011-12-29 Kuang-Yao Cheng Digital Hybrid V2 Control for Buck Converters
US20150077083A1 (en) * 2013-09-17 2015-03-19 Upi Semiconductor Corp. Ramp signal generating method and generator thereof, and pulse width modulation signal generator
CN110545039A (en) * 2019-08-29 2019-12-06 杭州士兰微电子股份有限公司 switch converter and control circuit and control method thereof
CN111817562A (en) * 2020-07-08 2020-10-23 无锡力芯微电子股份有限公司 Buck type DC-DC converter
US20210050790A1 (en) * 2019-08-15 2021-02-18 Microchip Technology Incorporated Constant on-time buck converter with calibrated ripple injection having improved light load transient response and reduced output capacitor size

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20110031948A1 (en) * 2009-08-05 2011-02-10 Min Chu Chien Dc-dc converter
US20110304308A1 (en) * 2010-06-14 2011-12-15 Richtek Technology Corporation Adaptive constant on time adjustment circuit and mathod for adaptively adjusting constant on time
US20110316508A1 (en) * 2010-06-28 2011-12-29 Kuang-Yao Cheng Digital Hybrid V2 Control for Buck Converters
US20150077083A1 (en) * 2013-09-17 2015-03-19 Upi Semiconductor Corp. Ramp signal generating method and generator thereof, and pulse width modulation signal generator
US20210050790A1 (en) * 2019-08-15 2021-02-18 Microchip Technology Incorporated Constant on-time buck converter with calibrated ripple injection having improved light load transient response and reduced output capacitor size
CN110545039A (en) * 2019-08-29 2019-12-06 杭州士兰微电子股份有限公司 switch converter and control circuit and control method thereof
CN111817562A (en) * 2020-07-08 2020-10-23 无锡力芯微电子股份有限公司 Buck type DC-DC converter

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