CN113066790A - Semiconductor package device and method of manufacturing the same - Google Patents

Semiconductor package device and method of manufacturing the same Download PDF

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Publication number
CN113066790A
CN113066790A CN202110294933.6A CN202110294933A CN113066790A CN 113066790 A CN113066790 A CN 113066790A CN 202110294933 A CN202110294933 A CN 202110294933A CN 113066790 A CN113066790 A CN 113066790A
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chip
dummy
rewiring
line
layer
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刘旭唐
张皇贤
黄敏龙
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Advanced Semiconductor Engineering Inc
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Advanced Semiconductor Engineering Inc
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Priority to CN202110294933.6A priority Critical patent/CN113066790A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/35—Mechanical effects
    • H01L2924/351—Thermal stress
    • H01L2924/3511—Warping

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The present disclosure relates to a semiconductor package device and a method of manufacturing the same. The semiconductor package device includes: a rewiring layer including at least one layer of rewiring lines; the first chip and the second chip are positioned on the upper surface of the redistribution layer; there is a variation in height in the vertical direction of the rewiring lines between the first chip and the second chip. The semiconductor packaging device and the manufacturing method thereof increase the total length and the surface area of the rewiring circuit, improve the stress resistance of the rewiring circuit, and effectively avoid the breakage of the rewiring circuit between the first chip and the second chip, thereby improving the product yield.

Description

Semiconductor package device and method of manufacturing the same
Technical Field
The present disclosure relates to the field of semiconductor packaging devices, and more particularly, to a semiconductor packaging device and a method of manufacturing the same.
Background
The FOCoS (Fan Out Chip on Substrate) packaging technology is implemented by using Fan-Out composite chips on a typical ball grid array Substrate. It can provide a lower cost solution with practically better electrical and thermal performance than silicon interposer structures.
In the FOCoS package device, the thermal expansion Coefficients (CTE) of different materials are different, the deformation generated during temperature change is different, and the stress generated due to the inconsistency of the CTE cannot be directly released by the whole structure during the thermal cycle. Since a line between an ASIC (Application Specific Integrated Circuit) chip and an HBM (High Bandwidth Memory) chip is located in a stress concentration region, a break is liable to occur under the stress.
Therefore, it is necessary to provide a new technical solution for FOCoS packaging.
Disclosure of Invention
The present disclosure provides a semiconductor package device and a method of manufacturing the same.
In a first aspect, the present disclosure provides a semiconductor package device, comprising:
a rewiring layer including at least one layer of rewiring lines;
the first chip and the second chip are positioned on the upper surface of the redistribution layer;
there is a variation in height in the vertical direction of the rewiring lines between the first chip and the second chip.
In some alternative embodiments, a longitudinal cross-section of the rewiring line between the first chip and the second chip includes at least one angled segment.
In some alternative embodiments, a longitudinal cross-section of the rewiring line between the first chip and the second chip includes a wave-shaped portion including at least one high point, at least one low point, and a sloped segment between the high point and the low point.
In some optional embodiments, the first chip and the second chip are located on an upper surface of the rewiring line of an uppermost layer in the rewiring layer.
In some alternative embodiments, the wave form part extends into a corresponding vertical projection region of the first chip; or
The wave form part extends to the vertical projection area corresponding to the second chip.
In some optional embodiments, the redistribution layer further includes a dummy line located at a lowermost layer, the dummy line being used to form the height variation of the redistribution line between the first chip and the second chip.
In some optional embodiments, the dummy line comprises at least two dummy cells, the at least two dummy cells having longitudinal cross-sections corresponding to at least two different widths; or
The longitudinal cross-sections of the at least two dummy cells correspond to at least two different thicknesses.
In some optional embodiments, the dummy cells include smaller dummy cells having a width in longitudinal cross-section greater than 2 microns and less than 10 microns and larger dummy cells having a width in longitudinal cross-section greater than 10 microns and less than 50 microns; and
the thickness of the longitudinal cross-section of the smaller dummy cells is greater than 2 microns and less than 5 microns, and the thickness of the longitudinal cross-section of the larger dummy cells is 2 microns greater than the thickness of the longitudinal cross-section of the smaller dummy cells.
In some optional embodiments, a minimum distance between adjacent dummy cells in the dummy line is 2 microns.
In some optional embodiments, a first dielectric layer is disposed between the dummy line and the adjacent rewiring line, and a thickness of a longitudinal cross section of the first dielectric layer is greater than 2 micrometers and less than 8 micrometers.
In some alternative embodiments, the length of the wave-form portion is greater than 10 microns and less than 4 millimeters.
In some optional embodiments, the rewiring line between the first chip and the second chip is electrically connected to the first chip and the second chip, respectively.
In some optional embodiments, the first chip is an application specific integrated circuit chip and the second chip is a high bandwidth memory chip.
In some alternative embodiments, the rewiring line has at least one bend in the horizontal plane.
In some alternative embodiments, the rewiring line has a zigzag structure in a horizontal plane.
In a second aspect, the present disclosure provides a method of manufacturing a semiconductor package device, comprising:
forming a dummy line on a carrier, wherein the dummy line has a height variation in a vertical direction;
forming a first dielectric layer on the dummy line;
and forming at least one layer of rewiring line on the first dielectric layer to obtain a rewiring layer.
In some optional embodiments, after forming at least one layer of rewiring lines on the first dielectric layer to obtain a rewiring layer, the method further comprises:
and arranging a first chip and a second chip on the surface of the rewiring layer, wherein the rewiring line is at least partially positioned between the first chip and the second chip.
In some optional embodiments, the forming a dummy line on the carrier includes:
disposing a second dielectric layer on the carrier;
and forming at least two dummy units on the bottom second electric layer by electroplating to obtain the dummy circuit, wherein the longitudinal sections of the at least two dummy units correspond to at least two different thicknesses.
In some optional embodiments, the forming a dummy line on the carrier includes:
forming at least two dummy units on the carrier in an electroplating mode to obtain the dummy circuit, wherein the longitudinal sections of the at least two dummy units correspond to at least two different thicknesses; and
after forming at least one layer of rewiring lines on the first dielectric layer to obtain a rewiring layer, the method further comprises:
and turning over the semiconductor packaging device, and forming a second dielectric layer on the dummy circuit.
In the semiconductor packaging device and the manufacturing method thereof, the height of the rewiring circuit between the first chip and the second chip is changed in the vertical direction, the total length and the surface area of the rewiring circuit are increased, the stress resistance of the rewiring circuit is improved, the rewiring circuit between the first chip and the second chip can be effectively prevented from being broken, and the product yield is improved.
Drawings
Other features, objects and advantages of the disclosure will become more apparent upon reading of the following detailed description of non-limiting embodiments thereof, made with reference to the accompanying drawings in which:
FIGS. 1A and 1B are schematic diagrams of a semiconductor package device in the prior art;
fig. 2-6 are first through fifth schematic views of semiconductor packaging devices according to embodiments of the present invention;
fig. 7 and 8 are schematic views of a method of manufacturing a semiconductor package device according to an embodiment of the present invention.
Description of the symbols:
11. an ASIC chip; 12. an HBM chip; 13. a substrate; 14. a wiring portion; 100. a first chip; 200. a second chip; 240. a first conductive pad; 300. rewiring the line; 301. a wave-shaped portion left end; 302. a wave form portion right end; 310. an inclined section; 320. a high point; 330. a low point; 340. a second conductive pad; 400. welding flux; 500. a first dielectric layer; 510. a first conductive via; 600. a dummy line; 610. a larger dummy cell; 620. a smaller dummy cell; 700. a second dielectric layer; 710. a second conductive via; 800. and (3) a carrier.
Detailed Description
The following description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples, and the technical problems and effects solved by the present invention will be readily apparent to those skilled in the art from the description of the embodiments. It is to be understood that the specific embodiments described herein are merely illustrative of the relevant invention and not restrictive of the invention. In addition, for convenience of description, only portions related to the related invention are shown in the drawings.
It should be noted that the structures, proportions, and dimensions shown in the drawings and described in the specification are for the understanding and reading of the present disclosure, and are not intended to limit the scope of the present disclosure, which is defined by the claims and the appended claims, and therefore, they are not technically essential, and any structural modification, proportion change, or size adjustment should be within the scope of the present disclosure without affecting the function and achievement of the present disclosure. In addition, the terms "above", "first", "second" and "a" as used in the present specification are for the sake of clarity only, and are not intended to limit the scope of the present invention, and changes or modifications of the relative relationship thereof may be regarded as the scope of the present invention without substantial technical changes.
It should also be noted that the longitudinal section corresponding to the embodiment of the present disclosure may be a front view direction section, the transverse section may be a right view direction section, and the horizontal section may be a top view direction section.
In addition, the embodiments and features of the embodiments in the present disclosure may be combined with each other without conflict. The present disclosure will be described in detail below with reference to the accompanying drawings in conjunction with embodiments.
Fig. 1A and 1B are schematic views of a semiconductor package device in the related art. As shown in fig. 1A, in the conventional semiconductor package device, the ASIC chip 11 and the HBM chip 12 are both located on the base 13, and the wiring portion 14 is located between and electrically connects the ASIC chip 11 and the HBM chip 12. Since the semiconductor package device has different thermal expansion coefficients of its respective parts (e.g., chip, underfill material, and package material), and the amount of deformation caused by temperature change is different, the entire structure is bent, and internal stress is caused. Among them, the line portion 14 between the ASIC chip 11 and the HBM chip 12 is located in a stress concentration region, and a fracture phenomenon is likely to occur. The broken line region in fig. 1B shows a fracture phenomenon of the wiring portion 14.
Fig. 2-6 are first to fifth schematic views of semiconductor package devices according to embodiments of the present invention.
Fig. 2 shows a longitudinal section of the semiconductor package device in the present embodiment. As shown in fig. 2, the semiconductor package device in the present embodiment includes a rewiring layer, a first chip 100, and a second chip 200.
In this embodiment, the rewiring layer includes at least one layer of rewiring lines 300 for accomplishing the rearrangement of the electrical connection points. The redistribution trace 300 may be a metal material, such as copper, gold, silver, and the like.
In the present embodiment, the first chip 100 and the second chip 200 are located on the upper surface of the rewiring layer. The first chip 100 is, for example, an application specific integrated circuit chip, and the second chip 200 is, for example, a high bandwidth memory chip. In the case where the rewiring layer includes a plurality of rewiring lines 300, the first chip 100 and the second chip 200 are located on the upper surface of the rewiring line 300 of the uppermost layer in the rewiring layer.
In one example, the first conductive pad 240 on the second chip 200 and the second conductive pad 340 on the rerouting circuit 300 are connected by solder 400. Similarly, the conductive pads on the first chip 100 corresponding to the redistribution lines 300 are also connected by solder 400. Thus, the re-wiring lines 300 between the first chip 100 and the second chip 200 are electrically connected to the first chip 100 and the second chip 200, respectively.
In the present embodiment, there is a variation in height in the vertical direction of the rewiring line 300 between the first chip 100 and the second chip 200.
The upper drawing in fig. 3 is a plan view of the rewiring line 300, the lower drawing in fig. 3 is a longitudinal section of the rewiring line 300, and the dotted line in fig. 3 shows the correspondence between the plan view and the longitudinal section. As shown in fig. 3, a longitudinal cross-section of the re-routing line 300 between the first chip 100 and the second chip 200 includes at least one inclined section 310. The inclined section 310 is located between a high point 320 and a low point 330. The plurality of high points 320 and the plurality of low points 330 are staggered and connected by the inclined section 310 to form a wave-shaped portion as a whole. It should be noted that the wavy portion in the drawings has a break angle, and the wavy portion in the actual structure has a smooth transition.
In the semiconductor package device of the embodiment, the height of the redistribution trace 300 between the first chip 100 and the second chip 200 varies in the vertical direction, so that the total length and the surface area of the redistribution trace 300 are increased, the stress resistance of the redistribution trace 300 is improved, the redistribution trace 300 between the first chip 100 and the second chip 200 can be effectively prevented from being broken, and the product yield is improved.
In one example, as shown in fig. 2, the wave-shaped portion extends into the corresponding vertical projection area of the first chip 100, and the left end 301 of the wave-shaped portion exceeds the right edge of the first chip 100. The wave-shaped portion also extends into the corresponding vertical projection area of the second chip 200, and the right end 302 of the wave-shaped portion exceeds the left edge of the second chip 200. Thus, it is advantageous to ensure that the rewiring line 300 between the first chip 100 and the second chip 200 is entirely in a wave shape, and to avoid a fragile portion, thereby further reducing the possibility of breakage of the rewiring line 300 between the first chip 100 and the second chip 200.
In one example, as shown in fig. 5, the rewiring layer further includes a dummy line 600 located at the lowermost layer, and the dummy line 600 is used to form a height variation of the rewiring line 300 between the first chip 100 and the second chip 200. The dummy line 600 includes at least two dummy cells, such as a larger dummy cell 610 and a smaller dummy cell 620. The longitudinal cross-sections of the larger dummy cell 610 and the smaller dummy cell 620 correspond to different widths, and the longitudinal cross-sections of the larger dummy cell 610 and the smaller dummy cell 620 correspond to different thicknesses. Different cells in the dummy line 600 may be separated from each other. The dummy line 600 is used to provide a plurality of surfaces having different heights, thereby forming a height variation of the re-routing line 300.
In one example, as shown in fig. 5, a first dielectric layer 500 may be further disposed between the dummy line 600 and the adjacent re-routing line 300. A first conductive via 510 is disposed on the first dielectric layer 500. The first conductive via 510 electrically connects an end cell (e.g., a left end cell or a right end cell in fig. 5) of the dummy line 600 and the re-wiring line 300. In the manufacturing process, the first dielectric layer 500 may vary with the height of the dummy line 600, thereby forming a wavy surface. On this basis, the re-wiring line 300 may be formed on the surface of the first dielectric layer 500, thereby achieving a height variation of the re-wiring line 300.
A second dielectric layer 700 may also be disposed under the dummy line 600. A second conductive via 710 is disposed on the second dielectric layer 700. The second conductive via 710 is electrically connected to the end unit of the dummy line 600. The re-routing wire 300 may be electrically connected to other wire structures located under the second dielectric layer 700 through the first conductive via 510 and the second conductive via 710.
In one example, as shown in fig. 6, the width a of the longitudinal cross-section of the smaller dummy cell 620 may be greater than 2 microns and less than 10 microns. The width C of the longitudinal cross-section of the larger dummy cell 610 may be greater than 10 microns and less than 50 microns. The thickness E of the longitudinal cross-section of the smaller dummy cells 620 may be greater than 2 microns and less than 5 microns. The thickness F of the longitudinal cross-section of the larger dummy cell 610 may be 2 microns greater than the thickness of the longitudinal cross-section of the smaller dummy cell 620. The minimum distance B between adjacent larger and smaller dummy cells 610, 620 may be 2 microns. The thickness G of the longitudinal cross-section of the first dielectric layer 500 may be greater than 2 microns and less than 8 microns. The length D of the wave form portion may be greater than 10 microns and less than 4 millimeters.
Fig. 4 shows a top view of a rewired line 300 in one example. As shown in fig. 4, the rewiring line 300 has at least one bend in the horizontal plane. More specifically, the rewiring line 300 has a zigzag structure in the horizontal plane. Therefore, the redistribution trace 300 in fig. 4 has both height variation in the vertical plane and bending in the horizontal plane, which is beneficial to further increase the total length and surface area of the redistribution trace 300 and reduce the possibility of breakage of the redistribution trace 300 between the first chip 100 and the second chip 200.
The present embodiment also provides a method of manufacturing a semiconductor package device.
Fig. 7 shows a first embodiment of a method of manufacturing a semiconductor package device. As shown in fig. 7, first, a second dielectric layer 700 is disposed on a carrier 800. Next, at least two dummy cells are formed on the bottom second electrical layer by electroplating to obtain a dummy line 600, wherein the longitudinal cross-sections of the at least two dummy cells correspond to at least two different thicknesses. Thereafter, a first dielectric layer 500 is formed on the dummy line 600. Finally, at least one layer of re-routing lines 300 is formed on the first dielectric layer 500 to obtain a re-routing layer.
Fig. 8 shows a second embodiment of a method of manufacturing a semiconductor package device. As shown in fig. 8, at least two dummy cells are first formed on a carrier 800 by electroplating to obtain a dummy line 600, wherein the longitudinal cross-sections of the at least two dummy cells correspond to at least two different thicknesses. Next, a first dielectric layer 500 is formed on the dummy line 600. Thereafter, at least one layer of re-wiring lines 300 is formed on the first dielectric layer 500 to obtain a re-wiring layer. Finally, the semiconductor package device is turned over, and a second dielectric layer 700 is formed on the dummy line 600.
Referring to fig. 7 and 8, since the order of forming the second dielectric layer 700 is different in the two embodiments, the aperture variation tendency of the second conductive via 710 formed by the two embodiments is opposite. In fig. 7, the pore diameter variation tendency of the second conductive via 710 is the same as that of the first conductive via 510. In fig. 8, the trend of the aperture of the second conductive via 710 is opposite to the trend of the aperture of the first conductive via 510.
For the embodiments in fig. 7 and 8, after obtaining the rewiring layer, the first chip 100 and the second chip 200 may be further disposed on the surface of the rewiring layer, wherein the rewiring line 300 is at least partially located between the first chip 100 and the second chip 200. Thus, a complete FOCoS package can be obtained.
The method for manufacturing the semiconductor package device in this embodiment can achieve similar technical effects to those of the semiconductor package device described above, and will not be described herein again.
While the present disclosure has been described and illustrated with reference to particular embodiments thereof, such description and illustration are not intended to limit the present disclosure. It will be clearly understood by those skilled in the art that various changes may be made and equivalents may be substituted for elements thereof without departing from the true spirit and scope of the present disclosure as defined by the appended claims. The illustrations may not be drawn to scale. There may be a difference between the technical reproduction in the present disclosure and the actual device due to variables in the manufacturing process and the like. There may be other embodiments of the disclosure that are not specifically illustrated. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method, or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the claims appended hereto. Although the methods disclosed herein have been described with reference to particular operations performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form equivalent methods without departing from the teachings of the present disclosure. Accordingly, unless specifically indicated herein, the order and grouping of the operations is not a limitation of the present disclosure.

Claims (18)

1. A semiconductor package device, comprising:
a rewiring layer including at least one layer of rewiring lines;
the first chip and the second chip are positioned on the upper surface of the redistribution layer;
there is a variation in height in the vertical direction of the rewiring lines between the first chip and the second chip.
2. The semiconductor package device of claim 1, wherein a longitudinal cross-section of the rewiring line between the first chip and the second chip comprises at least one angled segment.
3. The semiconductor package device of claim 1, wherein a longitudinal cross-section of the rewiring line between the first chip and the second chip comprises a wave-shaped portion comprising at least one high point, at least one low point, and a sloped segment between the high and low points.
4. The semiconductor package device according to claim 1, wherein the first chip and the second chip are located on an upper surface of the rewiring line of an uppermost layer in the rewiring layer.
5. The semiconductor package device of claim 3, wherein the wave-shaped portion extends into a corresponding vertical projection region of the first chip; or
The wave form part extends to the vertical projection area corresponding to the second chip.
6. The semiconductor package device of claim 1, wherein the redistribution layer further comprises a dummy line located at a lower layer, the dummy line for forming the height variation of the redistribution line between the first chip and the second chip.
7. The semiconductor package device of claim 6, wherein the dummy line comprises at least two dummy cells, a longitudinal cross-section of the at least two dummy cells corresponding to at least two different widths; or
The longitudinal cross-sections of the at least two dummy cells correspond to at least two different thicknesses.
8. The semiconductor package device of claim 7, wherein the dummy cells include smaller dummy cells having a longitudinal cross-section greater than 2 microns and less than 10 microns wide and larger dummy cells having a longitudinal cross-section greater than 10 microns and less than 50 microns wide; and
the thickness of the longitudinal cross-section of the smaller dummy cells is greater than 2 microns and less than 5 microns, and the thickness of the longitudinal cross-section of the larger dummy cells is 2 microns greater than the thickness of the longitudinal cross-section of the smaller dummy cells.
9. The semiconductor package device of claim 7, wherein a minimum distance between adjacent ones of the dummy cells in the dummy line is 2 microns.
10. The semiconductor package device of claim 7, wherein a first dielectric layer is disposed between the dummy line and the adjacent rewiring line, the first dielectric layer having a thickness in longitudinal cross-section greater than 2 microns and less than 8 microns.
11. The semiconductor package device of claim 5, wherein the length of the wave-shaped portion is greater than 10 microns and less than 4 millimeters.
12. The semiconductor package device of any one of claims 1-11, wherein the rewiring lines between the first chip and the second chip are electrically connected to the first chip and the second chip, respectively.
13. The semiconductor package device of any of claims 1-11, wherein the redistribution line has at least one bend in a horizontal plane.
14. The semiconductor package device of claim 13, wherein the rerouting line has a zigzag structure in a horizontal plane.
15. A method of manufacturing a semiconductor package device, comprising:
forming a dummy line on a carrier, wherein the dummy line has a height variation in a vertical direction;
forming a first dielectric layer on the dummy line;
and forming at least one layer of rewiring line on the first dielectric layer to obtain a rewiring layer.
16. The method of claim 15, wherein after forming at least one layer of rewiring lines on the first dielectric layer to obtain a rewiring layer, the method further comprises:
and arranging a first chip and a second chip on the surface of the rewiring layer, wherein the rewiring line is at least partially positioned between the first chip and the second chip.
17. The method of claim 15, wherein the forming a dummy line on a carrier comprises:
disposing a second dielectric layer on the carrier;
and forming at least two dummy units on the bottom second electric layer by electroplating to obtain the dummy circuit, wherein the longitudinal sections of the at least two dummy units correspond to at least two different thicknesses.
18. The method of claim 15, wherein the forming a dummy line on a carrier comprises:
forming at least two dummy units on the carrier in an electroplating mode to obtain the dummy circuit, wherein the longitudinal sections of the at least two dummy units correspond to at least two different thicknesses; and
after forming at least one layer of rewiring lines on the first dielectric layer to obtain a rewiring layer, the method further comprises:
and turning over the semiconductor packaging device, and forming a second dielectric layer on the dummy circuit.
CN202110294933.6A 2021-03-19 2021-03-19 Semiconductor package device and method of manufacturing the same Pending CN113066790A (en)

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GB2619868A (en) * 2022-01-14 2023-12-20 Guangdong Brunp Recycling Technology Co Ltd Silicon-carbon negative electrode material, and preparation method therefor and use thereof

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2619868A (en) * 2022-01-14 2023-12-20 Guangdong Brunp Recycling Technology Co Ltd Silicon-carbon negative electrode material, and preparation method therefor and use thereof

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