CN113066735B - Method for realizing high-resistance high-precision resistor - Google Patents
Method for realizing high-resistance high-precision resistor Download PDFInfo
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- CN113066735B CN113066735B CN202110302684.0A CN202110302684A CN113066735B CN 113066735 B CN113066735 B CN 113066735B CN 202110302684 A CN202110302684 A CN 202110302684A CN 113066735 B CN113066735 B CN 113066735B
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Abstract
The invention provides a method for realizing a high-resistance high-precision resistor, which comprises the following steps: step 1: depositing a polysilicon layer on the multi-layer dielectric body of the polysilicon resistor, isolating the polysilicon layer from the substrate and the integrated circuit elements; step 2: carrying out high-concentration ion doping on a doped region of the polycrystalline silicon layer, and forming a polycrystalline silicon region by adopting a photoetching process to obtain a first resistor; and step 3: after depositing a metal layer of the resistor, photoetching, contacting with the highly alloyed region, and annealing at a preset temperature to obtain a second resistor; and 4, step 4: and performing qualification verification on the second resistor, if the verification is successful, judging that the second resistor is a high-resistance high-precision resistor, and if not, performing correction verification on the second resistor. By doping and annealing the resistor after the metallization formation, it is convenient to improve the accuracy of the high sheet resistance of the obtained polysilicon resistor, and by performing qualification verification thereof, it is convenient to further ensure the high accuracy thereof.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for realizing a high-resistance high-precision resistor.
Background
For the production of high resistance high precision resistors, polysilicon resistors are commonly used as individual components or as part of an integrated circuit. Such as a PN junction resistor production method, which comprises the process steps of growing an n-type epitaxial layer on a p-type substrate, growing an n-type epitaxial layer on the p-type substrate, dividing the epitaxial layer into islands by insulated p-type regions, and forming p-type diffusion resistors and n-type feed regions with high impurity concentration in the islands. However, this production method has the following disadvantages due to the need to isolate the resistor from other components on the integrated circuit, and further due to the p-n junction on the resistor structure:
1) the occupied area of the resistor is large;
2) there is a large parasitic capacitance within the resistor;
3) the maximum achievable surface resistance is limited by impurities in the epitaxial film;
the other polysilicon resistor production mode comprises the steps of growing a resistor layer with a certain thickness on the surface of a substrate, wherein the resistor layer has a standard polysilicon grain structure; the polysilicon layer is oxidized, the grain boundary inside the polysilicon layer is separated by the formation of silicon oxide, and the resistor body is formed by the subsequent photolithography technique. However, in this method, the resistance of the polysilicon resistor greatly depends on the grain size, which may be different in each deposition process of polysilicon, and on the temperature gradient on the substrate in the oxidation process. As a result, this method cannot ensure an accurate high surface resistance of the obtained polycrystalline silicon layer.
In technical essence, the closest approach to the above mentioned solution is a method of manufacturing a polysilicon resistor as part of an integrated circuit, which method comprises coating a polysilicon layer, doping with N-type impurity ions and forming the gate of an NMOS transistor in one process, and then annealing. However, this method also cannot obtain a high surface resistance of a resistor with high accuracy because a high temperature operation is employed after forming the polysilicon resistor.
Therefore, the invention provides a method for realizing a high-resistance high-precision resistor.
Disclosure of Invention
The invention provides a method for realizing a high-resistance high-precision resistor, which is used for doping and annealing the resistor after metallization, so that the precision of the high surface resistance of the obtained polycrystalline silicon resistor is improved conveniently, and the high precision of the polycrystalline silicon resistor is further ensured conveniently through qualification verification.
The invention provides a method for realizing a high-resistance high-precision resistor, which comprises the following steps:
step 1: depositing a polysilicon layer on the multi-layer dielectric body of the polysilicon resistor, isolating the polysilicon layer from the substrate and the integrated circuit elements;
step 2: carrying out high-concentration ion doping on the doped region of the polycrystalline silicon layer, and forming a polycrystalline silicon region by adopting a photoetching process to obtain a first resistor;
and step 3: after depositing the metal layer of the resistor, photoetching, contacting with the highly alloyed region, and annealing at a preset temperature to obtain a second resistor;
and 4, step 4: and performing qualification verification on the second resistor, if the verification is successful, judging that the second resistor is a high-resistance high-precision resistor, and if not, performing correction verification on the second resistor.
In one possible way of realisation,
in step 2, the high-concentration ion doping of the doped region of the polysilicon layer is performed after the metallization of the polysilicon resistor, and the high-concentration ion doping of the doped region of the polysilicon layer includes:
determining a grain size of the first resistor and, based on a preset database, determining a dopant amount associated with the grain size;
and carrying out ion doping on the doped region of the polycrystalline silicon layer according to the doping amount.
In one possible way of realisation,
the preset temperature is in the range of (250 ℃ and 850 ℃).
In one possible way of realisation,
and the absolute value of the difference between the depth of the doped region in the polycrystalline silicon layer and the thickness of the polycrystalline silicon layer is smaller than a preset value.
In one possible way of realisation,
prior to determining the grain size of the first resistor, comprising:
determining a crystal region of the first resistor and dividing the crystal region into a peripheral region and an inner region;
performing diffraction measurement on the peripheral area to obtain diffraction information, analyzing abnormal information in the diffraction information according to a standard diffraction spectrum, and performing first marking on abnormal points in the peripheral area according to the abnormal information;
meanwhile, determining the size information of the crystal grains under the first marked abnormal point, and screening all first points of which the size information is larger than a preset size;
determining the point position information of each first point, and determining an arrangement pattern formed based on the first points according to the point position information;
judging whether the arrangement pattern meets a preset pattern standard or not based on a preset database, and if so, determining the occupation area of the pattern area of the arrangement pattern in the peripheral area;
otherwise, regarding the first point as an invalid point;
scanning and measuring the internal area to obtain scanning information, constructing a scanning array, screening abnormal points existing in the scanning array, and determining the current position of the abnormal points;
when the current positions are all regarded as invalid positions, the abnormal points are removed, and uniformity detection is carried out on the remaining points in the scanning array;
simultaneously, determining crystal grains on the outermost layer of the adjacent part of the external area and the internal area, and judging the stress direction of the crystal grains on the outermost layer of the adjacent part and the quantity difference of the crystal grains on the two layers in the process from the outside to the inside;
determining the distribution trend of the crystal grains on the two layers according to the judgment result;
judging whether crystal grains existing in a crystal region of the first resistor are effective or not according to the occupied area, the uniformity detection result and the distribution trend;
if valid, the first resistor is retained.
In one possible way of realisation,
after the first resistor is reserved, the method further comprises the following steps:
performing uniform area segmentation on the first resistor, acquiring a plurality of sub-areas, and determining the diameter of each crystal grain existing on each sub-area;
dividing the diameters of grains existing in each sub-area to obtain a large grain set, a medium grain set and a small grain set, and simultaneously determining the number of first grains of the large grain set, the number of second grains of the medium grain set and the number of third grains of the small grain set;
determining the area weight of the sub-area and the position weight of each crystal grain in the sub-area based on a standard position distribution library;
calculating a first distribution value F1 of a large crystal grain set, a second distribution value F2 of a medium crystal grain set and a third distribution value F3 of a small crystal grain set in a corresponding sub-area according to the area weight, the position weight of each crystal grain and the number of corresponding crystal grains based on the following formula;
wherein j takes the value of 1, 2, 3; when j is 1, Fj represents a first distribution value F1 of the large crystal grain set; when j is 2, Fj represents a second distribution value F2 of the medium grain set; when j is 3, Fj represents a third distribution value F3 of the small crystal grain set; ij represents the ith crystal grain in the total crystal grains Ij in the jth crystal grain set; a isijRepresenting the position weight of the ith crystal grain in the jth crystal grain set; alpha is alphaijThe position correction value of the ith crystal grain in the jth crystal grain set is represented, and the value range is [0.8, 1.2 ]]；sijThe grain volume of the ith grain in the jth grain set is represented; a denotes the region volume of the corresponding sub-region; ij represents the total number of the j-th crystal grains; Δ j represents the invalid distribution proportion of the jth crystal grain set based on the subareas, and the value is (0, 1);
calculating a corresponding average distribution value X based on the first distribution value, the second distribution value and the third distribution value and the following formula, determining a corresponding average distribution capability according to a distribution capability table, and further obtaining an average grain size of a corresponding sub-area according to a capability grain mapping table;
wherein χ 1 represents a position distribution weight value of the large grain set; chi 2 represents the position distribution weight value of the medium grain set; χ 3 represents a position distribution weight value of the small crystal grain set; r isi1Represents the grain radius of the ith grain in the large grain set; r isi2Represents the grain radius of the ith grain in the middle grain set; r isi3Represents the grain radius of the ith grain in the small grain set;
obtaining the grain size of the first resistor according to the average grain size of each subarea and the incidence relation between each subarea;
determining a dopant amount associated with the grain size based on a predetermined database.
In one possible way of realisation,
in step 4, the second resistor is qualified, and the method includes:
determining a first voltage and a second voltage for testing based on a semiconductor process for manufacturing the second resistor;
performing a first voltage test on the second resistor, monitoring a first actually generated voltage based on the second resistor, adjusting the first voltage to be a second voltage when capturing a time point that is greater than a preset voltage in the actually generated voltage, and continuing to monitor a second actually generated voltage based on the second resistor based on the time point;
acquiring a first temperature change of the second resistor based on a first actual generated voltage and a second temperature change of the second resistor based on a second actual generated voltage;
obtaining an adjustment voltage amount of the first voltage based on a voltage difference value between the second voltage and the first voltage, the first temperature change and the second temperature change, and obtaining a third voltage;
testing the second resistor according to the third voltage, and if a time point greater than a preset voltage still exists in the testing process, judging that the second resistor is unqualified;
otherwise, the second resistor is determined to be a high-resistance high-precision resistor.
In one possible way of realisation,
after the second resistor is judged to be unqualified, performing correction verification on the second resistor, wherein the correction verification comprises the following steps:
determining the area space of the doped area, and determining the space filling degree of high-concentration ion doping in the area space;
when the space filling degree is greater than the preset filling degree, judging the filling uniformity of the area space;
otherwise, performing filling verification on the second resistor;
when the filling uniformity is smaller than the preset uniformity, carrying out uniformity verification on the second resistor;
otherwise, respectively determining the voltage variation and the temperature gradient before and after doping, and performing preset verification on the voltage resistor.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.
Drawings
The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is an epitaxial layer with a dielectric layer and a polysilicon layer deposited thereon according to an embodiment of the present invention;
FIG. 2 is a structure of the present invention showing the addition of high alloy regions to the polysilicon layer of FIG. 1;
FIG. 3 is a cross-sectional view of a polysilicon resistor area formed after photolithography and etching in accordance with the present invention;
FIG. 4 shows a structure of a formed polysilicon region according to the present invention;
FIG. 5 shows a polysilicon resistor in accordance with the present invention;
FIG. 6 is a process flow for growing a thin film of a polysilicon resistor in accordance with the present invention;
FIG. 7 is a process flow of a highly doped region of a polysilicon resistor according to the present invention;
FIG. 8 illustrates a polysilicon resistor area process flow for a polysilicon resistor of the present invention;
FIG. 9 is a process flow for depositing a metal contact layer for a polysilicon resistor in accordance with the present invention;
FIG. 10 is a process flow of a polysilicon resistor basic structure of a polysilicon resistor according to the present invention;
FIG. 11 is a flow chart of a method for implementing a high resistance high precision resistor in an embodiment of the present invention;
fig. 12 is a structural view of a crystal region in the embodiment of the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Example 1:
the invention provides a method for realizing a high-resistance high-precision resistor, which comprises the following steps of:
step 1: depositing a polysilicon layer on the multi-layer dielectric body of the polysilicon resistor, isolating the polysilicon layer from the substrate and the integrated circuit elements;
step 2: carrying out high-concentration ion doping on the doped region of the polycrystalline silicon layer, and forming a polycrystalline silicon region by adopting a photoetching process to obtain a first resistor;
and step 3: after depositing the metal layer of the resistor, photoetching, contacting with the highly alloyed region, and annealing at a preset temperature to obtain a second resistor;
and 4, step 4: and performing qualification verification on the second resistor, if the verification is successful, judging that the second resistor is a high-resistance high-precision resistor, and if not, performing correction verification on the second resistor.
In this embodiment, in a method of forming a high resistance polysilicon resistor, includes depositing a polysilicon layer on a dielectric body, isolating it from a substrate and integrated circuit elements; ion doping the resistor contact area with a large amount of ions; forming a polycrystalline silicon region by using a photoetching process to obtain a resistor; the metal layer is deposited and then lithographically patterned to form contacts to the highly alloyed region, the doping of the resistor body is performed after the metallization, and the annealing is performed at a relatively low temperature (250 c-850 c) after the alloying is completed.
Since annealing is performed only at a relatively low temperature after ion doping of the resistor body, impurities penetrate into the polysilicon layer only within a limited depth, and thus the reproducibility of the surface resistance value of the resistor is drastically increased. For example, in order to obtain a polysilicon resistor having a thickness of 0.2 μm and a sheet resistance of 200k Ω/□, the doses of boron or phosphorus during ion doping were 1E14 and 1.1E14 ion/cm2, respectively. That is, using a sufficiently large and easily controlled dose of impurities when ion doping the resistor body, and annealing at relatively low temperatures (250 ℃ -850 ℃), the degree of influence of the polysilicon grain size on the sheet resistance can be greatly reduced, and the accuracy with which a given resistor rating can be obtained can be improved.
Also, doping and annealing the polysilicon layer after metallization formation allows for rapid control and detection and determination of the required dopant dose for a particular batch of wafers having a particular polysilicon grain size, which can result in very high precision and repeatability of the sheet resistance of the polysilicon layer.
Specific reference is made to figures 1-10 for embodiments of the present invention:
where 1 denotes a polysilicon layer, 2 denotes a dielectric layer, 3 denotes an epitaxial layer, 4 denotes a high alloy region, 5 denotes a high doped region, 6 denotes a sputtered metal layer, 7 denotes a silicon nitride layer, 8 denotes a silicon dioxide layer, 9 denotes a metal layer 2-aluminum, 10 denotes a metal layer 1-titanium tungsten, 11 denotes a metal layer, 12 denotes a doped layer, and 13 denotes a polysilicon layer.
The method for forming the polysilicon resistor structure shown in fig. 1 is originally used for producing a polysilicon resistor with the surface resistance of 200 +/-30 k omega. The typical process flow is briefly described as follows: a thin film layer of silicon dioxide (SiO2) was grown on the P-type epitaxial film, a layer of silicon nitride (Si3N4) was deposited on the thin film layer of (SiO2), and then a layer of polysilicon was deposited on the silicon nitride (Si3N4) (see fig. 6). Using photolithography, highly doped regions were formed in the polysilicon layer using phosphorus ion doping at a dose of 3.1E5 ions/cm 2 and an energy of E60 keV (see fig. 7). The resistive polysilicon regions are obtained by appropriate photolithography using anisotropic plasma chemical etching (see fig. 8). Next, as shown in FIG. 9, a titanium Tungsten (TiW) layer having a thickness of 0.18 μm and an aluminum (Al) layer having a thickness of 1.1 μm are deposited over the entire structure by plasma enhanced chemical vapor deposition or other methods. Thereafter, using appropriate photolithography, metal contacts were formed on the highly doped regions of the polysilicon resistor, and a doped layer was formed in the body of the polysilicon resistor after phosphorus ion doping at a dose of 1.1E14 ions/cm 2) and an energy of E ═ 30keV and a 15 minute annealing process in a nitrogen atmosphere at 510 ℃ (see fig. 10).
Therefore, the method for producing the high-resistance polysilicon resistor can obtain the resistor with high surface resistance, the value of the resistor can be adjusted with high precision, the production yield of the resistor and the yield of the integrated circuit taking the resistor as an element can be obviously improved, and after the second resistor is obtained, the high precision of the obtained new resistor can be effectively ensured by carrying out qualification verification and correction verification on the second resistor.
The beneficial effects of the above technical scheme are: the method is used for improving the precision of the high surface resistance of the obtained polysilicon resistor by doping and annealing the resistor after the metallization formation, and the high precision of the polysilicon resistor is further ensured by the qualification verification of the resistor.
Example 2:
based on embodiment 1, in step 2, the high-concentration ion doping of the doped region of the polysilicon layer is performed after the formation of the metallization of the polysilicon resistor, and the high-concentration ion doping of the doped region of the polysilicon layer includes:
determining a grain size of the first resistor and, based on a preset database, determining a dopant amount associated with the grain size;
and carrying out ion doping on the doped region of the polycrystalline silicon layer according to the doping amount.
In one possible way of realisation,
the preset temperature is in the range of (250 ℃ and 850 ℃).
In one possible way of realisation,
and the absolute value of the difference between the depth of the doped region in the polycrystalline silicon layer and the thickness of the polycrystalline silicon layer is smaller than a preset value.
In this embodiment, the production of the polysilicon resistor prior to metallization formation allows the structure of the resistor to be exposed to high temperature (850 ℃ -1200 ℃) operations before the end of the production process. As a result, the depth of the doped region in the polysilicon layer may be close to and equal to the thickness of the polysilicon layer. In addition, analysis of the current-voltage performance of polysilicon resistors fabricated according to the prototype and the originally specified method revealed that the sheet resistance differences of the resistors between different batches of substrates were largely determined by the grain size of the polysilicon. Ion doping of polysilicon resistors and their annealing at lower temperatures (250-850 c) after metallization formation requires the use of larger doses of impurities.
The beneficial effects of the above technical scheme are: the dosage of doping ions is effectively ensured, and a foundation is provided for improving the high precision of the resistor.
Example 3:
based on embodiment 2, before determining the grain size of the first resistor, the method includes:
determining a crystal region of the first resistor and dividing the crystal region into a peripheral region and an inner region;
performing diffraction measurement on the peripheral area to obtain diffraction information, analyzing abnormal information in the diffraction information according to a standard diffraction spectrum, and performing first marking on abnormal points in the peripheral area according to the abnormal information;
meanwhile, determining the size information of the crystal grains under the first marked abnormal point, and screening all first points of which the size information is larger than a preset size;
determining the point position information of each first point, and determining an arrangement pattern formed based on the first points according to the point position information;
judging whether the arrangement pattern meets a preset pattern standard or not based on a preset database, and if so, determining the occupation area of the pattern area of the arrangement pattern in the peripheral area;
otherwise, regarding the first point as an invalid point;
scanning and measuring the internal area to obtain scanning information, constructing a scanning array, screening abnormal points existing in the scanning array, and determining the current position of the abnormal points;
when the current positions are all regarded as invalid positions, the abnormal points are removed, and uniformity detection is carried out on the remaining points in the scanning array;
simultaneously, determining crystal grains on the outermost layer of the adjacent part of the external area and the internal area, and judging the stress direction of the crystal grains on the outermost layer of the adjacent part and the quantity difference of the crystal grains on the two layers in the process from the outside to the inside;
determining the distribution trend of the crystal grains on the two layers according to the judgment result;
judging whether crystal grains existing in a crystal region of the first resistor are effective or not according to the occupied area, the uniformity detection result and the distribution trend;
if valid, the first resistor is retained.
In this embodiment, as shown in fig. 12, a1 denotes an outer peripheral region, a2 denotes an inner region, a denotes a crystal region, and a3 denotes an outer layer surface of an adjacent portion.
In this embodiment, the abnormal information is determined by the diffraction information, and is determined by the diffracted light, and when the line of the diffracted light deviates from the preset line, the abnormal information is determined, and the corresponding point deviating from the boundary is obtained, the abnormal point is determined, and the preset size of the crystal grain is set in advance.
In this embodiment, the first point refers to a position point of the abnormal point whose size information is larger than the preset information, and the arrangement pattern is determined according to the position information, so as to effectively determine the position distribution map of the abnormal point, and to conveniently and effectively determine whether the position of the abnormal point is reasonable. And the preset pattern standard is preset.
In this embodiment, the area of the area is determined by the ratio of the area of the pattern formed by the area of each dot to the total area of the peripheral region.
In this embodiment, the abnormal point refers to the existence of a defect or the like after being scanned.
In this embodiment, the inactive position means that it does not affect the entire crystal region.
In this embodiment, the uniformity detection means detection of conductivity and the like of the remaining dots.
In this embodiment, the number difference refers to that there is a difference in the number of the crystal grains, and in the process of determining the stress direction of the crystal grains, the distribution direction of the crystal grains can be determined. Or the distribution trend is determined in advance from the direction of small crystal grains to the direction of large crystal grains.
The beneficial effects of the above technical scheme are: through obtaining the crystal region, and distinguish it, and through carrying out the diffraction measurement to peripheral region, and through size information, pattern comparison, judge whether the first point is invalid, secondly, through carrying out the scanning measurement to the internal region, confirm whether there is abnormal point, and carry out homogeneity detection to the remaining point, judge through the crystalline grain on the outmost face to adjacent part at last, confirm trend and quantity, through the combination of the three, effective definite crystalline grain is effective whether, and then realize the effective reservation to first resistor, effectively guarantee the high resistance high accuracy of resistor.
Example 4:
based on embodiment 3, after the first resistor is retained, the method further includes:
performing uniform area segmentation on the first resistor, acquiring a plurality of sub-areas, and determining the diameter of each crystal grain existing on each sub-area;
dividing the diameters of grains existing in each sub-area to obtain a large grain set, a medium grain set and a small grain set, and simultaneously determining the number of first grains of the large grain set, the number of second grains of the medium grain set and the number of third grains of the small grain set;
determining the area weight of the sub-area and the position weight of each crystal grain in the sub-area based on a standard position distribution library;
calculating a first distribution value F1 of a large crystal grain set, a second distribution value F2 of a medium crystal grain set and a third distribution value F3 of a small crystal grain set in a corresponding sub-area according to the area weight, the position weight of each crystal grain and the number of corresponding crystal grains based on the following formula;
wherein j takes the value of 1, 2, 3; when j is 1, Fj represents a first distribution value F1 of the large crystal grain set; when j is 2, Fj represents a second distribution value F2 of the medium grain set; when j is 3, Fj represents a third distribution value F3 of the small crystal grain set; ij represents the ith crystal grain in the total crystal grains Ij in the jth crystal grain set; a isijRepresenting the position weight of the ith crystal grain in the jth crystal grain set; alpha is alphaijThe position correction value of the ith crystal grain in the jth crystal grain set is represented, and the value range is [0.8, 1.2 ]]；sijThe grain volume of the ith grain in the jth grain set is represented; a denotes the region volume of the corresponding sub-region; ij represents the total number of the j-th crystal grains; Δ j represents the invalid distribution proportion of the jth crystal grain set based on the subareas, and the value is (0, 1);
calculating a corresponding average distribution value X based on the first distribution value, the second distribution value and the third distribution value and the following formula, determining a corresponding average distribution capability according to a distribution capability table, and further obtaining an average grain size of a corresponding sub-area according to a capability grain mapping table;
wherein χ 1 represents a position distribution weight value of the large grain set; chi 2 represents the position distribution weight value of the medium grain set; χ 3 represents a position distribution weight value of the small crystal grain set; r isi1Represents the grain radius of the ith grain in the large grain set; r isi2Represents the grain radius of the ith grain in the middle grain set; r isi3Represents the grain radius of the ith grain in the small grain set;
obtaining the grain size of the first resistor according to the average grain size of each subarea and the incidence relation between each subarea;
determining a dopant amount associated with the grain size based on a predetermined database.
In this embodiment, the average distribution capability and the average grain size are obtained to ensure high precision of the grains, and the association refers to stress of the grains between each sub-region.
The beneficial effects of the above technical scheme are: the method comprises the steps of obtaining a plurality of sub-regions by uniformly dividing the region, determining the grain diameter of the sub-regions, performing set division, determining the region weight of the sub-regions and the position weight of each grain, calculating the distribution value of grains with different diameters according to a formula, calculating the average distribution value according to the formula, obtaining the average grain size of each sub-region based on a mapping table, obtaining the grain size of a first resistor, obtaining the doping dose, ensuring the rationality of obtaining the doping dose, and providing a data base for obtaining a high-resistance high-precision resistor.
Example 5:
based on embodiment 1, in step 4, performing qualification verification on the second resistor includes:
determining a first voltage and a second voltage for testing based on a semiconductor process for manufacturing the second resistor;
performing a first voltage test on the second resistor, monitoring a first actually generated voltage based on the second resistor, adjusting the first voltage to be a second voltage when capturing a time point that is greater than a preset voltage in the actually generated voltage, and continuing to monitor a second actually generated voltage based on the second resistor based on the time point;
acquiring a first temperature change of the second resistor based on a first actual generated voltage and a second temperature change of the second resistor based on a second actual generated voltage;
obtaining an adjustment voltage amount of the first voltage based on a voltage difference value between the second voltage and the first voltage, the first temperature change and the second temperature change, and obtaining a third voltage;
testing the second resistor according to the third voltage, and if a time point greater than a preset voltage still exists in the testing process, judging that the second resistor is unqualified;
otherwise, the second resistor is determined to be a high-resistance high-precision resistor.
In this embodiment, the first voltage is greater than the second voltage, and the time point is when the actually generated voltage is greater than the predetermined voltage.
In this embodiment, the temperature change refers to a temperature change of the resistor itself, and the adjustment voltage amount may refer to a voltage amount directed to small adjustment.
The beneficial effects of the above technical scheme are: by determining the time point, different voltages are switched to test, the error of single test is reduced, the adjustment voltage amount is conveniently and effectively obtained by determining the temperature change and the differential pressure value, and further reasonable voltage is obtained, so that the second resistor is tested again, whether the second resistor is qualified is determined, and a foundation is provided for ensuring the high-precision high-resistance of the second resistor.
Example 6:
on the basis of embodiment 5, after determining that the second resistor is defective, performing correction verification on the second resistor includes:
determining the area space of the doped area, and determining the space filling degree of high-concentration ion doping in the area space;
when the space filling degree is greater than the preset filling degree, judging the filling uniformity of the area space;
otherwise, performing filling verification on the second resistor;
when the filling uniformity is smaller than the preset uniformity, carrying out uniformity verification on the second resistor;
otherwise, respectively determining the voltage variation and the temperature gradient before and after doping, and performing preset verification on the voltage resistor.
In this embodiment, the filling verification refers to determining high-concentration ions filled therein, the uniformity verification refers to verifying concentration uniformity distribution of the filled high-concentration ions, and the preset verification refers to verifying voltage and temperature, so as to implement corresponding correction.
The beneficial effects of the above technical scheme are: through carrying out the judgement of space filling degree, packing degree of consistency, can be effectual respectively fill check and the degree of consistency check to it, and through according to temperature and voltage variation, preset the check-up to voltage resistor, through the cubic check-up, guarantee the validity of check-up, provide the guarantee for the high accuracy high resistance who guarantees the resistor.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.
Claims (6)
1. A method for producing a high-resistance high-precision resistor, comprising:
step 1: depositing a polysilicon layer on a multi-layer dielectric body of a polysilicon resistor, isolating the multi-layer dielectric body from a substrate and integrated circuit elements;
step 2: carrying out high-concentration ion doping on the doped region of the polycrystalline silicon layer, and forming a polycrystalline silicon region by adopting a photoetching process to obtain a first resistor;
and step 3: after depositing the metal layer of the first resistor, photoetching, contacting with a highly alloyed region, and annealing at a preset temperature to obtain a second resistor;
and 4, step 4: and performing qualification verification on the second resistor, if the verification is successful, determining that the second resistor is a high-resistance high-precision resistor, otherwise, performing correction verification on the second resistor, and including:
determining a first voltage and a second voltage for testing based on a semiconductor process for manufacturing the second resistor;
performing a first voltage test on the second resistor, monitoring a first actually generated voltage based on the second resistor, adjusting the first voltage to be a second voltage when capturing a time point that is greater than a preset voltage in the actually generated voltage, and continuing to monitor a second actually generated voltage based on the second resistor based on the time point;
acquiring a first temperature change of the second resistor based on a first actual generated voltage and a second temperature change of the second resistor based on a second actual generated voltage;
obtaining an adjustment voltage amount of the first voltage based on a voltage difference value between the second voltage and the first voltage, the first temperature change and the second temperature change, and obtaining a third voltage;
testing the second resistor according to the third voltage, and if a time point greater than a preset voltage still exists in the testing process, judging that the second resistor is unqualified;
otherwise, judging that the second resistor is a high-resistance high-precision resistor;
after the second resistor is judged to be unqualified, performing correction verification on the second resistor, wherein the correction verification comprises the following steps:
determining the area space of the doped area, and determining the space filling degree of high-concentration ion doping in the area space;
when the space filling degree is greater than the preset filling degree, judging the filling uniformity of the area space;
otherwise, performing filling verification on the second resistor;
when the filling uniformity is smaller than the preset uniformity, carrying out uniformity verification on the second resistor;
otherwise, respectively determining the voltage variation and the temperature gradient before and after doping, and performing preset verification on the voltage resistor.
2. The production method according to claim 1, wherein in step 2, the high concentration ion doping of the doped region of the polysilicon layer is performed after the formation of the metallization of the polysilicon resistor, and the high concentration ion doping of the doped region of the polysilicon layer comprises:
determining a grain size of the first resistor and, based on a preset database, determining a dopant amount associated with the grain size;
and carrying out ion doping on the doped region of the polycrystalline silicon layer according to the doping amount.
3. The method of claim 1, wherein the predetermined temperature is in a range of 250 ℃ to 850 ℃.
4. The production method according to claim 1,
and the absolute value of the difference between the depth of the doped region in the polycrystalline silicon layer and the thickness of the polycrystalline silicon layer is smaller than a preset value.
5. The method of manufacturing as claimed in claim 2, wherein determining the grain size of the first resistor comprises, prior to:
determining a crystal region of the first resistor and dividing the crystal region into a peripheral region and an inner region;
performing diffraction measurement on the peripheral area to obtain diffraction information, analyzing abnormal information in the diffraction information according to a standard diffraction spectrum, and performing first marking on abnormal points in the peripheral area according to the abnormal information;
meanwhile, determining the size information of the crystal grains under the first marked abnormal point, and screening all first points of which the size information is larger than a preset size;
determining the point position information of each first point, and determining an arrangement pattern formed based on the first points according to the point position information;
judging whether the arrangement pattern meets a preset pattern standard or not based on a preset database, and if so, determining the occupation area of the pattern area of the arrangement pattern in the peripheral area;
otherwise, regarding the first point as an invalid point;
scanning and measuring the internal area to obtain scanning information, constructing a scanning array, screening abnormal points existing in the scanning array, and determining the current position of the abnormal points;
when the current positions are all regarded as invalid positions, the abnormal points are removed, and uniformity detection is carried out on the remaining points in the scanning array;
simultaneously, determining crystal grains on the outermost layer surface of the adjacent part of the peripheral area and the internal area, and judging the stress direction of the crystal grains on the outermost layer surface of the adjacent part and the quantity difference of the crystal grains on the two layer surfaces in the process from the outside to the inside;
determining the distribution trend of the crystal grains on the two layers according to the judgment result;
judging whether crystal grains existing in a crystal region of the first resistor are effective or not according to the occupied area, the uniformity detection result and the distribution trend;
if valid, the first resistor is retained.
6. The method of manufacturing as claimed in claim 5, wherein after retaining the first resistor, further comprising:
performing uniform area segmentation on the first resistor, acquiring a plurality of sub-areas, and determining the diameter of each crystal grain existing on each sub-area;
dividing the diameters of grains existing in each sub-area to obtain a large grain set, a medium grain set and a small grain set, and simultaneously determining the number of first grains of the large grain set, the number of second grains of the medium grain set and the number of third grains of the small grain set;
determining the area weight of the sub-area and the position weight of each crystal grain in the sub-area based on a standard position distribution library;
calculating a first distribution value F1 of a large crystal grain set, a second distribution value F2 of a medium crystal grain set and a third distribution value F3 of a small crystal grain set in a corresponding sub-area according to the area weight, the position weight of each crystal grain and the number of corresponding crystal grains based on the following formula;
wherein j takes the value of 1, 2, 3; when j is 1, Fj represents a first distribution value F1 of the large crystal grain set; when j is 2, Fj represents a second distribution value F2 of the medium grain set; when j is 3, Fj represents a third distribution value F3 of the small crystal grain set; i j denotes the ith crystal grain in the total crystal grains Ij in the jth crystal grain set; a isijRepresenting the position weight of the ith crystal grain in the jth crystal grain set; alpha is alphaijThe position correction value of the ith crystal grain in the jth crystal grain set is represented, and the value range is [0.8, 1.2 ]]；sijThe grain volume of the ith grain in the jth grain set is represented; a denotes the region volume of the corresponding sub-region; ij represents the total number of the j-th crystal grains; Δ j represents the invalid distribution proportion of the jth crystal grain set based on the subareas, and the value is (0, 1);
calculating a corresponding average distribution value X based on the first distribution value, the second distribution value and the third distribution value and the following formula, determining a corresponding average distribution capability according to a distribution capability table, and further obtaining an average grain size of a corresponding sub-area according to a capability grain mapping table;
wherein χ 1 represents a position distribution weight value of the large grain set; chi 2 represents the position distribution weight value of the medium grain set; χ 3 represents a position distribution weight value of the small crystal grain set; r isi1Represents the grain radius of the ith grain in the large grain set; r isi2Represents the grain radius of the ith grain in the middle grain set; r isi3Represents the grain radius of the ith grain in the small grain set;
obtaining the grain size of the first resistor according to the average grain size of each subarea and the incidence relation between each subarea;
determining a dopant amount associated with the grain size based on a predetermined database.
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| CN101030580A (en) * | 2006-02-22 | 2007-09-05 | 精工电子有限公司 | Semiconductor device and method of manufacturing the same |
| CN101465383A (en) * | 2008-12-30 | 2009-06-24 | 中国科学院上海微系统与信息技术研究所 | Schottky diode and manufacturing method thereof, method for manufacturing electric resistance transition memory |
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| CN101030580A (en) * | 2006-02-22 | 2007-09-05 | 精工电子有限公司 | Semiconductor device and method of manufacturing the same |
| CN101465383A (en) * | 2008-12-30 | 2009-06-24 | 中国科学院上海微系统与信息技术研究所 | Schottky diode and manufacturing method thereof, method for manufacturing electric resistance transition memory |
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