CN113066732A - Method for forming integrated circuit structure - Google Patents
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- CN113066732A CN113066732A CN202110273795.3A CN202110273795A CN113066732A CN 113066732 A CN113066732 A CN 113066732A CN 202110273795 A CN202110273795 A CN 202110273795A CN 113066732 A CN113066732 A CN 113066732A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3121—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation
- H01L23/3128—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed a substrate forming part of the encapsulation the substrate having spherical bumps for external connection
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
- H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49838—Geometry or layout
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Abstract
The application discloses a forming method of an integrated circuit structure, which is characterized by comprising a processor device, wherein at least one memory device with a conductive bump on the inverted top surface is provided with a conductive bump on the surface, the memory device and the processor device are partially overlapped, and part of the conductive bump on the memory device and part of the conductive bump on the processor device are mutually contacted and conducted; welding the conductive bumps and the conductive bumps which are in contact with each other; inverting the processor device with the memory device fixed on a semiconductor medium to enable the conductive boss on the semiconductor medium with the conductive boss on the top surface to be not shielded by the memory device and the conductive boss on the processor device; and welding the conductive bumps and the conductive bosses which are contacted with each other, so that the memory device, the processor device and the semiconductor medium respectively form the memory, the processor and the semiconductor substrate in the integrated circuit structure.
Description
Technical Field
The present invention relates to the field of semiconductors, and more particularly, to a method for forming an integrated circuit structure.
Background
At present, with the continuous development of science and technology, the High Performance Computing (HPC) and Artificial Intelligence (AI) technologies are rapidly developed, and the performance requirements of integrated circuit chips are higher and higher. Particularly, as 5G technology is continuously integrated with various industries, some fields require integrated circuit chips with high data transmission rate, high throughput, low latency, and large bandwidth capabilities.
For many years, the technological development and market adoption of integrated circuit chip manufacturers have followed moore's law, i.e., the number of integrated circuits on an integrated circuit chip doubles every 18 months, and the price drops by half. However, as the number of integrated circuits increases, the size of the chip becomes less and less demanding, and as the number of integrated transistors on the silicon increases, the line density increases, the complexity and error rate increases exponentially, thus making full and thorough chip testing nearly impossible.
Once the width of the line on the chip reaches the magnitude of nanometer (10^ -9 meters), the size is equivalent to the size of only a few molecules, and the physical and chemical properties of the material are substantially changed under the condition, but the semiconductor device adopting the existing process cannot normally work, and the Moore's law is about to go to the end.
Two major challenges now facing the chip industry are how to achieve minimum integration complexity. The second is how to achieve cost optimization. Because of the structural limitations of the ic chip itself, manufacturers are looking to advance the technology of higher frequency and smaller size to advance the technology of packaging. Currently, the mainstream advanced packaging technology comprises 7 important technologies such as Flip-Chip, WLCSP, Fan-Out, Embedded IC, 3D WLCSP, 3D IC, 2.5D interposer and the like.
Regardless of the packaging technology, it is necessary to solve the problem of placing the memory closest to the integrated circuit chip (e.g., processor) to reduce latency and power consumption through shorter connections.
One current technique is to place the memory and processor side-by-side on a substrate, connected by wires within the substrate. However, this technique requires a predetermined distance between the processor and the memory in the lateral direction. This, on the one hand, does not minimize the distance between the memory and the processor, and, on the other hand, increases the lateral size of the integrated circuit chip. The size of the chip in the lateral direction increases, so that the cost of the chip increases. Another technique is to deploy multiple memory and processor dies (die) on one or more layers of silicon substrate with TSV vertical interconnect vias and high density metal routing (Si interposer) and then package them. However, this technique requires a via hole to be opened and a metal conductive layer to be implanted into the via hole. Therefore, this technique is complicated and is not conducive to improving the yield and efficiency of integrated circuit chip production. Also, the silicon substrate is always spaced between the memory and processor die, and therefore, the spacing between the memory and the processor cannot be minimized.
Disclosure of Invention
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, wherein the integrated circuit structure formed by the method for forming an integrated circuit structure can not only be made smaller in size, but also can have a smaller space between a processor and a memory, thereby satisfying the requirement for the integrated circuit structure.
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, wherein a manufacturing process of the integrated circuit structure formed by the method for forming an integrated circuit structure is simple, so that manufacturing efficiency of the integrated circuit structure can be improved.
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, wherein the size of the integrated circuit structure formed by the method for forming an integrated circuit structure in the lateral direction can be smaller, and thus the manufacturing cost of a chip manufacturer can be reduced.
Another advantage of the present invention is to provide a method of forming an integrated circuit structure having a relatively low latency rate due to a relatively reduced separation between the memory and the processor.
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, wherein after a distance between a memory and a processor in the integrated circuit structure formed by the method for forming an integrated circuit structure is reduced, a length of a conductor required to be disposed to conduct the memory and the processor is effectively reduced, thereby effectively reducing power consumption of the integrated circuit structure.
It is another advantage of the present invention to provide a method of forming an integrated circuit structure in which the spacing between the memory and the processor in the integrated circuit structure formed by the method of forming the integrated circuit structure can be reduced, and therefore, the error rate of the integrated circuit structure is correspondingly reduced.
Another advantage of the present invention is to provide a method for forming an integrated circuit structure, in which a distance between a memory and a processor in the integrated circuit structure formed by the method for forming the integrated circuit structure can be reduced, and thus, the integrated circuit structure generates less heat.
To achieve at least one of the above advantages, the present invention provides a method for forming an integrated circuit structure, which includes the following steps:
s1, inverting at least one memory device with a conductive bump on the top surface to form a processor device with a conductive bump on the surface, and partially overlapping the memory device and the processor device, wherein part of the conductive bump on the memory device and part of the conductive bump on the processor device are in contact with each other and are conducted;
s2, thermocompression bonding the conductive bump and the conductive bump in contact with each other;
s3, inverting the processor device with the memory device fixed on a semiconductor medium to make the conductive boss on the semiconductor medium with the conductive boss on the top surface and the conductive bump which is not shielded by the memory device and is positioned on the processor device; and
and S4, thermocompression bonding the conductive bumps and the conductive bosses in contact with each other, so that the memory device, the processor device and the semiconductor medium respectively form a memory, a processor and a semiconductor substrate in an integrated circuit structure.
According to an embodiment of the present invention, the semiconductor medium is previously arranged with a wiring layer.
According to an embodiment of the invention, the method for forming the integrated circuit structure further includes the following steps:
s5, providing a bearing plate with a groove;
s6, placing the processor device in the groove with the conductive protrusion upward; and
s7, after the step S3 is completed, the bearing plate is moved out.
According to an embodiment of the present invention, a sum of heights of the memory and the thermocompression bonded conductive bump and the conductive bump in a thickness direction of the semiconductor substrate is adapted to a sum of heights of the conductive bump and the conductive bump in the thickness direction of the semiconductor substrate, which are provided between a side of the processor facing the semiconductor substrate and the semiconductor substrate.
According to an embodiment of the present invention, the plurality of conductive bumps and the plurality of conductive bumps are disposed at intervals.
According to an embodiment of the present invention, the integrated circuit structure includes two wiring layers symmetrically formed on both sides of the semiconductor substrate.
According to an embodiment of the present invention, the integrated circuit structure includes a plurality of electrical conductors, a plurality of through holes are formed between the top side and the bottom side of the semiconductor substrate, and each of the electrical conductors is electrically connected to the wiring layer on the top side of the semiconductor substrate and the wiring layer on the bottom side of the semiconductor substrate through the through hole to form a specific circuit structure.
According to an embodiment of the invention, the integrated circuit structure further includes a power board, wherein the power board is conducted to the memory by the electrical connection component.
According to an embodiment of the present invention, at least one bypass capacitor is disposed on the power board.
According to an embodiment of the invention, the processor is implemented as a microprocessor.
Drawings
Fig. 1 shows a perspective view of an integrated circuit structure according to the invention.
Fig. 2 shows a partial cross-sectional view of a semiconductor substrate and wiring level of an integrated circuit structure in accordance with the present invention.
Fig. 3 shows a partial cross-sectional view of an integrated circuit structure according to the present invention.
Fig. 4 shows a cross-sectional view of the wiring layer of the present invention.
Figure 5 shows a schematic diagram of a stage in the fabrication flow of the integrated circuit structure of the present invention.
Fig. 6 is a schematic diagram illustrating a second stage in the fabrication flow of the integrated circuit structure of the present invention.
Fig. 7 is a schematic diagram illustrating a third stage in the fabrication process of the integrated circuit structure of the present invention.
Fig. 8 shows a flow chart for the fabrication of an integrated circuit structure according to the invention.
Detailed Description
The following description is presented to disclose the invention so as to enable any person skilled in the art to practice the invention. The preferred embodiments in the following description are given by way of example only, and other obvious variations will occur to those skilled in the art. The basic principles of the invention, as defined in the following description, may be applied to other embodiments, variations, modifications, equivalents, and other technical solutions without departing from the spirit and scope of the invention.
It will be understood by those skilled in the art that in the present disclosure, the terms "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used in an orientation or positional relationship indicated in the drawings for ease of description and simplicity of description, and do not indicate or imply that the referenced devices or components must be in a particular orientation, constructed and operated in a particular orientation, and thus the above terms are not to be construed as limiting the present invention.
It is understood that the terms "a" and "an" should be interpreted as meaning that a number of one element or element is one in one embodiment, while a number of other elements is one in another embodiment, and the terms "a" and "an" should not be interpreted as limiting the number.
Referring to fig. 1 to 4, an integrated circuit structure according to a preferred embodiment of the present invention will be described in detail below, wherein the integrated circuit structure can be used in a variety of electronic or electrical devices, such as mobile phones, computers, and other devices.
Specifically, the integrated circuit structure includes at least one semiconductor substrate 10, at least one wiring layer 20, at least one memory 30, and at least one processor 40. The wiring layer 20 is formed on one side of the semiconductor substrate 10. Each of the memory 30 and the processor 40 is partially overlapped and mounted on the same side of the semiconductor substrate 10, and the memory 30 and the processor 40 are conducted to each other, and further, the processor 40 is set to be conducted to the wiring layer 20 in which the rear surface of the memory 30 is placed upside down on the semiconductor substrate 10.
It will be understood by those skilled in the art that the memory 30 may be implemented as any one or a combination of two or more selected from HBM, DRAM, SRAM, or solid state storage such as flash memory devices, and the present invention is not limited in this respect. The processor 40 can be implemented as a central processing unit CPU or a microprocessor MPU, but the invention is not limited in this respect.
It is worth mentioning that, since the memory 30 and the processor 40 are partially overlapped and mounted on the same side of the semiconductor substrate 10, and the memory 30 and the processor 40 are conducted with each other, the lateral size of the semiconductor substrate 10 required by the integrated circuit structure can be reduced, thereby reducing the cost of the integrated circuit structure as a whole.
It is more worth mentioning that the electrical connection 300 is arranged at the overlapping part of the memory 30 and the processor 40. While said electrical connection 300 is provided between said memory device 30 or said processor 40, which is inverted with respect to said semiconductor substrate 10, and the top of said semiconductor substrate 10 facing said processor 40.
In one embodiment, the processor 40 is inverted on the semiconductor substrate 10 and is conducted to the routing layer 20 by the electrical connection 300. It is worth mentioning that the electrical connection 300 is implemented as at least one conductive bump, and the heights of the conductive bumps arranged between the processor 40 and the semiconductor substrate 10 are consistent, so that the processor 40 can be supported by the electrical connection 300 when being inverted on the semiconductor substrate 10.
Furthermore, when the integrated circuit structure includes a plurality of the electrical connections 300, the plurality of the electrical connections 300 are arranged at intervals, in such a way that a gap of a predetermined size will be able to be formed between the processor 40 and the semiconductor substrate 10. Therefore, when the integrated circuit structure is mounted in an electronic or electrical device and the processor 40 operates for a long time or under a high load to generate a large amount of heat, the heat can be dissipated through the gap between the processor 40 and the semiconductor substrate 10, that is, the integrated circuit structure of the present invention has a good heat dissipation effect.
In addition, the processor 40 and the memory 30 are partially overlapped, and the processor 40 and the memory 30 are electrically connected with each other through the electrical connector 300 arranged between the overlapped parts of the processor 40 and the memory 30, so that the distance between the processor 40 and the memory 30 can be controlled by controlling the necessary length of the electrical connector 300. Due to this arrangement, the distance between the processor 40 and the memory 30 can be controlled to be smaller than the distance between the processor 40 and the memory 30 in the prior art.
It is worth mentioning that, in the process of electrically connecting the processor 40 and the memory 30 by the electrical connector 300, only the electrical connector 300 needs to be fixed to the memory 30 and the processor 40, respectively, without using a complicated wiring process and TSV process, so that the integrated circuit structure can be manufactured more simply.
Preferably, in this embodiment, one side of the memory 30 is attached to the wiring layer 20. It is understood that the wiring layer 20 includes a metal conductive layer 21, a contact layer 22 electrically connected to the metal conductive layer 21, and an insulating layer 23 formed of the semiconductor substrate 10. After being attached to the wiring layer 20, the memory 30 is in contact with the contact layer 22 in the wiring layer 20. The contact layer 22 is implemented as a material having a high thermal conductivity of a metal, such as copper, so that the memory 30 can dissipate heat through the contact layer 22 after being attached to the contact layer 22. It is understood that the wiring layer 20 can be further formed by a semiconductor process such as etching, developing, plating, etc. on the semiconductor substrate 10.
When the memory 30 is mounted on the semiconductor substrate 10, the memory 30 is electrically connected to the contact layer 22, and thus electrically conducted to the metal conductive layer 21. Preferably, the electrical connection 300 electrically connecting the memory 30 and the processor 40 is fixed to the memory 30. When the memory 30 and the processor 40 are partially overlapped, the top of the electrical connection 300 between the memory 30 and the processor 40 is thermally-compression-bonded (thermally-bonding) to the contact on the processor 40, so that the memory 30 and the processor 40 are fixed to each other and are in conduction with each other. More preferably, the electrical connections 300 are formed by thermal-compression bonding (thermocompression bonding) of respective conductive bumps disposed on the processor 40 and the memory 30.
It is worth mentioning that the metal conductive layer 21 forms a specific circuit structure according to a predetermined design.
In a variant embodiment, the memory device 30 and the processor 40 and the electrical connection 300 may also be arranged on the processor 40 on a side facing the semiconductor substrate 10, and the bottom end of the electrical connection 300 is thermo-compression-bonded (thermally-bonding) to contacts on the memory device 30 when the memory device 30 and the processor 40 are partially overlapped.
It is worth mentioning that the sum of the heights of the memory 30 and the electrical connection 300 in the thickness direction of the semiconductor substrate 10 is adapted to the electrical connection 300 provided between the side of the processor 40 facing the semiconductor substrate 10 and the semiconductor substrate 10, so that after the processor 40 is inverted, the electrical connection 300 can be brought into contact with the contact layer 22 on the wiring layer 20, so as to be subsequently brought into conduction with the wiring layer 20 by thermal-compression-bonding. More importantly, the levelness of the processor 40 can be effectively ensured by the limitation of height, and thus the conductive members 100 arranged side by side between the processor 40 and the memory 30 and the electrical connection members 300 between the processor 40 and the semiconductor substrate 10 can be contacted with corresponding contacts.
From the above description, it will be appreciated by those skilled in the art that the spacing between the memory 30 and the processor 40 is small compared to prior art connections, and thus has the ability to transmit signals with low delay when the integrated circuit structure is powered on.
It will be appreciated by those skilled in the art that since the electrical connection between the memory device 30 and the processor 40 is through the electrical connection 300 in the thickness direction of the semiconductor substrate 10 and there is a partial overlap between the memory device 30 and the processor 40, the lateral dimensions of the semiconductor substrate 10 can be reduced, which in turn allows the overall lateral dimensions of the integrated circuit structure to be reduced. At the same time, the spacing between the memory 40 and the processor 40 is smaller compared to the spacing between the memory and the processor in the prior art, resulting in an overall increase in latency resistance and less power consumption of the overall integrated circuit structure. More importantly, compared with the TSV technology in the prior art, the process for forming the integrated circuit structure is simpler and more efficient, and the yield of the integrated circuit structure can be effectively improved.
Preferably, the integrated circuit structure includes two of the wiring layers 20. Two layers of the wiring layers 20 are respectively provided on the top side of the semiconductor substrate 10 and the bottom side of the semiconductor substrate 10.
Preferably, the integrated circuit structure includes a plurality of electrical conductors 50, with a plurality of vias 101 formed between the top and bottom sides of the semiconductor substrate 10. After passing through the through hole, each conductive member 50 is electrically connected to the metal conductive layer 21 in the wiring layer 20 on the top side of the semiconductor substrate 10 and the metal conductive layer 21 in the wiring layer 20 on the bottom side of the semiconductor substrate 10 at both ends, respectively, to form a specific circuit structure. In this manner, the processor 40 can be electrically connected to other semiconductor devices on the backside. In addition, after the memory 40 is mounted on the semiconductor substrate 10, the back surface of the memory 40 contacts the contact layer 22 of the wiring layer 20, so that the memory 40 generated during operation can be conducted away from the memory 40 through the contact layer 22 and the conductive member 50, thereby achieving a better heat dissipation effect. That is, the conductive member 50 not only can serve to electrically connect the processor 40 to other semiconductor devices on the back surface, but also can make the memory 40 dissipate heat better.
Further, the integrated circuit structure further includes a plurality of conductive bumps 60, wherein the conductive bumps 60 are electrically connected to the metal conductive layer 21, and the conductive bumps 60 protrude from the wiring layer 20, so as to be electrically connected to other devices by means of thermal-compression-bonding (thermo-compression-bonding) later. It should be noted that the conductive convex hulls 60 are correspondingly disposed on the memory 30 and the processor 40, so that the conductive convex hulls 60 are formed by thermal-compression-bonding (thermo-compression-bonding) after the memory 30 and the processor 40 are overlapped, thereby forming the conductive elements 300.
It is understood that the device electrically connected to the processor 40 may extend to the back side of the semiconductor substrate 10 on which the processor 40 is mounted, by means of the conductive member 50 and the conductive convex hull 60.
More importantly, the integrated circuit structure can be electrically connected with other devices in the thickness direction of the semiconductor substrate 10 by means of thermal-compression bonding (thermal-bonding) through the conductive convex hull 60, so that the lateral dimension of the semiconductor substrate 10 can be further reduced.
Further, the integrated circuit structure further includes a power board 70, wherein the power board 70 is conducted to the memory 30 by the electrical connection 300. Preferably, at least one bypass capacitor 80 is disposed on the power board 70.
Referring to fig. 5-8, according to another aspect of the present invention, the present invention further provides a method for forming an integrated circuit structure, wherein the method for forming the integrated circuit structure comprises the following steps:
s1, inverting at least one memory device 800 having a conductive bump 801 on the top surface thereof, and placing a processor device 900 having a conductive bump 901 on the surface thereof, and partially overlapping the memory device 800 and the processor device 900, wherein a portion of the conductive bump 801 on the memory device 800 and a portion of the conductive bump 901 on the processor device 900 are in contact with each other and are in conduction;
s2, thermo-compression-bonding (thermo-compression-bonding) the conductive bump 901 and the conductive bump 801 in contact with each other;
s3, inversely fixing the processor device 900 with the memory device 800 on a semiconductor medium 700, so that the conductive bumps 701 on the semiconductor medium 700 with the top surface provided with the conductive bumps 701 and the conductive bumps 901 on the processor device 900 which are not covered by the memory device 800; and
s4, thermo-compression-bonding (thermo-compression-bonding) the conductive bumps 901 and the conductive lands 701 in contact with each other, so that the memory device 800, the processor device 900 and the semiconductor medium 700 form the memory 30, the processor 40 and the semiconductor substrate 10, respectively, in the integrated circuit structure described above.
It is worth mentioning that the semiconductor medium 700 is arranged with the wiring layer 20 in advance. It is worth mentioning that after the above-mentioned thermal-compression bonding (thermo-compression bonding) of the conductive bumps 901 and the conductive bumps 801 between the processor 40 and the memory 30, the electrical connection 300 between the processor 40 and the memory 30 will be formed. The electrical connection 300 between the processor 40 and the semiconductor medium 10 in the integrated circuit structure will be formed after thermo-compression bonding (bonding) of the conductive bumps 901 in contact with the conductive bumps 701 to the conductive bumps 701 as described above.
The method for forming the integrated circuit structure further comprises the following steps:
s5, providing a bearing plate 500 with a groove 501;
s6, placing the processor device 900 in the groove 501 with the conductive protrusion 901 facing upwards to prevent the processor device 900 from shaking during the manufacturing process;
s7, after the step S3 is completed, the bearing plate is moved out.
It will be appreciated by persons skilled in the art that the embodiments of the invention described above and shown in the drawings are given by way of example only and are not limiting of the invention. The advantages of the present invention have been fully and effectively realized. The functional and structural principles of the present invention have been shown and described in the examples, and any variations or modifications of the embodiments of the present invention may be made without departing from the principles.
Claims (10)
1. A method of forming an integrated circuit structure, comprising:
s1, inverting at least one memory device with a conductive bump on the top surface to form a processor device with a conductive bump on the surface, and partially overlapping the memory device and the processor device, wherein part of the conductive bump on the memory device and part of the conductive bump on the processor device are in contact with each other and are conducted;
s2, thermocompression bonding the conductive bump and the conductive bump in contact with each other;
s3, inverting the processor device with the memory device fixed on a semiconductor medium to make the conductive boss on the semiconductor medium with the conductive boss on the top surface and the conductive bump which is not shielded by the memory device and is positioned on the processor device; and
and S4, thermocompression bonding the conductive bumps and the conductive bosses in contact with each other, so that the memory device, the processor device and the semiconductor medium respectively form a memory, a processor and a semiconductor substrate in the integrated circuit structure.
2. The method of claim 1, wherein the semiconductor medium is pre-populated with wiring layers.
3. The method of claim 1, further comprising:
s5, providing a bearing plate with a groove;
s6, placing the processor device in the groove with the conductive protrusion upward; and
s7, after the step S3 is completed, the bearing plate is moved out.
4. The method as claimed in claim 1, wherein a sum of heights of the memory and thermocompression bonded conductive bumps and the conductive bumps in a thickness direction of the semiconductor substrate is adapted to a sum of heights of the conductive bumps and the conductive bumps in the thickness direction of the semiconductor substrate, the conductive bumps being disposed between a side of the processor facing the semiconductor substrate and the semiconductor substrate.
5. The method as claimed in claim 1, wherein the conductive bumps are disposed at intervals.
6. The method of claim 1, wherein the integrated circuit structure comprises two wiring layers, the two wiring layers being symmetrically formed on both sides of the semiconductor substrate.
7. The method as claimed in claim 1, wherein the integrated circuit structure includes a plurality of conductive members, a plurality of through holes are formed between the top side and the bottom side of the semiconductor substrate, and each conductive member is electrically connected to the wiring layer on the top side of the semiconductor substrate and the wiring layer on the bottom side of the semiconductor substrate through the through hole to form a specific circuit structure.
8. The method of claim 1, wherein the integrated circuit structure further comprises a power board, wherein the power board is electrically connected to the memory by the electrical connection.
9. The method as claimed in claim 1, wherein at least one bypass capacitor is disposed on the power board.
10. The method of claim 1, wherein the processor is implemented as a microprocessor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110273795.3A CN113066732B (en) | 2021-03-15 | 2021-03-15 | Method for forming integrated circuit structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110273795.3A CN113066732B (en) | 2021-03-15 | 2021-03-15 | Method for forming integrated circuit structure |
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| Publication Number | Publication Date |
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| CN113066732A true CN113066732A (en) | 2021-07-02 |
| CN113066732B CN113066732B (en) | 2024-04-09 |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
| CN103151337A (en) * | 2011-12-07 | 2013-06-12 | 台湾积体电路制造股份有限公司 | Test probing structure |
| CN103258806A (en) * | 2013-05-08 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor package structure with bridging structure and manufacturing method thereof |
| CN104253115A (en) * | 2013-06-28 | 2014-12-31 | 英特尔公司 | Underfill material flow control for reduced die-to-die spacing in semiconductor packages |
| CN107644839A (en) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20090212420A1 (en) * | 2008-02-22 | 2009-08-27 | Harry Hedler | integrated circuit device and method for fabricating same |
| CN103151337A (en) * | 2011-12-07 | 2013-06-12 | 台湾积体电路制造股份有限公司 | Test probing structure |
| CN103258806A (en) * | 2013-05-08 | 2013-08-21 | 日月光半导体制造股份有限公司 | Semiconductor package structure with bridging structure and manufacturing method thereof |
| CN104253115A (en) * | 2013-06-28 | 2014-12-31 | 英特尔公司 | Underfill material flow control for reduced die-to-die spacing in semiconductor packages |
| CN107644839A (en) * | 2017-08-31 | 2018-01-30 | 长江存储科技有限责任公司 | Wafer three-dimensional integration lead technique and its structure for three-dimensional storage |
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