CN113066717A - Semiconductor laser processing method - Google Patents

Semiconductor laser processing method Download PDF

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Publication number
CN113066717A
CN113066717A CN202110245825.XA CN202110245825A CN113066717A CN 113066717 A CN113066717 A CN 113066717A CN 202110245825 A CN202110245825 A CN 202110245825A CN 113066717 A CN113066717 A CN 113066717A
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Prior art keywords
substrate
metal silicide
regions
processing method
region
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CN202110245825.XA
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Chinese (zh)
Inventor
孙德瑞
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Shandong Aotian Environmental Protection Technology Co ltd
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Shandong Aotian Environmental Protection Technology Co ltd
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Priority to CN202110245825.XA priority Critical patent/CN113066717A/en
Publication of CN113066717A publication Critical patent/CN113066717A/en
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B23—MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23K—SOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00—Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36—Removing material
    • B23K26/362—Laser etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841—Barrier, adhesion or liner layers
    • H01L21/76853—Barrier, adhesion or liner layers characterized by particular after-treatment steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/552—Protection against radiation, e.g. light or electromagnetic waves

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Optics & Photonics (AREA)
  • Plasma & Fusion (AREA)
  • Mechanical Engineering (AREA)
  • Health & Medical Sciences (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

The invention provides a semiconductor laser processing method. The invention utilizes the previous working procedure to carry out the hybrid bonding of two silicon substrate chips, the bonding surface comprises a metal silicide region, the metal silicide region and a silicon material have better bonding effect, and the metal silicide simultaneously serves as an ohmic contact and an electromagnetic shielding layer. In particular, the metal silicide region is formed by local scanning of laser, and the formed electromagnetic shielding layer is embedded in the silicon substrate, so that bonding is facilitated and the stability of shielding is ensured.

Description

Semiconductor laser processing method
Technical Field
The invention relates to the field of semiconductor manufacturing, in particular to a semiconductor laser processing method.
Background
Miniaturization and versatility are goals sought in the industry for semiconductor device fabrication. In the prior art, the diversification of functions is usually realized by adopting a subsequent multi-chip packaging process. The packaging process needs additional plastic packaging materials, and the packaging process has the disadvantages of mismatched stress and larger volume.
Disclosure of Invention
Based on solving the above problems, the present invention provides a semiconductor laser processing method, which includes the steps of:
(1) providing a first substrate comprising a first active region at an active face thereof and a plurality of first contact doping regions in the first active region;
(2) forming a patterned metal layer on the passive layer of the first substrate, the patterned metal layer including a first pattern directly below the first active region and a plurality of second patterns around the first pattern;
(3) laser irradiating the patterned metal layer such that first metal silicide regions are formed between the first pattern and the first substrate and second metal silicide regions are formed between the second patterns and the first substrate;
(4) grinding and removing the patterned metal layer to enable the first metal silicide region and the second metal silicide regions to leak out from the passive surface of the first substrate;
(5) providing a second substrate comprising a second active region at an active face thereof and a plurality of second contact doping regions in the second active region;
(6) the active surface of the second substrate is closely attached to the passive surface of the first substrate, and the active surface of the second substrate and the passive surface of the first substrate are subjected to hybrid bonding by utilizing a hot pressing technology;
(7) irradiating laser from the active surface of the first substrate to form an opening and filling a conductive material to form a plurality of first through holes electrically connecting the plurality of second metal silicide regions and a second through hole exposing the first metal silicide region;
(8) and forming a wiring layer on the active surface of the first substrate, wherein the wiring layer is electrically connected with the first through hole, the second through hole and/or the plurality of first contact doped regions.
According to the embodiment of the invention, the method further comprises a step (9) of irradiating the part of the wiring layer on the plurality of first contact doping regions with laser light to form a plurality of third metal silicide regions between the plurality of first contact doping regions and the wiring layer.
According to the embodiment of the invention, the method further comprises the step (10) of covering a dielectric layer on the active surface of the first substrate and forming a plurality of third through holes which are electrically connected with the wiring layer in the dielectric layer.
According to an embodiment of the present invention, the third vias include at least one via directly contacting the third metal silicide regions.
According to an embodiment of the present invention, the first pattern is a square planar pattern, and the first metal silicide region is a patterned structure including a connection portion having at least one opening and a plurality of branch portions connected to the connection portion.
According to an embodiment of the present invention, in the step (6), the hybrid bonding includes a homogeneous bonding of the first substrate and the silicon material of the second substrate and a heterogeneous bonding of the first metal silicide region and the plurality of second metal silicide regions and the silicon material of the second substrate.
According to an embodiment of the invention, the second via is a ground via.
The invention also provides a semiconductor device formed by the semiconductor laser processing method.
The invention has the following advantages:
the invention utilizes the previous working procedure to carry out the hybrid bonding of two silicon substrate chips, the bonding surface comprises a metal silicide region, the metal silicide region and a silicon material have better bonding effect, and the metal silicide simultaneously serves as an ohmic contact and an electromagnetic shielding layer. In particular, the metal silicide region is formed by local scanning of laser, and the formed electromagnetic shielding layer is embedded in the silicon substrate, so that bonding is facilitated and the stability of shielding is ensured.
Drawings
FIG. 1 is a cross-sectional view of a semiconductor device of the present invention;
FIG. 2 is a schematic view of a first metal silicide region;
fig. 3-10 are process schematic diagrams of the semiconductor laser processing method of the present invention.
Detailed Description
The present technology will be described with reference to the drawings in the embodiments, it being understood that the present technology may be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the technology to those skilled in the art. Indeed, the technology is intended to cover alternatives, modifications and equivalents of these embodiments, which are included within the scope and spirit of the technology as defined by the appended claims. Furthermore, in the following detailed description of the present technology, numerous specific details are set forth in order to provide a thorough understanding of the present technology. It will be apparent, however, to one skilled in the art that the present technology may be practiced without these specific details.
The terms "top" and "bottom," upper "and" lower, "and" vertical "and" horizontal, "and their various forms, as used herein, are for purposes of illustration and description only and are not intended to limit the description of the technology, as the referenced items may be interchanged in position and orientation. Also, as used herein, the terms "substantially" and/or "about" mean that the specified dimensions or parameters may vary within acceptable manufacturing tolerances for a given application.
Referring first to fig. 1, the semiconductor device of the present invention includes a first substrate 10 and a second substrate 18. The first substrate 10 and the second substrate 18 are both silicon substrates, and the first substrate 10 and the second substrate 18 are both substrates having a chip structure. The first substrate 10 may have an integrated circuit chip such as a radio frequency chip, an antenna chip, etc., thereon, and the second substrate 18 may have an integrated circuit chip such as a controller, an amplifier, a rectifier, etc., thereon.
The first substrate 10 includes a first active region 11 on an active surface and a plurality of first contact doping regions 12 in the first active region 11, wherein the first contact doping regions 12 are heavily doped regions of silicon, which may be source and drain doping regions of a MOS structure, for example. The body material of the first contact doping region 12 is silicon, which can be formed by doping P or As. The bottom of the first active region 11 is at a distance from the passive side of said first substrate 10.
The first substrate 10 has a first metal silicide region 16 directly under the first active region 11 on a passive side (i.e., a bottom side), the area of the first metal silicide region 16 is larger than that of the first active region 11, and the first metal silicide region 16 is formed by locally irradiating a metal layer covering the passive side of the first substrate 10 with laser light, and the first metal silicide region 16 is embedded in the first substrate 10.
There are also a plurality of second metal suicide regions 17 on the inactive (i.e. bottom) side of the first substrate 10, which second metal suicide regions 17 can be used as electrical connections. The second metal suicide regions 17 are formed around the first metal suicide regions and are also formed by locally irradiating the metal layer overlying the passive side of the first substrate 10 with laser light. The material of the first metal silicide region 16 and the second metal silicide region 17 may be a nickel silicon material, a copper silicon material, or an aluminum silicon material.
The second substrate 18 has a second active region 19 on the active surface and a plurality of second contact doped regions 20 in the second active region 19, where the second contact doped regions 20 are heavily doped regions of silicon, which may be, for example, source and drain doped regions of a MOS structure. The body material of the second contact doping region 20 is silicon, which can be formed by doping P or As.
The inactive surface of the first substrate 10 and the active surface of the second substrate 18 are tightly bonded together, and the second contact doping regions 20 and the second metal silicide regions 17 are in one-to-one correspondence and form ohmic contacts, and the first metal silicide regions 16 are bonded with the silicon material of the second substrate 18.
There are also a plurality of first vias 21 and second vias 22 in the first substrate 10, the first vias 21 directly contacting the second metal suicide regions 17 and the second vias 22 directly contacting the first metal suicide regions 16. The first via 21 and the second via 22 surround the first active region 11 of the first substrate 10, and the second via 22 is a ground via for grounding of a shield signal.
A wiring layer 23 is directly formed on the active surface of the first substrate 10, and the wiring layer 23 electrically connects the first via hole 21, the second via hole 22, and/or the plurality of first contact doping regions 12. Here, in order to make the wiring layer 23 in ohmic contact with the first contact doping region 12, the wiring layer 23 above the first contact doping region 12 is irradiated with laser light to form the third metal silicide region 24, and the metal silicide region 24 is illustrated as the entire wiring layer 23 above the first contact doping region 12, but it may be formed only between the wiring layer 24 and the first contact doping region 12 as the third metal silicide region 24. The material of the wiring layer 23 may be nickel, copper, aluminum, or the like.
A dielectric layer 25 is covered on the active surface of the first substrate 10, and a plurality of third via holes 26 electrically connecting the wiring layers 23 are formed in the dielectric layer 25. A portion of the plurality of third vias 26 directly contacts the third metal suicide region 24. The dielectric layer 25 is formed by a chemical vapor deposition method or a physical vapor deposition method, and the material thereof may be silicon oxide or silicon nitride.
The first metal silicide region 16 is a patterned structure, which includes a connection portion 161 having at least one opening 164 and having a ring shape, a plurality of stem portions 162 coupled to the connection portion 161, and a plurality of branch portions 163 coupled to the plurality of stem portions 162, as shown in fig. 2. The at least one opening 164 may reduce eddy currents in the shield. The first metal silicide regions 16 are designed such that they can be directly connected to ground, which serves as a shield, especially when the first substrate 10 comprises a rf chip or antenna chip structure.
The semiconductor laser processing method will be described with reference to fig. 3 to 10, which specifically includes the following steps:
(1) providing a first substrate comprising a first active region at an active face thereof and a plurality of first contact doping regions in the first active region;
(2) forming a patterned metal layer on the passive layer of the first substrate, the patterned metal layer including a first pattern directly below the first active region and a plurality of second patterns around the first pattern;
(3) laser irradiating the patterned metal layer such that first metal silicide regions are formed between the first pattern and the first substrate and second metal silicide regions are formed between the second patterns and the first substrate;
(4) grinding and removing the patterned metal layer to enable the first metal silicide region and the second metal silicide regions to leak out from the passive surface of the first substrate;
(5) providing a second substrate comprising a second active region at an active face thereof and a plurality of second contact doping regions in the second active region;
(6) the active surface of the second substrate is closely attached to the passive surface of the first substrate, and the active surface of the second substrate and the passive surface of the first substrate are subjected to hybrid bonding by utilizing a hot pressing technology;
(7) irradiating laser from the active surface of the first substrate to form an opening and filling a conductive material to form a plurality of first through holes exposing the plurality of second metal silicide regions and a second through hole exposing the first metal silicide region;
(8) and forming a wiring layer on the active surface of the first substrate, wherein the wiring layer is electrically connected with the first through hole, the second through hole and/or the plurality of first contact doped regions.
Referring first to fig. 3, a first substrate 10 is provided, as previously described, the first substrate 10 being a silicon substrate, which may be formed by dicing singulation from a wafer. The first substrate 10 includes a first active region 11 at an active surface thereof and a plurality of first contact doping regions 12 in the first active region 11.
Referring to fig. 4, a patterned metal layer 13 is formed on the passive layer of the first substrate 10 by a deposition or sputtering method, and the patterned metal layer 13 includes a first pattern 14 directly under the first active region 11 and a plurality of second patterns 15 around the first pattern 14. The patterned metal layer 13 may be nickel or copper and may be thin, for example less than 100 μm thick. The first pattern 14 is a square planar pattern.
Referring next to fig. 5, the laser irradiates the patterned metal layer 14 such that a first metal silicide region 16 is formed between the first pattern 14 and the first substrate 10 and a plurality of second metal silicide regions 17 are formed between the plurality of second patterns 15 and the first substrate 10.
Then, the patterned metal layer 14 is removed by grinding, so that the first metal silicide region 16 and the plurality of second metal silicide regions 17 leak out from the passive surface of the first substrate 10, and at this time, the three are coplanar.
Referring to fig. 6, a second substrate 18 is provided, said second substrate 18 comprising a second active region 19 at its active face and a plurality of second contact doping regions 20 in said second active region 19. And closely attaching the active surface of the second substrate 18 to the passive surface of the first substrate 10, and performing hybrid bonding on the active surface of the second substrate 18 and the passive surface of the first substrate 10 by using a hot pressing technology, wherein the hybrid bonding comprises homogeneous bonding of the first substrate 10 and the silicon material of the second substrate 18 and heterogeneous bonding of the first metal silicide region 16 and the plurality of second metal silicide regions 17 and the silicon material of the second substrate 18.
Then, referring to fig. 7, an opening is formed by irradiating laser from the active surface of the first substrate 10 and filled with a conductive material to form a plurality of first via holes 21 electrically connecting the plurality of second metal silicide regions 17 and a second via hole 22 exposing the first metal silicide region 16.
A patterned wiring layer 23 is formed on the active surface of the first substrate 10 by a deposition or sputtering process, the wiring layer 23 electrically connecting the first via 21, the second via 22 and/or the plurality of first contact doping regions 12, see in particular fig. 8.
In order to form ohmic contact of the wiring layer 23 with the first contact doping regions 12, portions of the wiring layer 23 on the plurality of first contact doping regions 12 are irradiated with laser light to form a plurality of third metal silicide regions 24 between the plurality of first contact doping regions 12 and the wiring layer 23, see fig. 9.
Finally, referring to fig. 10, a dielectric layer 25 is covered on the active surface of the first substrate 10, and a plurality of third via holes 26 electrically connecting the wiring layers 23 are formed in the dielectric layer 25. The dielectric layer 25 may be silicon oxide or silicon nitride and may be formed by deposition. Wherein the third vias 26 comprise at least one via that directly contacts the third metal silicide regions 24.
In summary, the present invention utilizes the previous process to perform hybrid bonding of two silicon substrate chips, the bonding surface includes metal silicide regions (first and second metal silicide regions) that have better bonding effect with the silicon material, and the metal silicide layer (i.e. the first metal silicide region) serves as both an ohmic contact and an electromagnetic shielding layer. In particular, the metal silicide region is formed by local scanning of laser, and the formed electromagnetic shielding layer is embedded in the silicon substrate, so that bonding is facilitated and the stability of shielding is ensured.
The foregoing detailed description of the technology has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the technology to the precise form disclosed. Many modifications and variations are possible in light of the above teaching. The described embodiments were chosen in order to best explain the principles of the technology and its practical application to thereby enable others skilled in the art to best utilize the technology in various embodiments and with various modifications as are suited to the particular use contemplated. The scope of the present technology is defined by the appended claims.
The expressions "exemplary embodiment," "example," and the like, as used herein, do not refer to the same embodiment, but are provided to emphasize different particular features. However, the above examples and exemplary embodiments do not preclude their implementation in combination with features of other examples. For example, even in a case where a description of a specific example is not provided in another example, unless otherwise stated or contrary to the description in the other example, the description may be understood as an explanation relating to the other example.
The terminology used in the present invention is for the purpose of illustrating examples only and is not intended to be limiting of the invention. Unless the context clearly dictates otherwise, singular expressions include plural expressions.
While example embodiments have been shown and described, it will be apparent to those skilled in the art that modifications and changes may be made without departing from the scope of the invention as defined by the claims.

Claims (8)

1. A semiconductor laser processing method, comprising the steps of:
(1) providing a first substrate comprising a first active region at an active face thereof and a plurality of first contact doping regions in the first active region;
(2) forming a patterned metal layer on the passive layer of the first substrate, the patterned metal layer including a first pattern directly below the first active region and a plurality of second patterns around the first pattern;
(3) laser irradiating the patterned metal layer such that first metal silicide regions are formed between the first pattern and the first substrate and second metal silicide regions are formed between the second patterns and the first substrate;
(4) grinding and removing the patterned metal layer to enable the first metal silicide region and the second metal silicide regions to leak out from the passive surface of the first substrate;
(5) providing a second substrate comprising a second active region at an active face thereof and a plurality of second contact doping regions in the second active region;
(6) the active surface of the second substrate is closely attached to the passive surface of the first substrate, and the active surface of the second substrate and the passive surface of the first substrate are subjected to hybrid bonding by utilizing a hot pressing technology;
(7) irradiating laser from the active surface of the first substrate to form an opening and filling a conductive material to form a plurality of first through holes electrically connecting the plurality of second metal silicide regions and a second through hole exposing the first metal silicide region;
(8) and forming a wiring layer on the active surface of the first substrate, wherein the wiring layer is electrically connected with the first through hole, the second through hole and/or the plurality of first contact doped regions.
2. The semiconductor laser processing method according to claim 1, characterized in that: the method further comprises a step (9) of irradiating the parts of the wiring layer on the first contact doping regions with laser light to form a plurality of third metal silicide regions between the first contact doping regions and the wiring layer.
3. The semiconductor laser processing method according to claim 2, characterized in that: the method further comprises the step (10) of covering a dielectric layer on the active surface of the first substrate and forming a plurality of third through holes in the dielectric layer, wherein the third through holes are electrically connected with the wiring layer.
4. The semiconductor laser processing method according to claim 3, characterized in that: the third vias include at least one via that directly contacts the third metal silicide regions.
5. The semiconductor laser processing method according to claim 1, characterized in that: the first pattern is a square planar pattern, and the first metal silicide region is a patterned structure including a ring-shaped connecting portion having at least one opening, a plurality of trunk portions joined to the connecting portion, and a plurality of branch portions joined to the trunk portions.
6. The semiconductor laser processing method according to claim 1, characterized in that: in step (6), the hybrid bonding includes a homogeneous bonding of the first substrate and the silicon material of the second substrate and a heterogeneous bonding of the first metal silicide region and the plurality of second metal silicide regions and the silicon material of the second substrate.
7. The semiconductor laser processing method according to claim 6, characterized in that: the second through hole is a ground through hole.
8. A semiconductor device formed by the semiconductor laser processing method according to any one of claims 1 to 7.
CN202110245825.XA 2021-03-05 2021-03-05 Semiconductor laser processing method Withdrawn CN113066717A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116507123A (en) * 2023-06-26 2023-07-28 北京超弦存储器研究院 Semiconductor device, manufacturing method thereof and electronic equipment

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116507123A (en) * 2023-06-26 2023-07-28 北京超弦存储器研究院 Semiconductor device, manufacturing method thereof and electronic equipment
CN116507123B (en) * 2023-06-26 2023-09-05 北京超弦存储器研究院 Semiconductor device, manufacturing method thereof and electronic equipment

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Application publication date: 20210702