CN113055007A - Low-cost zero-delay SAR-ADC hardware correction algorithm - Google Patents
Low-cost zero-delay SAR-ADC hardware correction algorithm Download PDFInfo
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Abstract
A low-cost zero-delay SAR-ADC hardware correction algorithm adopts the following processing steps: s1, defining a register AM and a register AK, configuring a hardware algorithm circuit through the register AM and the register AK, wherein the sign bit of the register AM is Fm, the sign bit of the register AK is Fk, and the hardware algorithm circuit takes ADC output data Ya as input; s2, the arithmetic circuit obtains a correction value TEMP1 through Ya, wherein TEMP1 is Ya + (FmAM: -AM); s3, the arithmetic circuit obtains a corrected value TEMP2 through TEMP1, wherein TEMP2 is (FkAK: -AK) × TEMP 1; and S4, the algorithm circuit obtains the ADC output data correction value Yb according to the correction value TEMP1 and the correction value TEMP2, wherein Yb is TEMP1+ TEMP 2. The register is provided with a hardware algorithm circuit, the calculation method is simple, the sampling time of the ADC is not occupied, the correction of the ADC can be simplified, and the method has the characteristics of low consumption and zero time delay.
Description
Technical Field
The invention relates to the technical field of SAR-ADC, in particular to a low-cost zero-delay SAR-ADC hardware correction algorithm.
Background
Successive approximation register analog-to-digital converters (SAR-ADCs) occupy most of the medium to high resolution ADC markets, with sampling rates up to 5Msps and resolutions of 8-bit to 18-bit. In view of the fact that the SAR framework allows the high-performance and low-power consumption ADC to be packaged in a small size and has the characteristics of high speed, low cost and high precision, the SAR-ADC is particularly suitable for a system with strict requirements on size and is widely integrated in an MCU chip.
However, due to the deviation of the production process, the ADC characteristics of each chip will have a little deviation, so that calibration and compensation are required to obtain better consistency. At present, a conventional compensation method is implemented through software compensation, and the currently known hardware compensation method generally has the defects of large resource consumption, clock occupation and the like.
Disclosure of Invention
In order to make up for the above defects in the prior art, the invention provides a low-cost zero-delay SAR-ADC hardware correction algorithm, and the technical scheme is as follows.
A low-cost zero-delay SAR-ADC hardware correction algorithm adopts the following processing steps:
s1, defining a register AM and a register AK, configuring a hardware algorithm circuit through the register AM and the register AK, wherein the sign bit of the register AM is Fm, the sign bit of the register AK is Fk, and the hardware algorithm circuit takes ADC output data Ya as input;
s2, the arithmetic circuit obtains the correction value TEMP1 through Ya, wherein
TEMP1＝Ya+(FmAM:-AM)；
S3, the arithmetic circuit obtains the correcting value TEMP2 through TEMP1, wherein
TEMP2＝(FkAK:-AK)*TEMP1；
S4, the algorithm circuit obtains the correction value Yb of the ADC output data according to the correction value TEMP1 and the correction value TEMP2
Yb＝TEMP1+TEMP2。
Compared with the prior art, the invention has the beneficial effects that: the register is provided with a hardware algorithm circuit, the calculation method is simple, the sampling time of the ADC is not occupied, the correction of the ADC can be simplified, and the method has the characteristics of low consumption and zero time delay.
The present invention will be further described with reference to specific embodiments.
Detailed Description
A low-cost zero-delay SAR-ADC hardware correction algorithm adopts the following processing steps:
s1, defining a register AM and a register AK, configuring a hardware algorithm circuit through the register AM and the register AK, wherein the sign bit of the register AM is Fm, the sign bit of the register AK is Fk, and the hardware algorithm circuit takes ADC output data Ya as input;
s2, the arithmetic circuit obtains the correction value TEMP1 through Ya, wherein
TEMP1＝Ya+(FmAM:-AM)；
S3, the arithmetic circuit obtains the correcting value TEMP2 through TEMP1, wherein
TEMP2＝(FkAK:-AK)*TEMP1；
S4, the algorithm circuit obtains the correction value Yb of the ADC output data according to the correction value TEMP1 and the correction value TEMP2
Yb＝TEMP1+TEMP2。
In the embodiment, a hardware algorithm circuit is configured through the register, the calculation method is simple, the sampling time of the ADC is not occupied, the correction of the ADC can be calculated in the simplest mode, and the method has the advantages of being low in consumption and zero in time delay.
In addition to the above embodiment, in step S1, the register AM and its sign bit Fm, and the register AK and its sign bit Fk are defined as follows:
s11, sampling ADC output data under two ideal ADC input voltages, and fitting a unary linear equation of the ADC input voltage X and the ADC output data Ya according to the two ideal ADC input voltages to be Ya (Ka X + Ma);
wherein Ka and Ma are preset equation coefficients;
s12, presetting ideal ADC output data Yb ═ Kb × X;
kb is a preset equation coefficient;
accordingly, the ideal ADC output data Yb ═ Kb/Ka ═ Ya-Ma;
on the basis, the ideal ADC output data Yb is further converted into the ideal ADC output data Yb by substituting the register AM and the sign bit Fm thereof, the register AK and the sign bit Fk thereof
Yb＝(1+(Fk？|(Kb-Ka)/Ka|:-|(Kb-Ka)/Ka|)*(Ya+(Fm？|Ma|:-|Ma|))
AM, AK, Fm and Fk which need to be configured are calculated according to the calculation, and the definitions of the register AM and the sign bit Fm thereof, the register AK and the sign bit Fk thereof are carried out according to the calculation.
Further, in step S12, since | Kb-Ka/Ka | is a relatively small decimal, Kc/16384 is used instead, where Kc is a number smaller than 256 and | Ma | is also a number smaller than 256; defining register AM ═ Ma |, defining register AK ═ Kc, ideal ADC output data Yb are further converted into
Yb＝(1+(FkAK:-AK)/16384)&(Ya+(FmAM:-AM))；
AM, AK, Fm and Fk which need to be configured are calculated according to the calculation, and the definitions of the register AM and the sign bit Fm thereof, the register AK and the sign bit Fk thereof are carried out according to the calculation.
It will be clear to a person skilled in the art that the scope of protection of the present invention is not limited to details of the foregoing illustrative embodiments, and that all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein by the appended claims without departing from the spirit or essential characteristics thereof.
Claims (3)
1. A low-cost zero-delay SAR-ADC hardware correction algorithm is characterized by comprising the following processing steps:
s1, defining a register AM and a register AK, configuring a hardware algorithm circuit through the register AM and the register AK, wherein the sign bit of the register AM is Fm, the sign bit of the register AK is Fk, and the hardware algorithm circuit takes ADC output data Ya as input;
s2, the arithmetic circuit obtains the correction value TEMP1 through Ya, wherein
TEMP1＝Ya+(FmAM:-AM)；
S3, the arithmetic circuit obtains the correcting value TEMP2 through TEMP1, wherein
TEMP2＝(FkAK:-AK)*TEMP1；
S4, the algorithm circuit obtains the correction value Yb of the ADC output data according to the correction value TEMP1 and the correction value TEMP2
Yb＝TEMP1+TEMP2。
2. The low-cost zero-delay SAR-ADC hardware correction algorithm of claim 1, wherein in step S1, the definition of the register AM and its sign bit Fm, the register AK and its sign bit Fk adopts the following steps:
s11, sampling ADC output data under two ideal ADC input voltages, and fitting a unary linear equation of the ADC input voltage X and the ADC output data Ya according to the two ideal ADC input voltages to be Ya (Ka X + Ma);
wherein Ka and Ma are preset equation coefficients;
s12, presetting ideal ADC output data Yb ═ Kb × X;
kb is a preset equation coefficient;
accordingly, the ideal ADC output data Yb ═ Kb/Ka ═ Ya-Ma;
on the basis, the ideal ADC output data Yb is further converted into the ideal ADC output data Yb by substituting the register AM and the sign bit Fm thereof, the register AK and the sign bit Fk thereof
Yb＝(1+(Fk？|(Kb-Ka)/Ka|:-|(Kb-Ka)/Ka|)*(Ya+(Fm？|Ma|:-|Ma|))
AM, AK, Fm and Fk which need to be configured are calculated according to the calculation, and the definitions of the register AM and the sign bit Fm thereof, the register AK and the sign bit Fk thereof are carried out according to the calculation.
3. A low cost zero delay SAR-ADC hardware correction algorithm as claimed in claim 2, wherein in step S12, given that | Kb-Ka/Ka | is a relatively small decimal, it is replaced by Kc/16384, where Kc is a number less than 256 and | Ma | is also a number less than 256; defining register AM ═ Ma |, defining register AK ═ Kc, ideal ADC output data Yb are further converted into
Yb＝(1+(FkAK:-AK)/16384)&(Ya+(FmAM:-AM))；
AM, AK, Fm and Fk which need to be configured are calculated according to the calculation, and the definitions of the register AM and the sign bit Fm thereof, the register AK and the sign bit Fk thereof are carried out according to the calculation.
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- 2021-03-25 CN CN202110321763.6A patent/CN113055007A/en active Pending
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| CN102938647A (en) * | 2012-11-20 | 2013-02-20 | 华为技术有限公司 | Conversion circuit and chip |
| CN106941354A (en) * | 2017-04-17 | 2017-07-11 | 北京机械设备研究所 | A kind of hardware circuit bearing calibration based on Mathematical Fitting |
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| CN111800131A (en) * | 2019-04-03 | 2020-10-20 | 半导体元件工业有限责任公司 | Calibration circuit and method for calibrating ADC output codes from a set of analog-to-digital converters |
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Application publication date: 20210629 |