CN113054912A - Photoelectric monolithic integrated chip of PIN detector and trans-impedance amplifier and preparation method - Google Patents
Photoelectric monolithic integrated chip of PIN detector and trans-impedance amplifier and preparation method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
Abstract
The present disclosure provides a monolithic optoelectronic integrated chip of a silicon-based PIN detector and a transimpedance amplifier, comprising: the device comprises a silicon-based PIN detector, a transverse NPN triode, a first resistor and a second resistor; the transverse NPN triode, the first resistor and the second resistor form a transimpedance amplifier and are connected with the silicon-based PIN detector; the silicon-based PIN detector is used for detecting a laser signal and generating a current signal; the trans-impedance amplifier is used for amplifying and outputting a current signal. The photoelectric monolithic integrated chip realizes the integration of the laser detector and the trans-impedance amplifier, can effectively improve the anti-interference capability of the laser receiving module, and enhances the signal stability. In addition, the disclosure also provides a preparation method of the chip, and the method is simple in process and easy to implement.
Description
Technical Field
The disclosure relates to the technical field of photoelectric monolithic integration, in particular to a photoelectric monolithic integrated chip of a silicon-based PIN detector and a transimpedance amplifier and a preparation method thereof.
Background
The infrared laser fuse technology is a technology for detecting a target by transmitting a pulse laser signal and achieving the detection purpose by identifying a reflected pulse laser signal. The two modules are packaged in the same metal tube shell, the distance is very short, and when the transmitting module works, the pulse heavy current generated by the driving circuit of the semiconductor laser can cause strong electromagnetic interference to the laser receiving module. In addition, since the laser fuze system works in an external environment, when the photocurrent signal received by the detector is small, in order to prevent the remote tiny photocurrent signal detected by the detector in the laser receiving module from being submerged by electromagnetic noise, the signal-to-noise ratio of the signal at the output end of the detector needs to be improved. Since electromagnetic interference in the laser emission module cannot be avoided, the size of the output end signal on the detector must be increased.
The optoelectronic monolithic integrated chip is an integrated chip with optical and electrical signal processing functions, which is formed by manufacturing semiconductor optical devices (such as lasers, detectors, optical waveguides, modulators and the like) and electronic devices (such as bipolar transistors, various field effect transistors and the like) on the same substrate by adopting compatible semiconductor process technology. Compared with the traditional hybrid circuit, the photoelectric monolithic integrated circuit has the advantages of low noise, small volume, high performance, strong stability and the like, meets the requirements of the modern information technology on high speed, miniaturization and multifunctional development, and becomes the mainstream direction of the research on the photoelectric monolithic integrated technology at home and abroad. The preparation technology of the photoelectric monolithic integrated chip is combined with the infrared laser fuse technology, so that the method has a relatively high research prospect.
Disclosure of Invention
In view of the above problems, the present invention provides a monolithic optoelectronic integrated chip of a silicon-based PIN detector and a transimpedance amplifier, and a method for manufacturing the monolithic optoelectronic integrated chip.
The present disclosure provides a monolithic optoelectronic integrated chip of a silicon-based PIN detector and a transimpedance amplifier, comprising: the device comprises a silicon-based PIN detector, a transverse NPN triode, a first resistor and a second resistor; the transverse NPN triode, the first resistor and the second resistor form a transimpedance amplifier and are connected with the silicon-based PIN detector; the silicon-based PIN detector is used for detecting a laser signal and generating a current signal; the trans-impedance amplifier is used for amplifying and outputting the current signal.
Optionally, the method includes: the photoelectric monolithic integrated chip comprises an N + silicon layer, an intrinsic layer and a metal electrode layer from bottom to top in sequence, and is divided into an illumination area and a non-illumination area according to transverse distribution; the silicon-based PIN detector is arranged in the illumination area, and the transverse NPN triode, the first resistor and the second resistor are arranged in the non-illumination area.
Optionally, a first P + layer is disposed in the intrinsic layer of the illumination region, and the first P + layer, the intrinsic layer, and the N + silicon layer of the illumination region form the silicon-based PIN detector.
Optionally, a first isolation region and a second isolation region are respectively disposed in the intrinsic layer of the non-illumination region, the lateral NPN transistor is disposed in the first isolation region, and the first resistor and the second resistor are disposed in the second isolation region.
Optionally, a plurality of electrodes are disposed on the metal electrode layer and respectively connected to the P + layer and the N + silicon layer of the silicon-based PIN detector, the poles of the lateral NPN triode, the first resistor, and the second resistor, and the plurality of electrodes are connected according to a preset circuit to form a circuit for amplifying an output signal of the silicon-based PIN detector.
Optionally, a through hole is formed in the intrinsic layer between the illumination region and the non-illumination region, and an electrode connected with the N + silicon layer of the silicon-based PIN detector on the metal electrode layer is connected to the N + silicon layer through the through hole.
Optionally, a second P + layer is disposed in the first isolation region, and a third P + layer is disposed in the second isolation region, and is connected to the electrode disposed on the metal electrode layer and corresponding to the second P + layer and the third P + layer.
Optionally, the plurality of electrodes are isolated from each other by SiO 2.
Optionally, the method further includes: and the direct current blocking capacitor is used for isolating the direct current signal included in the current signal.
The present disclosure provides a preparation method, applied to prepare the optoelectronic monolithic integrated chip according to the first aspect, including: epitaxially growing an intrinsic layer on an N + type silicon substrate; respectively injecting boron ions into two positions on the intrinsic layer to form a first isolation region and a second isolation region; respectively injecting phosphorus ions into the first isolation region and the second isolation region, forming a collector and an emitter of the transverse NPN triode in the first isolation region, and forming a first resistor and a second resistor in the second isolation region; respectively injecting boron ions into the first isolation region, the second isolation region and the intrinsic region except the first isolation region and the second isolation region to respectively form a second P + layer, a third P + layer and a first P + layer; depositing SiO2 on the surface of the intrinsic layer to be used as a masking layer of the wet etching intrinsic layer, photoetching an etching window, and etching a metal contact hole to form a plurality of metal electrodes; re-depositing SiO2 as a passivation anti-reflection film, and forming the plurality of metal electrode interconnections by means of alignment; the interconnection of the plurality of metal electrodes enables the NPN triode, the first resistor and the second resistor to form a transimpedance amplifier and be connected with the silicon-based PIN detector, so that a circuit for amplifying the output of the base PIN detector is formed.
The at least one technical scheme adopted in the embodiment of the disclosure can achieve the following beneficial effects:
the photoelectric monolithic integrated chip of the PIN detector and the transimpedance amplifier provided by the disclosure is characterized in that the transimpedance amplifier is integrated by utilizing the area of a non-illumination area of the PIN detector, and the used triode is a transverse NPN triode. The photoelectric monolithic integrated chip also realizes the compatibility of the PIN detector and the trans-impedance amplifier in the process, and the last key process of the PIN detector, namely the formation of a P + layer by ion implantation and the high-temperature annealing are carried out at last, so that the process parameters of the PIN detector can be ensured not to be changed, and the performance of the PIN detector is ensured not to be changed.
Drawings
For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:
fig. 1 schematically illustrates a schematic diagram of a PCB-based amplifying circuit provided by an embodiment of the present disclosure;
fig. 2 schematically illustrates a schematic diagram of an optoelectronic monolithic integrated chip of a PIN detector and a transimpedance amplifier provided by an embodiment of the present disclosure;
fig. 3 schematically illustrates a schematic diagram of an optoelectronic monolithic integrated chip circuit of a PIN detector and a transimpedance amplifier provided by an embodiment of the present disclosure;
FIG. 4 is a schematic diagram illustrating pulsed photocurrent signals generated by a PIN detector in a test experiment provided by an embodiment of the present disclosure;
fig. 5 schematically shows a signal diagram of amplified pulsed photocurrent signals generated by a PIN detector in a test experiment provided by the embodiment of the disclosure.
Detailed Description
Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. It should be understood that the description is illustrative only and is not intended to limit the scope of the present disclosure. In the following detailed description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the embodiments of the disclosure. It may be evident, however, that one or more embodiments may be practiced without these specific details. Moreover, in the following description, descriptions of well-known structures and techniques are omitted so as to not unnecessarily obscure the concepts of the present disclosure.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. The terms "comprises," "comprising," and the like, as used herein, specify the presence of stated features, steps, operations, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, or components.
All terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art unless otherwise defined. It is noted that the terms used herein should be interpreted as having a meaning that is consistent with the context of this specification and should not be interpreted in an idealized or overly formal sense.
Fig. 1 schematically illustrates a schematic diagram of a PCB-based amplifying circuit provided by an embodiment of the present disclosure.
In the prior art, an amplifying circuit is disposed on a PCB board in a laser receiving module to amplify signals. As shown in fig. 1, the whole amplification circuit is composed of a transimpedance amplifier and a voltage amplifier, wherein the transimpedance amplifier has a certain transimpedance gain, converts a pulsed photocurrent signal of the PIN detector into a pulsed voltage signal, and then inputs the pulsed voltage signal to the next-stage voltage amplifier, and the voltage amplifier further amplifies the input pulsed voltage signal to be processed by a subsequent related circuit. A DC blocking capacitor is added at the output end of each stage of amplifying circuit to filter the dark current noise and other DC components of the detector.
Fig. 2 schematically illustrates a schematic diagram of an optoelectronic monolithic integrated chip of a PIN detector and a transimpedance amplifier provided by an embodiment of the present disclosure.
As shown in fig. 2, an optoelectronic monolithic integrated chip of a PIN detector and a transimpedance amplifier includes: the device comprises a silicon-based PIN detector, a transverse NPN triode, a first resistor and a second resistor; the transverse NPN triode, the first resistor and the second resistor form a transimpedance amplifier and are connected with the silicon-based PIN detector; the silicon-based PIN detector is used for detecting a laser signal and generating a current signal; the trans-impedance amplifier is used for amplifying and outputting the current signal.
Specifically, as shown in fig. 2, the monolithic optoelectronic integrated chip sequentially includes, from bottom to top, an N + silicon layer, an intrinsic layer, and a metal electrode layer, and is divided into an illumination region and a non-illumination region according to lateral distribution. The illumination area is an area for receiving pulse laser signals and is used for converting the pulse laser signals into pulse current signals; the non-illumination area is an area for manufacturing the trans-impedance amplifier and is used for amplifying the pulse photocurrent signal and outputting an amplified pulse voltage signal. The silicon-based PIN detector is arranged in the illumination area, and the transverse NPN triode, the first resistor and the second resistor are arranged in the non-illumination area. A first P + layer is arranged in the intrinsic layer of the illumination area, and the first P + layer, the intrinsic layer and the N + silicon layer of the illumination area form the silicon-based PIN detector. The intrinsic layer of the non-illumination area is respectively provided with a first isolation area and a second isolation area, the transverse NPN triode is arranged in the first isolation area, and the first resistor and the second resistor are arranged in the second isolation area. And a second P + layer is arranged in the first isolation region, a third P + layer is arranged in the second isolation region, and the metal electrode layer is provided with electrodes corresponding to the second P + layer and the third P + layer to be connected, so that ohmic contact is formed. And an emitter, a collector and a base of the transverse NPN triode are arranged in the first isolation region, and the base is a second P + layer in the first isolation region.
The metal electrode layer is provided with a plurality of electrodes which are respectively connected with the P + layer and the N + silicon layer of the silicon-based PIN detector, the poles of the transverse NPN triode, the first resistor and the second resistor, and the plurality of electrodes are connected according to a preset circuit to form a circuit for amplifying the output signal of the silicon-based PIN detector. As can be seen from fig. 2, the electrode material in the present disclosure is Al, and the electrodes are isolated from each other by SiO 2.
Particularly, a through hole is formed in an intrinsic layer between the illumination area and the non-illumination area, and an electrode connected with the N + silicon layer of the silicon-based PIN detector on the metal electrode layer is connected to the N + silicon layer through the through hole.
Fig. 3 schematically illustrates a schematic diagram of an optoelectronic monolithic integrated chip circuit of a PIN detector and a transimpedance amplifier provided by an embodiment of the present disclosure.
As shown in fig. 3, the circuit schematic diagram schematically illustrates a connection manner of a PIN detector and a transimpedance amplifier formed by a lateral NPN transistor, a first resistor, and a second resistor in the optoelectronic monolithic integrated chip provided by the present disclosure, a dc bias of the circuit may be 5V, the lateral NPN transistor is ensured to operate in an amplification region under the dc bias of 5V, the PIN detector does not operate when there is no pulse laser signal, and when the laser pulse signal strikes the PIN detector, the PIN detector generates a pulse photocurrent signal, and the pulse photocurrent signal generated by the PIN detector is amplified as a small signal through the transimpedance amplifier. And finally, the amplified pulse voltage signal is output, wherein the theoretical values of the transimpedance RF and the load resistor RL are 1000 Ω, so that the theoretical amplification factor of the transimpedance amplifier on the pulse photocurrent signal of the PIN detector is 1000 times.
The structural design of the photoelectric monolithic integrated chip is that two P wells are formed by ion implantation by utilizing the area of a non-illumination area of a PIN detector, then required transverse NPN triodes and resistors are respectively manufactured, finally the interconnection of the PIN detector and a transimpedance amplifier is realized by a metal alignment process, and the structural design is consistent with the circuit design.
The optoelectronic monolithic integrated chip provided by the present disclosure may further include a dc blocking capacitor for isolating a dc electrical signal included in the current signal. The direct current signal refers to a noise signal included in the current signal.
The following describes test experiments performed on the optoelectronic monolithically integrated chip provided in the present disclosure.
The test result of the test experiment comprises the response of the PIN detector and the photoelectric monolithic integrated chip under the pulse laser signal, a signal source used for the test is an infrared pulse laser signal, the wavelength is 860nm, the pulse width is 100ns, the working frequency is 10kHz, the distance between a signal source and a target is set to be 5m, and the test principle is as follows: the pulse laser signal emitted by the laser emitting module is reflected by the target, the reflected pulse laser signal irradiates the illumination area of the PIN detector, and then a pulse photocurrent signal is generated, and the result is shown in fig. 4. The pulse voltage signal amplified by the transimpedance amplifier, that is, the test and setup result of the monolithic optoelectronic integrated chip is shown in fig. 5, and the PIN detector and the monolithic optoelectronic integrated chip are tested under the same condition. In order to eliminate the influence of external noise on the test result, the whole test process is carried out in a dark environment.
Fig. 4 schematically shows a diagram of pulsed photocurrent signals generated by a PIN detector in a test experiment provided by an embodiment of the present disclosure.
Fig. 5 schematically shows a signal diagram of amplified pulsed photocurrent signals generated by a PIN detector in a test experiment provided by the embodiment of the disclosure.
Fig. 4 schematically shows the pulsed photocurrent signal detected by the PIN detector, and it can be seen that the pulsed photocurrent signal has a magnitude of about 1.85uA and a pulse width of 110 ns. The pulse response of the monolithic optoelectronic integrated chip is tested under the same test conditions, as shown in fig. 5, it can be seen that the pulse width of the pulse voltage signal is not changed basically, the pulse width is about 1.85mV, and compared with the photocurrent signal 1.85uA of the PIN detector shown in fig. 3, the pulse width is amplified by 1000 times, that is, the transimpedance gain of the transimpedance amplifier is 1000, and the theoretical values of the transimpedance gain and the transimpedance resistance are 1000 Ω.
The photoelectric monolithic integrated chip provided by the disclosure enables the PIN detector and the transimpedance amplifier to be compatible, and can integrate the transimpedance amplifier by using redundant area of the PIN detector on the basis of not changing the structure of the PIN detector.
The present disclosure provides a preparation method, which is applied to prepare the optoelectronic monolithic integrated chip, and includes the following steps.
S220, epitaxially growing an intrinsic layer on the N + type silicon substrate.
In the disclosed embodiment, the N + type silicon substrate is arsenic ion (As)+) The doping thickness is 380um, the crystal orientation is (111), and the resistivity is 0.004 omega cm. The N + type silicon substrate is an intrinsic I layer which is phosphorus ion (P)+) The doped epitaxial layer has a thickness of 40um and a resistivity of 1100 Ω · cm.
And S230, respectively injecting boron ions into two positions on the intrinsic layer to form a first isolation region and a second isolation region.
In the embodiment of the present disclosure, S230 specifically includes S231 to S233.
S231, depositing SiO2 by a PECVD method, and photoetching and carrying out wet etching on the intrinsic layer to form an alignment mark.
S232, depositing SiO2 again to serve as an ion implantation masking layer, photoetching an ion implantation window, implanting boron (B +) ions into the intrinsic layer to form a first isolation region and a second isolation region of the transverse NPN triode, wherein the junction depth is about 900 nm.
And S233, annealing at 850 ℃ for 20 min.
And S240, respectively injecting phosphorus ions into the first isolation region and the second isolation region, forming a collector and an emitter of the lateral NPN triode in the first isolation region, and forming a first resistor and a second resistor in the second isolation region.
In the embodiment of the present disclosure, this step specifically includes S241 to S242.
And S241, redepositing SiO2 as an ion implantation masking layer, photoetching an ion implantation window, and implanting phosphorus (P +) ions into the first isolation region and the second isolation region of the intrinsic layer to respectively form a collector, an emitter and a resistor of the transverse NPN triode, wherein the junction depth is about 350 nm.
And S242, annealing at a high temperature of 800 ℃ for 20 min.
And S250, respectively injecting boron ions into the first isolation region, the second isolation region and the regions of the intrinsic region except the first isolation region and the second isolation region to respectively form a second P + layer, a third P + layer and a first P + layer.
In the embodiment of the present disclosure, this step specifically includes S251 to S252.
S251, redepositing SiO2And as an ion implantation masking layer, photoetching an ion implantation window, and implanting boron (B +) ions into the first isolation region, the second isolation region and the intrinsic region except the first isolation region and the second isolation region to respectively form ohmic contacts of the two well regions and a P + layer of the PIN detector, wherein the junction depth is about 200 nm.
And S252, annealing at a high temperature of 500 ℃ for 10 min.
S260, depositing SiO2 on the surface of the intrinsic layer to serve as a masking layer of the wet etching intrinsic layer, photoetching an etching window, and etching a metal contact hole to form a plurality of metal electrodes.
And S270, depositing SiO2 again to serve as a passivation anti-reflection film, and forming the metal electrode interconnections in an alignment mode.
The interconnection of the plurality of metal electrodes enables the NPN triode, the first resistor and the second resistor to form a transimpedance amplifier and be connected with the silicon-based PIN detector, so that a circuit for amplifying the output of the base PIN detector is formed.
According to the method, under the condition that the structure and the performance of the PIN detector are not changed completely, the trans-impedance amplifier is manufactured by utilizing the non-illumination area of the PIN detector, the compatibility of the structure and the process of the PIN detector and the trans-impedance amplifier is realized, and finally the chip is successfully processed, wherein the trans-impedance gain of the trans-impedance amplifier can be adjusted by adjusting the resistance value, and the transistor used by the trans-impedance amplifier is a transverse NPN triode. The photoelectric monolithic integrated chip is applied to a laser receiving module of a laser fuze system, and a pulse photoelectric current signal detected by a PIN detector is amplified, so that the signal-to-noise ratio of a signal at the output end of the PIN detector can be improved, and the anti-noise capability of the laser receiving module is enhanced.
While the disclosure has been shown and described with reference to certain exemplary embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the disclosure as defined by the appended claims and their equivalents. Accordingly, the scope of the present disclosure should not be limited to the above-described embodiments, but should be defined not only by the appended claims, but also by equivalents thereof.
Claims (10)
1. An optoelectronic monolithic integrated chip of a PIN detector and a transimpedance amplifier, comprising:
the device comprises a silicon-based PIN detector, a transverse NPN triode, a first resistor and a second resistor;
the transverse NPN triode, the first resistor and the second resistor form a transimpedance amplifier and are connected with the silicon-based PIN detector;
the silicon-based PIN detector is used for detecting a laser signal and generating a current signal;
the trans-impedance amplifier is used for amplifying and outputting the current signal.
2. The optoelectronic monolithic integrated chip of claim 1, comprising:
the photoelectric monolithic integrated chip comprises an N + silicon layer, an intrinsic layer and a metal electrode layer from bottom to top in sequence, and is divided into an illumination area and a non-illumination area according to transverse distribution;
the silicon-based PIN detector is arranged in the illumination area, and the transverse NPN triode, the first resistor and the second resistor are arranged in the non-illumination area.
3. The optoelectronic monolithic integrated chip as claimed in claim 2, wherein a first P + layer is disposed in the intrinsic layer of the illumination region, and the first P + layer, the intrinsic layer and the N + silicon layer of the illumination region constitute the silicon-based PIN detector.
4. The optoelectronic monolithic integrated chip as claimed in claim 2, wherein a first isolation region and a second isolation region are respectively disposed in the intrinsic layer of the non-illumination region, the lateral NPN transistor is disposed in the first isolation region, and the first resistor and the second resistor are disposed in the second isolation region.
5. The optoelectronic monolithic integrated chip according to claim 2, wherein the metal electrode layer is provided with a plurality of electrodes, and the electrodes are respectively connected to the P + layer and the N + silicon layer of the silicon-based PIN detector, the respective poles of the lateral NPN triode, the first resistor, and the second resistor, and the plurality of electrodes are connected according to a preset circuit to form a circuit for amplifying the output signal of the silicon-based PIN detector.
6. The method according to claim 5, wherein a through hole is formed in the intrinsic layer between the illumination region and the non-illumination region, and an electrode connected with the N + silicon layer of the silicon-based PIN detector on the metal electrode layer is connected to the N + silicon layer through the through hole.
7. The optoelectronic monolithic integrated chip according to claim 4, wherein a second P + layer is disposed in the first isolation region, a third P + layer is disposed in the second isolation region, and the second P + layer is connected to the electrode disposed on the metal electrode layer and corresponding to the second P + layer and the third P + layer.
8. The optoelectronic monolithic integrated chip according to claim 5, wherein the plurality of electrodes are isolated from each other by SiO 2.
9. The optoelectronic monolithic integrated chip of claim 1, further comprising:
and the direct current blocking capacitor is used for isolating the direct current signal included in the current signal.
10. A preparation method for preparing the optoelectronic monolithic integrated chip as claimed in claims 1 to 9, comprising:
epitaxially growing an intrinsic layer on an N + type silicon substrate;
respectively injecting boron ions into two positions on the intrinsic layer to form a first isolation region and a second isolation region;
respectively injecting phosphorus ions into the first isolation region and the second isolation region, forming a collector and an emitter of the transverse NPN triode in the first isolation region, and forming a first resistor and a second resistor in the second isolation region;
respectively injecting boron ions into the first isolation region, the second isolation region and the intrinsic region except the first isolation region and the second isolation region to respectively form a second P + layer, a third P + layer and a first P + layer;
depositing SiO2 on the surface of the intrinsic layer to be used as a masking layer of the wet etching intrinsic layer, photoetching an etching window, and etching a metal contact hole to form a plurality of metal electrodes;
re-depositing SiO2 as a passivation anti-reflection film, and forming the plurality of metal electrode interconnections by means of alignment;
the interconnection of the plurality of metal electrodes enables the NPN triode, the first resistor and the second resistor to form a transimpedance amplifier and be connected with the silicon-based PIN detector, so that a circuit for amplifying the output of the base PIN detector is formed.
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| CN (1) | CN113054912A (en) |
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| US5311020A (en) * | 1992-11-04 | 1994-05-10 | Trw Inc. | Monolithically-integrated semiconductor/superconductor infrared detector and readout circuit |
| CN101132653A (en) * | 2006-08-25 | 2008-02-27 | 中国科学院声学研究所 | Optical fiber silicon microphone system based on phase carrier modulation |
| CN101308671A (en) * | 2008-07-10 | 2008-11-19 | 中国科学院化学研究所 | Data reading method for super-high density information storage |
| CN107979420A (en) * | 2017-11-21 | 2018-05-01 | 深圳市光为光通信科技有限公司 | CXP optical modules and optical communication apparatus |
| CN209859951U (en) * | 2019-05-23 | 2019-12-27 | 浙江机电职业技术学院 | Photoelectric integrated sensor for intelligent instrument |
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2021
- 2021-03-09 CN CN202110257855.2A patent/CN113054912A/en active Pending
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5311020A (en) * | 1992-11-04 | 1994-05-10 | Trw Inc. | Monolithically-integrated semiconductor/superconductor infrared detector and readout circuit |
| CN101132653A (en) * | 2006-08-25 | 2008-02-27 | 中国科学院声学研究所 | Optical fiber silicon microphone system based on phase carrier modulation |
| CN101308671A (en) * | 2008-07-10 | 2008-11-19 | 中国科学院化学研究所 | Data reading method for super-high density information storage |
| CN107979420A (en) * | 2017-11-21 | 2018-05-01 | 深圳市光为光通信科技有限公司 | CXP optical modules and optical communication apparatus |
| CN209859951U (en) * | 2019-05-23 | 2019-12-27 | 浙江机电职业技术学院 | Photoelectric integrated sensor for intelligent instrument |
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