CN113053997B - 高压碳化硅器件的结终端扩展结构及其制造方法 - Google Patents

高压碳化硅器件的结终端扩展结构及其制造方法 Download PDF

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CN113053997B
CN113053997B CN202011588647.2A CN202011588647A CN113053997B CN 113053997 B CN113053997 B CN 113053997B CN 202011588647 A CN202011588647 A CN 202011588647A CN 113053997 B CN113053997 B CN 113053997B
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邓小川
陶梦玲
吴昊
刘瑞
姜春艳
严静融
张波
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State Grid Smart Grid Research Institute Co ltd
University of Electronic Science and Technology of China
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Global Energy Interconnection Research Institute
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Abstract

本发明公开了一种高压碳化硅功率器件的结终端扩展结构及其制造方法,该扩展结构包括N+型衬底、N‑型漂移区、第一P型结终端扩展区、第二P型结终端扩展区、P型主结、N+场截止环、第一金属电极层和第二金属电极层,第一P型结终端扩展区和第二P型结终端扩展区分别注入高低不同的浓度,同时将第一P型结终端扩展区和第二P型结终端扩展区在版图上通过直角三角形或直角梯形斜边对接平铺形成。本发明通过两种掺杂P型结终端扩展区在第三维度交叉结合,从而实现碳化硅终端结构等效横向变掺杂,使电场均匀分布,在保证终端效率的前提下缩小终端面积,从而能制造出芯片面积更小的高压碳化硅功率器件。

Description

高压碳化硅器件的结终端扩展结构及其制造方法
技术领域
本发明涉及半导体技术领域,特别是涉及高压碳化硅功率器件的结终端扩展结构及其制作方法。
背景技术
碳化硅(Silicon Carbide)材料作为第三代宽禁带半导体材料的代表之一,基于碳化硅材料制作的高压功率器件较传统的硅器件具有优异的电、热性能,可以满足更苛刻的应用环境,其在电源、光伏发电、电动汽车、航天航空等领域有着广泛应用。高压以及超高压(>10kV)的SiC二极管和金属氧化物半导体场效应晶体管(MOSFET)将朝着小型化、高效化、低能耗、轻量化的方向发展。
对于超高压SiC功率器件,结终端结构的设计是一大难点问题。由于考虑到实际芯片的曲率效应,超高压SiC功率器件必须采用合适的终端结构来改善电场集中现象。目前普遍采用的多区结终端扩展(JTE)或场限环(FLR)终端结构,前者由于分区数量有限,不同区域之间的浓度突变,容易引入新的电场尖峰,导致表面电场的效率远低于理想终端;后者场限环结终端结构需要的环个数多、终端长度很长、终端占有的面积增大,该结终端结构设计难度高,工艺精度要求高,制造成本很高。
为了进一步提高终端结构的效率,横向变掺杂(Variation of Lateral Doping,VLD)终端的概念被提出,这种技术是用浓度或剂量线性变化的分布来获得表面均匀电场。完全变掺杂的终端效率最高,占用芯片面积最小。然而终端注入铝离子在SiC材料中扩散能力远不如在硅材料中,因此碳化硅功率器件的结终端难以实现完全线性横向变掺杂。
为解决现有技术的不足之处,本发明提出一种高压碳化硅功率功率器件的结终端扩展结构,可实现结终端扩展(JTE)的横向变掺杂。其优化耗尽区的电场分布,占用较小的终端面积可达到近乎理想的结终端效率,并且降低结终端设计的难度,工艺的实现仅需要两张掩模版,不需增加额外工艺步骤。
发明内容
针对上述问题,本发明提出一种高压碳化硅功率器件的结终端扩展结构,该P型结终端扩展区中,直角靠近P型主结的第一P型终端扩展区的掺杂为高浓度,直角靠近N+场截止环的第二P型终端扩展区的掺杂为低浓度,从而实现等效横向变掺杂。具有等效渐变掺杂结终端扩展结构在制造工艺上没有额外增加工艺步骤,和传统的双区结终端扩展技术一致仅需要两张掩模版,降低了工艺复杂性;同时克服了分区结终端利用效率不高的缺点,更高效利用表面掺杂浓度,使得表面电场效率接近VLD器件并能减小终端占用面积。
为达到上述目的,本发明采用下述技术方案:
一种高压碳化硅功率器件的结终端扩展结构,包括第一金属电极层5、第一金属电极层5上方的N+型衬底4、N+型衬底4上方的N-型漂移区3;所述N-型漂移区3的左上方设有P型主结2;所述P型主结2的右侧邻接处设有P型结终端扩展区6,沿P型主结2和P型结终端扩展区6的邻接线方向将所述P型结终端扩展区6等分为多个矩形,每个矩形沿对角线分为2个直角三角形,分别为第一P型结终端扩展区61和第二P型结终端扩展区62,第一P型结终端扩展区61的一条直角边为P型主结2和P型结终端扩展区6的邻接线,第二P型结终端扩展区62的一条直角边为N-型漂移区3和P型结终端扩展区6的邻接线,所述P型结终端扩展区6右侧设有N+场截止环7,所述N+场截止环7与所述P型结终端扩展区6不相邻;所述P型主结2上方设有第二金属电极层1;所述P型结终端扩展区6上方设有钝化介质层8。
本发明还提供第二种高压碳化硅器件的结终端扩展结构,包括第一金属电极层5、第一金属电极层5上方的N+型衬底4、N+型衬底4上方的N-型漂移区3;所述N-型漂移区3的左上方设有P型主结2,所述P型主结2的右侧邻接处设有P型结终端扩展区6,沿P型主结2和P型结终端扩展区6的邻接线方向将所述P型结终端扩展区6等分为多个矩形,每个矩形沿对角线分为2个相同的直角梯形,分别为第一P型结终端扩展区61和第二P型结终端扩展区62,第一P型结终端扩展区61的较长底边为P型主结2和P型结终端扩展区6的邻接线,第二P型结终端扩展区62的较短底边为N-型漂移区3和P型结终端扩展区6的邻接线,所述P型结终端扩展区6右侧设有N+场截止环7,所述N+场截止环7与所述P型结终端扩展区6不相邻;所述P型主结2上方设有第二金属电极层1;所述P型结终端扩展区6上方设有钝化介质层8。
作为优选方式,所述N-型漂移区3的掺杂浓度范围为1×1014cm-3至5×1016cm-3,N-型漂移区3层的厚度为1μm至200μm。
作为优选方式,所述P型结终端扩展区6、P型主结2、N+场截止环7均为多次离子注入形成。
作为优选方式,所述P型主结2的掺杂浓度范围为1×1018cm-3至1×1019cm-3,注入深度为0.8μm至1μm。
作为优选方式,所述第一P型结终端扩展区61注入剂量范围为1×1013cm-2至2×1013cm-2,注入能量范围为50KeV至500KeV,所述第二P型结终端扩展区62注入剂量范围为1×1012cm-2至5×1012cm-2,注入能量范围为10KeV至400KeV。
作为优选方式,所述P型结终端扩展区6的注入深度为0.6μm至1μm。
作为优选方式,所述器件各区域掺杂类型与权利要求1相反。
作为优选方式,所述器件N-型漂移区3、N+型衬底4、P型主结2、P型结终端扩展区6、N+场截止环7的材料均为碳化硅。
本发明还提供上述高压的碳化硅器件的结终端扩展结构的制造方法,包括步骤:
第一步:清洗外延片;
第二步:注入氮离子形成N+场截止层;
第三步:注入铝离子形成P型主结;
第四步:进行第一P型结终端扩展区61注入;
第五步:进行第二P型结终端扩展区62注入;
第六步:淀积多晶硅,进行离子注入并退火;
第七步:淀积阳极、阴极金属;
第八步:淀积钝化氧化层介质层。
所述器件P型主结区为阳极,N+衬底端为阴极;
所述P型结终端扩展区适用于硅基和宽禁带半导体功率整流器、化合物半导体功率整流器、肖特基二极管、金属-氧化物半导体场效应晶体管、绝缘栅双极型晶体管或晶体管功率器件中任意一种。
本发明的有益效果为:本发明通过引入具有等效渐变掺杂结终端扩展结构来实现终端区的横向变掺杂浓度,从而既提高了器件反向工作时的终端效率,减小了终端占用面积,又降低了工艺复杂性。
附图说明
图1是传统的双区JTE终端保护的碳化硅二极管结构示意图;
图2(a)是是本发明实施例1的碳化硅器件的结终端扩展结构主视图;
图2(b)是图2(a)的俯视图。
图3是本发明实施例3的氮离子注入形成N+场截止层的示意图;
图4是本发明实施例3的在外延片上注入铝离子形成P型主结的示意图;
图5是本发明实施例3的铝离子注入形成三角JTE1的示意图;
图6是本发明实施例3的铝离子注入形成三角JTE2的示意图;
图7是本发明实施例3的淀积阳极和阴极金属的示意图;
图8是本发明实施例3的淀积钝化氧化层介质层的示意图;
图9(a)是本发明实施例2的碳化硅器件的结终端扩展结构示意图;
图9(b)是图9(a)的俯视图;
图9(c)是本发明实施例2的立体结构示意图;
1为第二金属电极层,2为P型主结,3为N-型漂移区,4为N+型衬底,5为第一金属电极层,6为P型结终端扩展区,61为第一P型结终端扩展区,62为第二P型结终端扩展区,7为N+场截止环,8为钝化介质层。
具体实施方式
以下通过特定的具体实例说明本发明的实施方式,本领域技术人员可由本说明书所揭露的内容轻易地了解本发明的其他优点与功效。本发明还可以通过另外不同的具体实施方式加以实施或应用,本说明书中的各项细节也可以基于不同观点与应用,在没有背离本发明的精神下进行各种修饰或改变。
实施例1
如图2(a)和图2(b)所示,一种高压碳化硅功率器件的结终端扩展结构,包括第一金属电极层5、第一金属电极层5上方的N+型衬底4、N+型衬底4上方的N-型漂移区3;所述N-型漂移区3的左上方设有P型主结2;所述P型主结2的右侧邻接处设有P型结终端扩展区6,沿P型主结2和P型结终端扩展区6的邻接线方向将所述P型结终端扩展区6等分为多个矩形,每个矩形沿对角线分为2个直角三角形,分别为第一P型结终端扩展区61和第二P型结终端扩展区62,第一P型结终端扩展区61的一条直角边为P型主结2和P型结终端扩展区6的邻接线,第二P型结终端扩展区62的一条直角边为N-型漂移区3和P型结终端扩展区6的邻接线,所述P型结终端扩展区6右侧设有N+场截止环7,所述N+场截止环7与所述P型结终端扩展区6不相邻;所述P型主结2上方设有第二金属电极层1;所述P型结终端扩展区6上方设有钝化介质层8。
所述N-型漂移区3的掺杂浓度范围为1×1014cm-3至5×1016cm-3,N-型漂移区3的厚度为1μm至200μm。
所述P型结终端扩展区6、P型主结2、N+场截止环7均为多次离子注入形成。
所述P型主结2的掺杂浓度范围为1×1018cm-3至1×1019cm-3,注入深度为0.8μm至1μm。
所述第一P型结终端扩展区61注入剂量范围为1×1013cm-2至2×1013cm-2,注入能量范围为50KeV至500KeV,所述第二P型结终端扩展区62注入剂量范围为1×1012cm-2至5×1012cm-2,注入能量范围为10KeV至400KeV。
所述P型结终端扩展区6的注入深度为0.6μm至1μm。
在其他实施例中,所述器件各区域掺杂类型与上述相反。
所述器件N-型漂移区3、N+型衬底4、P型主结2、P型结终端扩展区6、N+场截止环7的材料均为碳化硅。
本实施例通过引入等效渐变掺杂结终端扩展结构实现终端横向变掺杂,从而在提高器件反向工作时结终端效率的同时,又保证了器件的较小的终端面积,并且不增加工艺步骤,降低了器件的工艺复杂性。
所述P型结终端扩展区适用于硅基和宽禁带半导体功率整流器、化合物半导体功率整流器、肖特基二极管、金属-氧化物半导体场效应晶体管、绝缘栅双极型晶体管或晶体管功率器件中任意一种。
实施例2
本实施例由实施例1修改P型结终端扩展区的掩模版形状获得。
如图9(a)-图9(c)所示,一种高压碳化硅器件的结终端扩展结构,包括第一金属电极层5、第一金属电极层5上方的N+型衬底4、N+型衬底4上方的N-型漂移区3;所述N-型漂移区3的左上方设有P型主结2,所述P型主结2的右侧邻接处设有P型结终端扩展区6,沿P型主结2和P型结终端扩展区6的邻接线方向将所述P型结终端扩展区6等分为多个矩形,每个矩形沿对角线分为2个相同的直角梯形,分别为第一P型结终端扩展区61和第二P型结终端扩展区62,第一P型结终端扩展区61的较长底边为P型主结2和P型结终端扩展区6的邻接线,第二P型结终端扩展区62的较短底边为N-型漂移区3和P型结终端扩展区6的邻接线,所述P型结终端扩展区6右侧设有N+场截止环7,所述N+场截止环7与所述P型结终端扩展区6不相邻;所述P型主结2上方设有第二金属电极层1;所述P型结终端扩展区6上方设有钝化介质层8。
实施例3
如图3-图8所示,本实施例提供一种实施例1的高压碳化硅器件的结终端扩展结构的制备方法,包括以下步骤:
第一步:清洗外延片;
第二步:注入氮离子形成N+场截止层;
第三步:注入铝离子形成P型主结;
第四步:进行第一P型结终端扩展区61注入;
第五步:进行第二P型结终端扩展区62注入;
第六步:淀积多晶硅,进行离子注入并退火;
第七步:淀积阳极、阴极金属;
第八步:淀积钝化氧化层介质层。
所述器件P型主结区为阳极,N+衬底端为阴极;
上述实施例仅例示性说明本发明的原理及其功效,而非用于限制本发明。任何熟悉此技术的人士皆可在不违背本发明的精神及范畴下,对上述实施例进行修饰或改变。因此,凡所属技术领域中具有通常知识者在未脱离本发明所揭示的精神与技术思想下所完成的一切等效修饰或改变,仍应由本发明的权利要求所涵盖。

Claims (10)

1.一种高压碳化硅器件的结终端扩展结构,其特征在于:包括第一金属电极层(5)、第一金属电极层(5)上方的N+型衬底(4)、N+型衬底(4)上方的N-型漂移区(3);所述N-型漂移区(3)的左上方设有P型主结(2);所述P型主结(2)的右侧邻接处设有P型结终端扩展区(6),沿P型主结(2)和P型结终端扩展区(6)的邻接线方向将所述P型结终端扩展区(6)等分为多个矩形,每个矩形沿对角线分为2个直角三角形,分别为第一P型结终端扩展区(61)和第二P型结终端扩展区(62),第一P型结终端扩展区(61)的一条直角边为P型主结(2)和P型结终端扩展区(6)的邻接线,第二P型结终端扩展区(62)的一条直角边为N-型漂移区(3)和P型结终端扩展区(6)的邻接线,所述P型结终端扩展区(6)右侧设有N+场截止环(7),所述N+场截止环(7)与所述P型结终端扩展区(6)不相邻;所述P型主结(2)上方设有第二金属电极层(1);所述P型结终端扩展区(6)上方设有钝化介质层(8)。
2.一种高压碳化硅器件的结终端扩展结构,其特征在于:包括第一金属电极层(5)、第一金属电极层(5)上方的N+型衬底(4)、N+型衬底(4)上方的N-型漂移区(3);所述N-型漂移区(3)的左上方设有P型主结(2),所述P型主结(2)的右侧邻接处设有P型结终端扩展区(6),沿P型主结(2)和P型结终端扩展区(6)的邻接线方向将所述P型结终端扩展区(6)等分为多个矩形,每个矩形沿对角线分为2个相同的直角梯形,分别为第一P型结终端扩展区(61)和第二P型结终端扩展区(62),第一P型结终端扩展区(61)的较长底边为P型主结(2)和P型结终端扩展区(6)的邻接线,第二P型结终端扩展区(62)的较短底边为N-型漂移区(3)和P型结终端扩展区(6)的邻接线,所述P型结终端扩展区(6)右侧设有N+场截止环(7),所述N+场截止环(7)与所述P型结终端扩展区(6)不相邻;所述P型主结(2)上方设有第二金属电极层(1);所述P型结终端扩展区(6)上方设有钝化介质层(8)。
3.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述N-型漂移区(3)的掺杂浓度范围为1×1014cm-3至5×1016cm-3,N-型漂移区(3)的厚度为1μm至200μm。
4.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述P型结终端扩展区(6)、P型主结(2)、N+场截止环(7)均为多次离子注入形成。
5.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述P型主结(2)的掺杂浓度范围为1×1018cm-3至1×1019cm-3,注入深度为0.8μm至1μm。
6.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述第一P型结终端扩展区(61)注入剂量范围为1×1013cm-2至2×1013cm-2,注入能量范围为50KeV至500KeV,所述第二P型结终端扩展区(62)注入剂量范围为1×1012cm-2至5×1012cm-2,注入能量范围为10KeV至400KeV。
7.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述P型结终端扩展区(6)的注入深度为0.6μm至1μm。
8.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述器件各区域掺杂类型与权利要求1相反。
9.根据权利要求1或2所述高压的碳化硅器件的结终端扩展结构,其特征在于:所述器件N-型漂移区(3)、N+型衬底(4)、P型主结(2)、P型结终端扩展区(6)、N+场截止环(7)的材料均为碳化硅。
10.根据权利要求1至9任意一项所述高压的碳化硅器件的结终端扩展结构的制造方法,其特征在于,包括步骤:
第一步:清洗外延片;
第二步:注入氮离子形成N+场截止层;
第三步:注入铝离子形成P型主结;
第四步:进行第一P型结终端扩展区(61)注入;
第五步:进行第二P型结终端扩展区(62)注入;
第六步:淀积多晶硅,进行离子注入并退火;
第七步:淀积阳极、阴极金属;
第八步:淀积钝化氧化层介质层;
所述器件P型主结区为阳极,N+衬底端为阴极。
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CN107482050A (zh) * 2017-08-18 2017-12-15 珠海格力电器股份有限公司 一种功率器件的终端结构及其制造方法

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