CN113052748B - Graphics processor and video decoding display method - Google Patents

Graphics processor and video decoding display method Download PDF

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CN113052748B
CN113052748B CN202110228958.6A CN202110228958A CN113052748B CN 113052748 B CN113052748 B CN 113052748B CN 202110228958 A CN202110228958 A CN 202110228958A CN 113052748 B CN113052748 B CN 113052748B
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video
video data
data
display
decoding
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CN113052748A (en
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敬念
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Changsha Jingmei Integrated Circuit Design Co ltd
Changsha Jingjia Microelectronics Co ltd
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Changsha Jingmei Integrated Circuit Design Co ltd
Changsha Jingjia Microelectronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
    • H04N19/44—Decoders specially adapted therefor, e.g. video decoders which are asymmetric with respect to the encoder
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Multimedia (AREA)
  • Signal Processing (AREA)
  • Controls And Circuits For Display Device (AREA)

Abstract

The embodiment of the application provides a graphic processor and a decoding display method, wherein the graphic processor comprises a hardware decoding module, a double-rate synchronous dynamic random access memory, an output module and a 2D hardware module; the double-rate synchronous dynamic random access memory is used for storing the acquired video data; the hardware decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory; and the 2D hardware module is used for copying the decoded video data from the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for display through the output module. The video decoding, the data copying and the output display are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and the data copying transmission time are also reduced, and the efficiency of video decoding and displaying is improved.

Description

Graphics processor and video decoding display method
Technical Field
The present application relates to the field of computer graphics processing technology, and in particular, to a graphics processor and a video decoding display method.
Background
The video card supports video decoding and display in addition to image processing and display. Video decoding display is usually implemented by software or hardware, and often, after video decoding, color conversion or scaling is performed by software or other modules, and after the decoded video is processed, a central processing unit is required to copy data to a display device for display. However, performing video decoding display in this way not only increases the CPU usage but also the video display efficiency is not high.
Disclosure of Invention
The embodiment of the application provides a graphics processor and a video decoding display method, which can effectively solve the problems of high CPU utilization rate and low video display efficiency.
According to a first aspect of embodiments of the present application, there is provided a graphics processor including a hardware decoding module, a double rate synchronous dynamic random access memory, an output module, and a 2D hardware module; the double-rate synchronous dynamic random access memory is used for storing the acquired video data; the hardware decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory; and the 2D hardware module is used for copying the decoded video data from the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for display through the output module.
According to a second aspect of embodiments of the present application, there is provided a video decoding display method, including: acquiring video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video window to display equipment for display.
According to a third aspect of embodiments of the present application, there is provided a video decoding display apparatus, the apparatus comprising: the acquisition module is used for acquiring video data; the decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory; and the display module is used for copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window and outputting the video window to display equipment for display.
According to a fourth aspect of embodiments of the present application, there is provided an electronic device comprising one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform a method as described above as applied to an electronic device.
According to a fifth aspect of embodiments of the present application, embodiments of the present application provide a computer readable storage medium having program code stored therein, wherein the above-described method is performed when the program code is run.
By adopting the graphic processor and the video decoding display method provided by the embodiment of the application, the graphic processor decodes the acquired video data and stores the decoded video data in the double-rate synchronous dynamic random access memory; copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window and outputting the video window to display equipment for display. The video decoding, copying the decoded video data to the video window and outputting and displaying are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying and transmitting time is also reduced, and the efficiency of video decoding and displaying is improved.
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The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and together with the description serve to explain the application and do not constitute an undue limitation to the application. In the drawings:
FIG. 1 is a block diagram of a graphics processor provided in an embodiment of the present application;
FIG. 2 is a schematic diagram illustrating connection between a graphics processor and a CPU and a system memory according to one embodiment of the present disclosure;
FIG. 3 is a flowchart of a video decoding display method according to an embodiment of the present application;
FIG. 4 is a schematic diagram of an interface for displaying video data according to one embodiment of the present application;
FIG. 5 is a functional block diagram of a video decoding display device according to an embodiment of the present application;
fig. 6 is a block diagram of an electronic device for performing a video decoding display method according to an embodiment of the present application.
Detailed Description
Video decoding display is a common graphics processing technique. Traditional video decoding is implemented by software or hardware, firstly, video is decoded to obtain decoded video data, and after decoding, color conversion or scaling is required by software or other modules. After processing is completed, a central processing unit (Central Processing Unit, CPU) is also required to copy the data to a display device for display.
The inventors have found in research that, during display, typically, the CPU copies data to the display device for display, i.e., after decoding the video and processing, data interaction with the CPU is required for display. In this way, since the CPU needs to copy data, the CPU utilization rate is increased, and it takes a certain time to perform data transmission when the CPU copies data, resulting in low video decoding display efficiency.
In view of the above problems, an embodiment of the present application provides a graphics processor and a video decoding display method, where the graphics processor decodes acquired video data, and stores the decoded video data in a double-rate synchronous dynamic random access memory; copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window for display. The video decoding, copying the decoded video data to the video window and outputting and displaying are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying and transmitting time is also reduced, and the efficiency of video decoding and displaying is improved.
The solutions in the embodiments of the present application may be implemented in various computer languages, for example, object-oriented programming language Java and an transliterated scripting language JavaScript.
In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of exemplary embodiments of the present application is given with reference to the accompanying drawings, and it is apparent that the described embodiments are only some of the embodiments of the present application and not exhaustive of all the embodiments. It should be noted that, in the case of no conflict, the embodiments and features in the embodiments may be combined with each other.
Referring to FIG. 1, a diagram of a graphics processor architecture is shown, as provided in one embodiment of the present application. Graphics processor (Graphics Processing Unit, GPU) 10 includes 2D hardware module 11, double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) 12, hardware decoding module 13, and output module 14. The double rate synchronous dynamic random access memory 12 is used for storing video data acquired by the GPU 10; the hardware decoding module 13 is configured to decode the video data according to the size of a video window, and store the decoded video data in the DDR SDRAM 12; the 2D hardware module is configured to copy the decoded video data from the DDR SDRAM12 to the video window, and output the video data to a display device for display through the output module 14.
The 2D hardware module 11, the DDR SDRAM12, the hardware decoding module 13, and the output module 14 are connected through an AXI bus. AXI is a bus protocol, which is an on-chip bus with high performance, high bandwidth, and low latency. The 2D hardware module 11 in the GPU10, the DDR SDRAM12, the hardware decoding module 13, and the output module 14 are connected through an AXI bus so as to be able to communicate with each other.
Referring to fig. 2, a schematic diagram of connection between a GPU and a central processing unit (Central Processing Unit, CPU) and a system memory according to an embodiment of the present application is shown.
The 2D hardware module 11 in the GPU10, the DDR SDRAM12, the hardware decoding module 13, the output module 14 is connected through an AXI bus, and the AXI bus is connected with the CPU10 and the system memory 30 through a PCIe bus. Therefore, the GPU10 may perform data transmission with the CPU 20 and the system memory 30, so that the GPU10 may obtain video data from the system memory 30 through the CPU 20, and thus the GPU10 may decode and display the obtained video data. After the GPU10 acquires the video data, the video data may be stored in the DDR SDRAM12, and the hardware decoding module 13 may acquire the video data from the DDR SDRAM12 through an AXI bus and decode the video data.
When the hardware decoding module 13 decodes the video data, parameters of a video window for displaying the video data may be obtained, and the video data may be decoded according to the parameters of the video window, so that the decoded video data matches with the video window. The parameters of the video window may be a display position of the video window, a size of the video window, a rotation angle of the video window, or an output format of the video window.
The hardware decoding module 13 may decode the video data according to the parameters of the video window to obtain YVU data, convert the YVU data into RGB data, and write the RGB data into the DDR SDRAM 12. The YUV data and the RGB data are both data formats of images, video frames. Y in YUV corresponds to the "luminance" component of the gray scale, UV is two "chrominance" components, where U is the blue projection and V is the red projection. The hardware decoding module 13 may obtain YUV components of each pixel in the video frame, decode the video data into YUV data, convert the YUV data into RGB data, and store the RGB data in the DDR SDRAM12 for subsequent use.
It can be understood that if the video data is displayed, the YUV data is required to be displayed, and the YUV data is not required to be converted into RGB data, and the embodiment of the present application will be described below with reference to the RGB data display.
After the video decoding is completed, a series of processes, such as size conversion, rotation, etc., are generally required to be performed on the decoded data to adapt to the video window, and since the decoding is performed according to the parameters of the video window in the embodiment of the present application, the obtained decoded video data is directly adapted to the video window. After decoding, if the decoded video data is to be displayed, the decoded video data needs to be copied to a display frame memory.
Since the decoded video data is stored in the DDR SDRAM12, the 2D hardware module 11 may read the decoded video data from the DDR SDRAM12, and copy the decoded data to a display frame memory for display. That is, the 2D hardware module 11 reads the RGB data from the DDR SDRAM12, copies the RGB data into a display frame memory, and realizes display of the video data. Because the video data needs to be displayed in a video window, an area corresponding to the video window in a display frame memory can be obtained, the decoded video data, namely the RGB data, is copied to the area corresponding to the video window in the display frame memory, and the video data is displayed in the video window on a display device through the output module 14.
When the video data is displayed on the display device through the video window, the video data can be output to the display device through the output module 14 for display, and the output module 14 can be a high-definition multimedia interface (High Definition Multimedia Interface, HDMI) and is connected with a display screen through the HDMI, so that the video data is displayed through the video window. The output module 14 may also be a video graphics array (Video Graphics Array, VGA) connected to a display screen via a VGA interface so that the output module 14 can display the video data on the display device in the video window. The display device may be a display screen of an electronic device mounted by the GPU, or may be a display device connected to the HDMI or VGA interface, such as a display, a television, or the like.
The image processor provided by the embodiment of the application comprises a hardware decoding module, a double-rate synchronous dynamic random access memory, an output module and a 2D hardware module; the double-rate synchronous dynamic random access memory stores the acquired video data; the hardware decoding module decodes the video data according to the parameters of the video window, and stores the decoded video data in the double-rate synchronous dynamic random access memory; and the 2D hardware module copies the decoded video data to the video window from the double-rate synchronous dynamic random access memory, and outputs the video data to display equipment for display through the output module. The 2D hardware module is used for replacing a CPU to execute data copying, so that the utilization rate of the CPU can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding display efficiency is improved.
Referring to fig. 3, an embodiment of the present application provides a video decoding display method, which may be applied to the graphics processor provided in the foregoing embodiment, where the graphics processor may be installed in an electronic device, and the electronic device may be a computer or a server, and the specific method may include the following steps.
In step 110, video data is acquired.
The graphics processor (Graphics Processing Unit, GPU) is connected to the central processor (Central Processing Unit, CPU) and system memory via a PCIe bus. Thus, the GPU may retrieve the video data from the system memory via the CPU. After the GPU acquires the video data, the video data can be processed by the GPU, so that the video data can be displayed.
And step 120, decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory.
After the GPU acquires the video data, parameters of a video window for displaying the video data can be acquired, and the video data is decoded according to the parameters of the video window, so that the video data is matched with the video window when being displayed. The parameters of the video window can be the display position of the video window, the size of the video window, the output format of the video window and the like.
After the GPU acquires the parameters of the video window, the video data can be decoded according to the parameters of the video window to obtain decoded video data, and the GPU can store the decoded video data. The GPU has a double rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM) internally, so the GPU can store decoded data in the internal DDR SDRAM for further processing.
Specifically, when the GPU decodes the video data, the GPU may decode the video data into YUV data according to the parameters of the video window, and after obtaining the YUV data, convert the YUV data into RGB data for display.
And 130, copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video window to a display device for display.
And decoding the obtained video data by the GPU to obtain decoded video data, namely RGB data, and storing the decoded video data in the DDR SDRAM. Typically, if the video data is to be displayed, the video data needs to be copied to a display frame memory, and the video data is displayed on a display screen waiting for a screen refresh. Thus, the GPU may copy the decoded video data stored in the DDR SDRAMSDRAM memory into a display frame memory to wait for display while screen refresh is occurring. Because the video data is displayed in the video window, the GPU can copy the decoded video data to a corresponding area of the video window in a display frame memory, and wait for screen refreshing to display the video data.
It will be appreciated that the GPU may be installed in an electronic device and that the video data may be displayed in a variety of ways.
In some embodiments, the GPU may directly display the video data on a display screen of the electronic device when the electronic device is provided with a display function.
In some embodiments, the GPU may also be provided with multiple graphics output interfaces, such as a high definition multimedia interface (High Definition Multimedia Interface, HDMI), and video graphics array (Video Graphics Array, VGA), among others. The video data can be output to the display device for display by connecting with the display device through HDMI and VGA interfaces.
Referring to fig. 4, an interface diagram showing video data is shown. In the display interface shown in fig. 4, various elements 41 may be displayed, while in the area of the dashed box indicated by 42, the video data may be displayed, i.e. the dashed box is the video window within which the video data is displayed.
This process is described below in one specific example. Assuming that the GPU is mounted on a computer graphics card, a user can use a player to play video on the computer, and when a multimedia video file is played, the GPU can acquire the video data from a system memory through a CPU. After the video data is obtained, decoding the video data into YUV data according to parameters of a video window, converting the YUV data into RGB data, storing the RGB data in a DDR SDRAM in a GPU, copying the RGB data stored in the DDR SDRAM to a region corresponding to the video window in a display frame memory by the GPU, and outputting the RGB data to a screen for display, thereby realizing the display of the video data in the video window. The user can then view the video on the computer.
The decoding display method provided by the embodiment of the application acquires video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video window to display equipment for display. The GPU is utilized to execute video decoding, the video data after decoding is copied to a video window and output and display are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the efficiency of video decoding and displaying is improved.
Referring to fig. 5, an embodiment of the present application provides a video decoding display apparatus 200, which is applicable to an electronic device, where the video decoding display apparatus 200 includes an obtaining module 210, a decoding module 220, and a display module 230. The acquiring module 210 is configured to acquire video data; the decoding module 220 is configured to decode the video data according to parameters of a video window, and store the decoded video data in a double rate synchronous dynamic random access memory; the display module 230 is configured to copy the decoded video data in the double rate synchronous dynamic random access memory to the video window, and output the video window to a display device for display.
Further, the decoding module 220 is further configured to decode the video data into YUV data according to parameters of a video window; converting the YUV data into RGB data.
Further, the display module 230 is further configured to obtain RGB data in the double rate synchronous dynamic random access memory; and copying the RGB data to a region corresponding to the video window in a display frame memory and outputting the RGB data to display equipment for display.
The video decoding display device provided by the embodiment of the application acquires video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video window to display equipment for display. The GPU is utilized to execute video decoding, the video data after decoding is copied to a video window and output and display are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the efficiency of video decoding and displaying is improved.
It should be noted that, for convenience and brevity of description, specific working processes of the apparatus described above may refer to corresponding processes in the foregoing method embodiments, which are not repeated herein.
Referring to fig. 6, an embodiment of the present application provides a block diagram of an electronic device, where the electronic device 300 includes a processor 310, a memory 320, and one or more application programs, where the one or more application programs are stored in the memory 320 and configured to be executed by the one or more processors 310, and the one or more program is configured to perform the method of video decoding display described above.
The electronic device 300 may be a terminal device such as a notebook computer or a computer capable of running an application program, or may be a server. The electronic device 300 in this application may include one or more of the following components: a processor 310, a memory 320, and one or more application programs, wherein the one or more application programs may be stored in the memory 320 and configured to be executed by the one or more processors 310, the one or more program(s) configured to perform the method as described in the foregoing method embodiments.
Processor 310 may include one or more processing cores. The processor 310 utilizes various interfaces and lines to connect various portions of the overall electronic device 300, perform various functions of the electronic device 300, and process data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 320, and invoking data stored in the memory 320. Alternatively, the processor 310 may be implemented in hardware in at least one of digital signal processing (Digital Signal Processing, DSP), field programmable gate array (Field-Programmable Gate Array, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 310 may integrate one or a combination of several of a central processing unit (Central Processing Unit, CPU), an image processor (Graphics Processing Unit, GPU), and a modem, etc. The CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for being responsible for rendering and drawing of display content; the modem is used to handle wireless communications. It will be appreciated that the modem may not be integrated into the processor 310 and may be implemented solely by a single communication chip.
The Memory 320 may include a random access Memory (Random Access Memory, RAM) or a Read-Only Memory (Read-Only Memory). Memory 320 may be used to store instructions, programs, code sets, or instruction sets. The memory 320 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing the various method embodiments described below, etc. The storage data area may also store data created by the electronic device 300 in use (e.g., phonebook, audiovisual data, chat log data), and the like.
The electronic equipment provided by the embodiment of the application acquires video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video window to display equipment for display. The GPU is utilized to execute video decoding, the video data after decoding is copied to a video window and output and display are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the efficiency of video decoding and displaying is improved.
It will be appreciated by those skilled in the art that embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiments and all such alterations and modifications as fall within the scope of the application.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.

Claims (11)

1. A graphics processor, wherein the graphics processor comprises a hardware decoding module, a double rate synchronous dynamic random access memory, an output module and a 2D hardware module;
the double-rate synchronous dynamic random access memory is used for storing the acquired video data;
the hardware decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory;
and the 2D hardware module is used for copying the decoded video data from the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for display through the output module.
2. The graphics processor of claim 1, wherein the hardware decode module, double rate synchronous dynamic random access memory, output module, and 2D hardware module are coupled via an AXI bus coupled to the central processor and system memory via a PCIe bus.
3. The graphics processor of claim 2, wherein the graphics processor obtains the video data from the system memory via the central processing unit and stores the video data in the double rate synchronous dynamic random access memory.
4. The graphics processor of claim 1, wherein the hardware decoding module decodes the video data into YUV data and converts the YUV data into RGB data.
5. The graphics processor of claim 1, wherein the output module comprises a high definition multimedia interface or a video graphics array.
6. A video decoding display method applied to the graphics processor of any one of claims 1-5, the method comprising:
acquiring video data;
decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory;
copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video window to display equipment for display.
7. The method of claim 6, wherein decoding the video data according to parameters of a video window comprises:
decoding the video data into YUV data according to parameters of a video window;
converting the YUV data into RGB data.
8. The method of claim 7, wherein copying the decoded video data in the double rate synchronous dynamic random access memory to the video window and outputting to a display device for display comprises:
acquiring RGB data in the double-rate synchronous dynamic random access memory;
and copying the RGB data to a region corresponding to the video window in a display frame memory and outputting the RGB data to display equipment for display.
9. A video decoding display device, the device comprising:
the acquisition module is used for acquiring video data;
the decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory;
and the display module is used for copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window and outputting the video window to display equipment for display.
10. An electronic device, the electronic device comprising:
one or more processors;
a memory electrically connected to the one or more processors;
one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform the method of any of claims 6 to 8.
11. A computer readable storage medium having stored therein program code which is callable by a processor to perform the method according to any one of claims 6 to 8.
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CN116193201A (en) * 2023-02-27 2023-05-30 深圳数拓科技有限公司 Video data processing method

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873585A (en) * 1984-09-07 1989-10-10 Ivex Corporation Method of selectively retrieving video images from a video reproducer for simulating movement
US6975324B1 (en) * 1999-11-09 2005-12-13 Broadcom Corporation Video and graphics system with a video transport processor
EP1995959A2 (en) * 2007-05-25 2008-11-26 Samsung Electronics Co., Ltd. Video apparatus having integrated terminal and control method thereof
CN102279821A (en) * 2011-08-02 2011-12-14 记忆科技(深圳)有限公司 Method and system for transmitting DDR (double data rate) controller port command
CN102474604A (en) * 2009-06-30 2012-05-23 高通股份有限公司 Texture compression in a video decoder for efficient 2d-3d rendering
CN109065094A (en) * 2018-08-09 2018-12-21 晶晨半导体（深圳）有限公司 Obtain the method and system of Double Data Rate synchronous DRAM volume production frequency
CN110347459A (en) * 2019-06-11 2019-10-18 广州视源电子科技股份有限公司 A kind of window minimizes method, apparatus, storage medium and interactive intelligent tablet computer
CN111866408A (en) * 2020-07-30 2020-10-30 长沙景嘉微电子股份有限公司 Graphic processing chip and video decoding display method
WO2021008290A1 (en) * 2019-07-15 2021-01-21 腾讯科技（深圳）有限公司 Video stream decoding method and apparatus, terminal device and storage medium

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7446774B1 (en) * 1998-11-09 2008-11-04 Broadcom Corporation Video and graphics system with an integrated system bridge controller
US20130148947A1 (en) * 2011-12-13 2013-06-13 Ati Technologies Ulc Video player with multiple grpahics processors
CN108366288A (en) * 2018-03-01 2018-08-03 厦门普杰信息科技有限公司 A kind of efficient decoding and playback method and system for HD video

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4873585A (en) * 1984-09-07 1989-10-10 Ivex Corporation Method of selectively retrieving video images from a video reproducer for simulating movement
US6975324B1 (en) * 1999-11-09 2005-12-13 Broadcom Corporation Video and graphics system with a video transport processor
EP1995959A2 (en) * 2007-05-25 2008-11-26 Samsung Electronics Co., Ltd. Video apparatus having integrated terminal and control method thereof
CN102474604A (en) * 2009-06-30 2012-05-23 高通股份有限公司 Texture compression in a video decoder for efficient 2d-3d rendering
CN102279821A (en) * 2011-08-02 2011-12-14 记忆科技(深圳)有限公司 Method and system for transmitting DDR (double data rate) controller port command
CN109065094A (en) * 2018-08-09 2018-12-21 晶晨半导体（深圳）有限公司 Obtain the method and system of Double Data Rate synchronous DRAM volume production frequency
CN110347459A (en) * 2019-06-11 2019-10-18 广州视源电子科技股份有限公司 A kind of window minimizes method, apparatus, storage medium and interactive intelligent tablet computer
WO2021008290A1 (en) * 2019-07-15 2021-01-21 腾讯科技（深圳）有限公司 Video stream decoding method and apparatus, terminal device and storage medium
CN111866408A (en) * 2020-07-30 2020-10-30 长沙景嘉微电子股份有限公司 Graphic processing chip and video decoding display method

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