CN109688462B

CN109688462B - Method and device for reducing power consumption of equipment, electronic equipment and storage medium

Info

Publication number: CN109688462B
Application number: CN201811428037.9A
Authority: CN
Inventors: 胡小朋
Original assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Current assignee: Guangdong Oppo Mobile Telecommunications Corp Ltd
Priority date: 2018-11-27
Filing date: 2018-11-27
Publication date: 2021-06-15
Anticipated expiration: 2038-11-27
Also published as: CN109688462A

Abstract

The application discloses a method and a device for reducing equipment power consumption, electronic equipment and a storage medium, wherein the method for reducing the equipment power consumption comprises the following steps: when video playing is carried out, whether a mode of display enhancement processing is started or not is judged, and the display enhancement processing improves the image quality of the played video by processing images in the played video through optimizing parameters; if the video playing mode is started, detecting a decoding mode for decoding the playing video at present; and performing power consumption reduction processing for reducing the working frequency of the processor according to the power consumption reduction processing method corresponding to the decoding mode. The method can reduce the power consumption of the electronic equipment.

Description

Method and device for reducing power consumption of equipment, electronic equipment and storage medium

Technical Field

The present application relates to the field of electronic device technologies, and in particular, to a method and an apparatus for reducing power consumption of a device, an electronic device, and a storage medium.

Background

Electronic devices, such as computers and mobile phones, have become one of the most common consumer electronic products in daily life. With the development of electronic devices, more and more users play videos by using the electronic devices, but when playing videos by using the electronic devices, larger power consumption is brought.

Disclosure of Invention

In view of the foregoing problems, the present application provides a method, an apparatus, an electronic device, and a computer-readable storage medium for reducing power consumption of a device, so as to reduce power consumption of the device.

In a first aspect, an embodiment of the present application provides a method for reducing power consumption of a device, where the method includes: when video playing is carried out, whether a mode of display enhancement processing is started or not is judged, and the display enhancement processing improves the image quality of the played video by processing images in the played video through optimizing parameters; if the video playing mode is started, detecting a decoding mode for decoding the playing video at present; and performing power consumption reduction processing for reducing the working frequency of the processor according to the power consumption reduction processing method corresponding to the decoding mode.

In a second aspect, an embodiment of the present application provides an apparatus for reducing power consumption of a device, where the apparatus includes: the device comprises an enhancement detection module, a decoding detection module and a power consumption processing module, wherein the enhancement detection module is used for judging whether a mode of display enhancement processing is started or not when video playing is carried out, and the display enhancement processing is used for processing images in the played video through optimized parameters to improve the image quality of the played video; the decoding detection module is used for detecting the current decoding mode for decoding the played video if the decoding detection module is started; and the power consumption processing module is used for reducing the power consumption of the processor according to the power consumption reduction processing method corresponding to the decoding mode.

In a third aspect, an embodiment of the present application provides an electronic device, including: one or more processors; a memory; one or more application programs, wherein the one or more application programs are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of reducing power consumption of a device as provided in the first aspect above.

In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, where a program code is stored in the computer-readable storage medium, and the program code may be called by a processor to execute the method for reducing power consumption of a device according to the first aspect.

According to the scheme, whether the mode of the display enhancement processing is started or not is judged when the video is played, when the mode of the display enhancement processing is started, the decoding mode of decoding the played video at present is detected, and the power consumption reduction processing for reducing the working frequency of the processor is carried out according to the power consumption reduction processing method corresponding to the decoding mode, so that the power consumption reduction processing is carried out according to the decoding mode when the mode of the display enhancement processing is started, and the effect of reducing the power consumption of the electronic equipment when the video is played is achieved.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.

Fig. 1 shows a block diagram of a video playing architecture provided according to an embodiment of the present application.

FIG. 2 shows a flow diagram of a method of reducing power consumption of a device according to one embodiment of the present application.

FIG. 3 shows a flow diagram of a method of reducing power consumption of a device according to another embodiment of the present application.

Fig. 4 shows a flowchart of step S230 in the method for reducing power consumption of a device according to the embodiment of the present application.

Fig. 5 shows a flowchart of step S240 in the method for reducing power consumption of a device according to the embodiment of the present application.

FIG. 6 shows a flow diagram of a method of reducing power consumption of a device according to yet another embodiment of the present application.

Fig. 7 shows a flowchart of step S330 in the method for reducing power consumption of a device according to the embodiment of the present application.

FIG. 8 shows a block diagram of an apparatus for reducing power consumption of a device according to an embodiment of the present application.

Fig. 9 shows a block diagram of a power consumption processing module in an apparatus for reducing power consumption of a device according to an embodiment of the present application.

FIG. 10 shows another block diagram of a power consumption processing module in an apparatus for reducing power consumption of a device according to an embodiment of the application.

Fig. 11 is a block diagram of an electronic device for executing a method for reducing power consumption of the device according to an embodiment of the present application.

Fig. 12 is a memory unit for storing or carrying program code implementing a method for reducing power consumption of a device according to an embodiment of the present application.

Detailed Description

In order to make the technical solutions better understood by those skilled in the art, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application.

Currently, most electronic devices, such as computers, mobile phones, tablet computers, and the like, can play videos. When the electronic device plays the video, the operating system of the electronic device can analyze the audio and video data after acquiring the video data to be played. Generally, a video file is composed of two parts, namely a video stream and an audio stream, and the packaging formats of audio and video in different video formats are different. The process of synthesizing files of audio streams and video streams is called muxer (merge file). The inverse process of muxer corresponds to the process of separating audio and video streams from a media file is called demux (separation file). When playing a video file, an audio stream and a video stream need to be separated from a file stream and decoded respectively, a decoded video frame can be directly rendered, an audio frame can be sent to a buffer area of audio output equipment for playing, and certainly, timestamps of video rendering and audio playing need to be controlled to be synchronous.

The video decoding may include hard decoding and soft decoding, the hardware decoding is performed by submitting a part of video data, which is originally completely processed by a Central Processing Unit (CPU), to an image processor (GPU), and the parallel computing capability of the GPU is much higher than that of the CPU, so that the load on the CPU can be greatly reduced, and some other programs can be simultaneously run after the CPU has a low occupancy rate. Of course, for better performing processors, software decoding may also be used, i.e. decoding by a decoding software program in the CPU.

Referring to fig. 1, a block diagram of a video playback architecture of an electronic device is shown. When the player adopts a hard decoding player, a Media Framework (multimedia Framework) acquires a Video file to be played by a client through an API interface of the client of the player, and decodes the Video file by a Video decoder to obtain decoded Video data, that is, image data to be rendered. The Media frame is a multimedia Framework in an Android system, and may include three parts, namely, a MediaPlayer, a MediaPlayerService, and a stagefrigplaylayer. Specifically, the multimedia framework part adopts a C/S structure, the MediaPlayer is used as a Client (Client) end of the C/S structure, the MediaPlayer service and the stagefrigliplayyer are used as a C/S structure Server (service) end, the responsibility of playing the multimedia file is born, and the Server end completes the request of the Client end and responds through the stagefrigliplayer. The Video decoder is a decoder that can Decode audio data as well as Video data, and decodes the Video data. After the Video Decode decodes the Video file, the decoded Video data may be transmitted to a surface flag (layer delivery module) through a Video driver for rendering and displaying on a screen. The Surface flunger is an independent Service, which receives Surface layers of all windows as input, calculates the position of each Surface in a final composite image according to parameters such as ZOrder, transparency, size, position and the like, and then sends the position to HWComposer or OpenGL (Open Graphics Library) to generate a final display Buffer, and then displays the final display Buffer on a specific display device.

When the player adopts soft decoding, the CPU decodes the video through software, and the GPU is called to render and combine the video after decoding, and then the video is displayed on a screen. And hard decoding means that the video decoding task is independently completed through a special daughter card device without the aid of a CPU.

In the embodiment of the application, the electronic device can perform display enhancement processing of video playing in the video playing process. Specifically, after the decoded Video data is obtained through hard decoding or soft decoding, the decoded Video data is used as image data to be rendered, and when the image data to be rendered is sent to the surface flag, the image data to be rendered may be intercepted and optimized by an HQV (Hollywood Quality Video) algorithm module, and then sent to the surface flag for rendering and subsequent display operations on a screen. The HQV algorithm module is used for storing the image data to be rendered into the off-screen rendering buffer area, and then performing display enhancement processing on the image of the multi-frame image data in the off-screen rendering buffer area through optimization parameters such as exposure enhancement, denoising, edge sharpening, contrast increase and saturation increase, and then transmitting the image to the surface flicker for rendering and subsequent optimization operation on the screen. The display enhancement processing can improve the image quality of the played video, wherein the image quality comprises definition, sharpness, lens distortion, color, resolution, color gamut range, purity and the like, and different display enhancement effects can be achieved through different combination modes. Achieving different combinations in the image quality may be achieved by controlling the optimization parameter. It should be noted that the display enhancement processing on the played video may also be understood as a series of operations performed before formal processing on the played video, including image enhancement, image restoration, and the like, where the image enhancement is to add some information or transform data to an original image by a certain means, selectively highlight interesting features in the image or suppress some unnecessary features in the image, so that the image is matched with the optimization parameters, thereby improving the image quality and enhancing the visual effect, so that the displayed video image achieves the effect of super-visibility. Specifically, the surface flunger may call the GPU to render and synthesize the image data, and then put the rendered result into a frame buffer, and then the video controller reads the data in the frame buffer, and transmits the data to the display through digital-to-analog conversion, thereby enhancing the display of the video display.

However, the inventors have found through research that, when performing display enhancement in the video playing process, power consumption is increased compared with the case of performing display after directly rendering a video file after decoding the video file. Therefore, in view of the technical problem, the inventor has studied and proposed a method, an apparatus, an electronic device, and a computer-readable storage medium for reducing device power consumption according to embodiments of the present application for a long time, and performs power consumption reduction processing for reducing the operating frequency of a processor according to a power consumption reduction processing method corresponding to a current decoding mode of a played video when a mode of display enhancement processing is turned on when the video is played, so as to achieve an effect of reducing power consumption of the electronic device.

The method for reducing the power consumption of the device according to the embodiment of the present application is described in detail below.

Referring to fig. 2, an embodiment of the present application provides a method for reducing power consumption of a device, which is applicable to an electronic device, and the method for reducing power consumption of the device may include:

step S110: when video playing is carried out, whether a mode of display enhancement processing is started or not is judged, and the display enhancement processing improves the image quality of the played video by processing images in the played video through optimizing parameters.

In the process of playing video by electronic equipment, display enhancement processing is performed on the played video in order to ensure the playing effect of the video. The display enhancement processing improves the image quality of the played video by optimizing the image in the parameter processing, and the specific display enhancement processing can refer to the description of the display enhancement processing.

In the embodiment of the application, the current video playing state of the electronic device can be detected, so that when the electronic device plays a video, whether a mode for performing display enhancement processing on the played video is started or not is determined. As one manner, detecting whether the electronic device performs video playing may be detecting whether a video playing framework of the electronic device works to determine whether the electronic device is currently in a state of performing video playing, that is, when the video playing framework works, determining that the electronic device is in the state of performing video playing. In addition, whether a related module used during video playing is working may also be detected to determine whether the electronic device is in a state of performing video playing, for example, when detecting that a video decoder, a layer transfer module, a video player, and the like are in a working state, it is detected that the electronic device is currently in a state of performing video playing. Of course, the specific manner of detecting whether the video is currently in the video playing state is not limited in the embodiment of the present application.

Further, when it is determined that the electronic device plays the video, it may be determined whether the mode for performing the display enhancement processing on the played video is turned on, so that when the mode for performing the display enhancement processing is turned on, the power consumption reduction processing is performed to reduce the power consumption of the electronic device. As one mode, a display-enhanced switch button for video playing may be provided in the system interface of the electronic device, and a user may turn on or off the display-enhanced function of video playing through the switch button. By detecting whether a switch button for performing display enhancement processing on the played video is turned on, when the switch button is turned on, a mode for performing display enhancement processing on the played video is turned on; when the switch button is turned off, the mode for performing display enhancement processing on the played video is turned off. As another mode, when the display enhancement processing is performed on the played video, the HQV algorithm module is called to perform an optimization operation on the decoded video image data, so as to achieve the display enhancement of the played video. Therefore, by detecting whether the HQV algorithm module is called or not, if the HQV algorithm module is called, the mode for performing display enhancement processing on the played video is started; if the HQV algorithm module is not called, it indicates that the mode for display enhancement processing of the playing video is off. Of course, the specific manner of detecting whether the mode of the display enhancement processing is turned on is not limited in the embodiment of the present application.

Step S120: and if the video decoding device is started, detecting a decoding mode for decoding the played video at present.

In the embodiment of the present application, when the mode for performing display enhancement processing on the played video is turned on, it means that display enhancement processing is performed on the played video when the video is played. When the display enhancement processing is performed on the played video, larger power consumption can be generated, so that the power consumption reduction processing can be performed to reduce the power consumption of the electronic equipment.

Further, when the mode of the display enhancement processing is judged to be started, the current decoding mode for decoding the played video is detected, so that the corresponding power consumption reduction processing is performed according to the decoding mode for the played video. It can be understood that, in general, when the electronic device decodes the video file, a hard decoding manner or a soft decoding manner is adopted to decode the video file. When the playing video is decoded by using the hard decoding mode, the occupied resources of the processor are different from those when the playing video is decoded by using the soft decoding mode. The soft decoding method is to decode by software, and when the soft decoding is actually performed, the soft decoding method also depends on hardware, namely a central processing unit. In the soft decoding process, a large amount of video information needs to be calculated, so that the requirement on the performance of the central processing unit is very high. The hard decoding mode refers to decoding realized through hardware, and the hard decoding mode realizes decoding through hardware, so that resources of a central processing unit are not occupied. The hard decoding mode may be understood as a decoding operation performed by a special hardware module (i.e., a circuit board), and as one mode, the hard decoding may be performed by a Video Processing Unit (VPU), of course, the hard decoding may also be performed by an image processor, and a hardware module specifically used for the hard decoding may not be limited in this embodiment of the application.

As an embodiment, when detecting a decoding mode for decoding a currently played video, it may be detected whether a video decoder module for soft decoding is called, where when the video decoder module for soft decoding is called, it indicates that the mode for decoding the currently played video is a soft decoding mode, and when the video decoder module for soft decoding is not called, it indicates that the mode for decoding the currently played video is a hard decoding mode. As another embodiment, when detecting a decoding method for decoding a currently played video, the method may detect a use condition of a hardware module for performing hard decoding, and when the use condition of the hardware module includes a process of performing video decoding, it indicates that the currently played video decoding method is the hardware decoding method, and when the use condition of the hardware module includes no process of performing video decoding, it indicates that the currently played video decoding method is the soft decoding method. Of course, the specific manner of detecting the decoding manner of the currently played video may not be limited in the embodiment of the present application.

Step S130: and performing power consumption reduction processing for reducing the working frequency of the processor according to the power consumption reduction processing method corresponding to the decoding mode.

In the embodiment of the application, after the decoding mode for decoding the currently played video is detected, power consumption reduction processing may be performed according to the power consumption reduction processing method corresponding to the current decoding mode, so as to reduce power consumption of the electronic device.

Further, due to the development of technology, since the configuration of the electronic device is better at present, the performance of the processor is excellent, that is, the rated operating frequency and the maximum operating frequency of the processor are very high, when video playing is performed and the played video is displayed and enhanced, the performance of the processor is often excessive, which causes resource waste and causes higher power consumption. Therefore, the operating frequency of the processor can be appropriately reduced to reduce the power consumption of the electronic device.

In addition, when the hard decoding is adopted, the occupied resources of the processor are different from those of the soft decoding, so that the power consumption reduction processing for reducing the working frequency of the processor can be carried out according to the specific decoding mode for decoding the played video. When the soft decoding mode is adopted to decode the played video, the hard decoding mode is adopted to decode the played video, occupied resources of the central processing unit are large, and therefore the working frequency of the central processing unit can be reduced according to the fact that the reduction degree of the working frequency of the central processing unit in the hard decoding mode is larger than that in the soft decoding mode. For example, when the decoding mode is a hard decoding mode, the operating frequency of the central processing unit may be reduced to a first operating frequency, and when the decoding mode is a soft decoding mode, the operating frequency of the central processing unit may be reduced to a second operating frequency, where the second operating frequency is greater than the first operating frequency. When the working frequency of the central processing unit is reduced, the purpose of reducing the working frequency of the central processing unit can be achieved by closing the central processor core of the multi-core central processing unit or adjusting the working frequency of the central processor core.

In some embodiments, when performing the power consumption reduction processing for reducing the operating frequency of the processor, in addition to the above-described reduction of the operating frequency of the central processing unit, the operating frequency of the image processor may also be reduced, so that the power consumption of the electronic device is reduced.

According to the method for reducing the power consumption of the equipment, when the mode of displaying the enhanced processing is started during video playing, the decoding mode for decoding the played video is detected, then the power consumption reduction processing method corresponding to the decoding mode is used for reducing the working frequency of the processor, so that different power consumption reduction processing for reducing the working frequency of the processor is realized according to different decoding modes when the mode of displaying the enhanced processing is started, the effect of reducing the power consumption of the electronic equipment is achieved, and the cruising ability of the terminal equipment and the user experience of a user are improved.

Referring to fig. 3, another embodiment of the present application provides a method for reducing power consumption of a device, which is applicable to an electronic device, and the method for reducing power consumption of the device may include:

step S210: when video playing is carried out, whether a mode of display enhancement processing is started or not is judged, and the display enhancement processing comprises processing the played video by utilizing a preset image processing algorithm.

Step S220: and if the video decoding device is started, detecting a decoding mode for decoding the played video at present.

In the embodiment of the present application, step S210 and step S220 may refer to the contents of the above embodiments, and are not described herein again.

Step S230: and when the decoding mode is a hard decoding mode, controlling the first central processor core to be closed and/or reducing the working frequency of the second central processor core, wherein the working frequency of the first central processor core is greater than the working frequency of the second central processor core.

In the embodiment of the present application, after the decoding mode for decoding the currently played video is detected, power consumption reduction processing for reducing the operating frequency of the processor may be performed according to the power consumption reduction processing method corresponding to the decoding mode.

Due to the development of technology, the maximum operating frequency of the central processing units and the maximum operating frequency of the image processors of most of the electronic devices are higher, and most of the central processing units are multi-core processors. The processor cores of the multi-core processor may include a first central processor core and a second central processor core, and the operating frequency of the first central processor core is greater than the operating frequency of the second central processor core. That is, the processor cores of the multi-core processor may be divided into a large core and a small core, where the large core refers to a central processor core with a high operating frequency, and the small core refers to a central processor core with a low operating frequency. For example, the central processing unit of the electronic device is an eight-core central processing unit, and the central processor core of the eight-core central processing unit is divided into four large cores and four small cores, i.e., four first central processor cores and four second central processor cores.

Furthermore, when the played video is decoded by adopting a hard decoding mode, the decoding task does not occupy the resource of the central processing unit, so that the first central processing unit core of the central processing unit can be controlled to be closed, and/or the working frequency of the second central processing unit core of the central processing unit can be reduced. It can be understood that, when the playing video is decoded by using the hard decoding method, the remaining resources of the central processing unit are more, so that the first central processing unit core may be selected to be turned off, and the operating frequency of the second central processing unit core is reduced, that is, the large core and the small core are turned off, or only the first central processing unit core may be turned off, that is, only the large core is turned off, or only the second central processing unit core is turned off, that is, the small core is turned off. In some embodiments, the first central processor core of the central processor may be selectively controlled to be turned off and/or the operating frequency of the second central processor core of the central processor may be reduced according to the actual situation, the performance parameters of the central processor, and the like. For example, when the performance of the central processing unit is better, the first central processing unit core can be turned off and the operating frequency of the second central processing unit core can be reduced at the same time. The working frequency of the second central processor core is required to be within a certain range of the working frequency required by the hard decoding and the display enhancement processing, so that the phenomenon that the central processor is overloaded to cause video playing jamming or application program crash and the like is avoided.

In the embodiment of the present application, the central processor core of the central processing unit can be controlled by hot-plug driver and DVFS driver in Kernel (real-time operating system). The hot-plug driver is used for controlling the core number of the central processing unit in the switch, namely controlling the opening and closing of the central processing unit core, and the DVFS driver is used for adjusting the frequency of the central processing unit core.

In some embodiments, the first central processor core may be turned off and/or the operating frequency of the second central processor core may be reduced according to the application program actually playing the video. For example, in some video playing applications, the number of tasks that the central processing unit is required to execute is small, so the first central processing unit core can be turned off, and the operating frequency of the second central processing unit core can be reduced, specifically, the extent to which the operating frequency of the second central processing unit core is reduced can be set according to actual requirements. For another example, in some video playing applications, the central processing unit is required to perform more tasks, so the first central processor core may be turned off, or the operating frequency of the second central processor core may be reduced. Therefore, the problem that the video playing is blocked or the application program is crashed due to the over-high load of the central processing unit is avoided.

In some embodiments, when the decoding mode for decoding the played video is a hard decoding mode, the first central processor core may be controlled to be turned off according to the real-time load rate of the central processor, and/or the operating frequency of the second central processor core may be reduced, so as to avoid a stall caused by an excessively high load of the central processor after the power consumption reduction processing is performed. Therefore, referring to fig. 4, step S230 may include:

step S231: and when the decoding mode is a hard decoding mode, detecting the current load rate of the central processing unit.

In the embodiment of the present application, when the decoding mode is a hard decoding mode, the load condition of the central processing unit may be detected to obtain the current load rate of the central processing unit, so as to subsequently control the first central processing unit core to be turned off according to the current load rate, and/or reduce the operating frequency of the second central processing unit core. For example, when the operating system of the terminal device is an Android system, the load condition and the process time of the system can be obtained through a ProcessStats class in the Android system. The specific implementation principle is that files under the proc directory are read, when the system runs, the kernel can update the files under the proc directory, and the running condition of the PID is written into the corresponding files. The current load rate of the central processing unit can be obtained by obtaining the ratio of the current load of the central processing unit to the maximum load of the central processing unit. Of course, the above manner of obtaining the current load factor of the central processing unit is not limited in the implementation of the present application.

Step S232: and judging whether the current load rate is lower than a first load rate threshold value or not.

After the current load rate of the central processing unit is obtained through detection and the current load rate of the central processing unit of the terminal device is obtained, the first central processing unit core can be controlled to be closed according to the current load rate, and/or the working frequency of the second central processing unit core is reduced.

In this embodiment, the load ratios of the central processing units may be divided into a first level and a second level, where the load ratio lower than the first load ratio threshold is in the first level, and the load ratio not lower than the first load ratio threshold is in the second level. When the load rate is a first level, the load rate indicates that the load of the current central processing unit is in a very low condition, that is, the number of tasks required to be executed by the central processing unit is very small, that is, the current thread number is very low; when the load rate is the second level, it indicates that the load of the current cpu is in a lower state, that is, the number of tasks that the cpu needs to execute is less, that is, the current number of threads is lower, but more tasks need to be executed by the cpu than in the first level, and the number of threads is also higher than in the first level.

Further, it may be determined whether the obtained current load rate of the central processing unit is smaller than a first load rate threshold, so as to control the first central processing unit core to be turned off and/or reduce the operating frequency of the second central processing unit core according to the determination result.

Step S233: and if the load rate is lower than the first load rate threshold value, controlling the first central processor core to be closed, and reducing the working frequency of the second central processor core.

It is understood that when the current load rate of the central processing unit is lower than the first load rate threshold, that is, the current load rate is at the first level, it may indicate that the current load of the central processing unit is very low, that is, the central processing unit is required to perform very few tasks, and thus the operating frequency of the central processing unit is required to be low. That is, the operating frequency of the central processing unit can be currently reduced to a very low level. Thus, the first central processor core may be controlled to be turned off and the operating frequency of the second central processor core may be reduced.

Further, when the operating frequency of the second cpu core is reduced, the operating frequency may be reduced to a set frequency corresponding to the current load factor. The terminal device may store a corresponding relationship between the load rate and the operating frequency of the second central processing unit core when the load rate of the central processing unit is smaller than the first load rate threshold. The corresponding relation can be obtained through experiments, namely the running condition of executing the task only by the working frequency of the second central processing unit core after the first central processing unit core is closed. The specific correspondence between the load factor and the operating frequency of the second central processing unit core may not be limited in this embodiment of the application. In addition, it is necessary to reduce the operating frequency of the second cpu core to a certain range of the operating frequency required for decoding by hard decoding and displaying the enhanced processor, so as to avoid the video playing jamming or application crash caused by the high load rate of the cpu. Therefore, when the current load rate is lower than the first load rate threshold, the power consumption of the central processing unit is reduced, and the effect of reducing the power consumption of the terminal equipment is achieved.

Step S234: and if the load rate is not lower than the first load rate threshold, controlling the first central processor core to be closed, or reducing the working frequency of the second central processor core.

It can be understood that, when it is determined that the current load rate of the central processing unit is not lower than the first load rate threshold, that is, the current load rate is in the second level, and the load of the current central processing unit is in a lower condition, that is, the number of tasks that the central processing unit needs to execute is less, that is, the current number of threads is lower, but more tasks need to be executed by the central processing unit than in the first level, and the number of threads is also higher than in the first level. Thus, only the first central processor core may be controlled to be turned off, or only the operating frequency of the second central processor core may be reduced. The terminal device may store a corresponding relationship between the load rate and the operating frequency of the second central processing unit core when the load rate of the central processing unit is not lower than the first load rate threshold. The corresponding relation can be obtained through experiments, namely the running condition of the task executed by the central processing unit after the working frequency of the second central processing unit core is reduced when the first central processing unit core is started. The specific correspondence between the load factor and the operating frequency of the second central processing unit core may not be limited in this embodiment of the application. In addition, it is necessary to reduce the operating frequency of the second cpu core to a certain range of the operating frequency required for decoding by hard decoding and displaying the enhanced processor, so as to avoid the video playing jamming or application crash caused by the high load rate of the cpu. Therefore, when the current load rate is not lower than the first load rate threshold, the power consumption of the central processing unit is reduced, and the effect of reducing the power consumption of the terminal equipment is achieved.

Step S240: the operating frequency of the image processor is reduced.

In the embodiment of the present application, when performing the power consumption reduction processing for reducing the operating frequency of the processor, in addition to the above-mentioned reduction of the operating frequency of the central processing unit, the operating frequency of the image processor may also be reduced, so that the power consumption of the electronic device is reduced. It can be understood that, since most of the electronic devices at present use the VPU for hard decoding, it does not occupy the GPU resources, so the operating frequency of the image processor can be reduced appropriately. The specific degree to which the operating frequency of the image processor needs to be reduced may not be limited in the embodiment of the present application, and may be determined according to a performance parameter of the image processor.

In the embodiment of the present application, please refer to fig. 5, step S240 may include:

step S241: and judging whether the current video playing mode is a full-screen playing mode.

In the embodiment of the application, whether the working frequency of the image processor is reduced or not can be determined by detecting whether the current video playing mode is a full-screen playing mode or not. It can be understood that when the full-screen playing mode is adopted to play the video, the image processor needs to process more tasks than the non-full-screen playing mode. Therefore, when the video is played in a full-screen playing mode, if the operating frequency of the image processor is lowered, the load of the image processor may be high, and the video may be jammed. When the video is played in a non-full-screen playing mode, if the working frequency of the image processor is reduced, the load of the image processor is not high.

Step S242: if the mode is not the full screen playing mode, the working frequency of the image processor is reduced.

When it is determined in step S241 that the current video playing mode is not the full-screen playing mode, the operating frequency of the image processor may be reduced, and the specific degree to which the operating frequency of the image processor needs to be reduced may not be limited in this embodiment, and may be determined according to the performance parameter of the image processor.

According to the method for reducing the power consumption of the device, when the video is played and the mode of the display enhancement processing is started, the decoding mode for decoding the played video is detected, and then when the decoding mode is the hard decoding mode, the first central processor core is controlled to be closed, and/or the working frequency of the second central processor core is reduced. In addition, according to the current load rate of the central processing unit, the first central processing unit core is controlled to be closed, and/or the working frequency of the second central processing unit core is reduced, and the blocking after the power consumption is reduced is avoided. In addition, the working frequency of the image processor is also reduced, so that the power consumption of the image processor is reduced. Therefore, the power consumption of the electronic equipment in the video playing display enhancement process is reduced, and the cruising ability of the terminal equipment is improved.

Referring to fig. 6, another embodiment of the present application provides a method for reducing power consumption of a device, which is applicable to an electronic device, and the method for reducing power consumption of the device may include:

step S310: when video playing is carried out, whether a mode of display enhancement processing is started or not is judged, and the display enhancement processing improves the image quality of the played video by processing images in the played video through optimizing parameters.

Step S320: and if the video decoding device is started, detecting a decoding mode for decoding the played video at present.

In the embodiment of the present application, step S310 and step S320 may refer to the contents of the above embodiments, and are not described herein again.

Step S330: and if the decoding mode is a soft decoding mode, reducing the working frequency of the first central processing unit core and/or reducing the working frequency of the second central processing unit core.

Furthermore, when the playing video is decoded by adopting a soft decoding mode, the decoding task occupies the resources of the central processing unit, so that the working frequency of the first central processing unit core can be reduced, and/or the working frequency of the second central processing unit core of the central processing unit can be reduced. It can be understood that when the playing video is decoded by using the soft decoding method, the remaining resources of the central processing unit may be more, so that the operating frequency of the first central processing unit core may be selectively reduced, and the operating frequency of the second central processing unit core may be reduced, that is, the operating frequencies of the large core and the small core are reduced at the same time, or only the operating frequency of the first central processing unit core may be reduced, that is, only the operating frequency of the large core is reduced, or only the operating frequency of the second central processing unit core may be reduced, that is, only the operating frequency of the small core is reduced. In some embodiments, the operating frequency of the first central processor core may be selectively reduced and/or the operating frequency of the second central processor core of the central processor may be reduced according to actual conditions, performance parameters of the central processor, and the like. For example, when the performance of the central processing unit is better, the operating frequency of the first central processing unit core can be reduced and the operating frequency of the second central processing unit core can be reduced at the same time. The working frequency to which the first central processor core and the second central processor core need to be reduced is required to be within a certain range of the working frequency required by soft decoding and display enhancement processing, so that the phenomenon that the central processor is overloaded to cause video playing jamming or application program crash and the like is avoided.

In the embodiment of the present application, the manner of adjusting the operating frequency of the processor core of the central processing unit may refer to the contents of the above embodiments, and is not described herein again.

In some embodiments, when the decoding mode for decoding the played video is a soft decoding mode, the operating frequency of the first central processing unit core may be reduced according to the real-time load rate of the central processing unit, and/or the operating frequency of the second central processing unit core may be reduced, so as to avoid a deadlock caused by an excessively high load of the central processing unit after the power consumption reduction processing is performed. Therefore, referring to fig. 7, step S330 may include:

s331: and if the decoding mode is a soft decoding mode, detecting the current load rate of the central processing unit.

In the embodiment of the present application, the manner of detecting the current load rate of the central processing unit may refer to the contents of the above embodiments, and is not described herein again.

S332: and judging whether the current load rate is lower than a second load rate threshold value or not.

In this embodiment of the present application, it may be determined whether the current load of the central processing unit is lower than a second load rate threshold, where the second load rate threshold may be greater than the first load rate threshold in the foregoing embodiment. Similarly, the load rate of the cpu may be divided into two levels (a third level and a fourth level) according to the second load rate threshold, where the load rate lower than the second load rate threshold is in the third level and the load rate not lower than the second load rate threshold is in the fourth level. When the load rate is the third level, it indicates that the load of the current central processing unit is in a lower condition, that is, the number of tasks required to be executed by the central processing unit is less, that is, the current thread number is lower; when the load rate is the fourth level, it indicates that the load of the current cpu is low, that is, the number of tasks that the cpu needs to execute is small, that is, the current number of threads is low, but more tasks need to be executed by the cpu than in the third level, and the number of threads is also higher than in the third level.

Further, it may be determined whether the obtained current load rate of the central processing unit is smaller than a second load rate threshold, so as to control to reduce the operating frequency of the first central processing unit and/or reduce the operating frequency of the second central processing unit core according to the determination result.

S333: if the load factor is lower than the second load factor threshold, the operating frequency of the first central processing unit core is reduced, and the operating frequency of the second central processing unit core is reduced.

It can be understood that, when the current load rate of the central processing unit is lower than the second load rate threshold, that is, the current load rate is at the third level, it may indicate that the load of the current central processing unit is in a lower condition, that is, the central processing unit is required to perform fewer tasks, and thus the operating frequency of the central processing unit is required to be lower. That is, the operating frequency of the central processing unit can be currently reduced to a lower level. Therefore, the operating frequency of the first central processor core can be reduced, and the operating frequency of the second central processor core can be reduced.

Further, when the operating frequencies of the first central processor core and the second central processor core are reduced, the operating frequencies can be reduced to a set frequency corresponding to the current load factor. The terminal device may store a corresponding relationship between the load rate and the operating frequency of the second central processing unit core when the load rate of the central processing unit is lower than the second load rate threshold. The corresponding relationship can be obtained through experiments, namely the running condition of the task executed by the central processing unit is obtained after the working frequencies of the first central processing unit core and the second central processing unit core are reduced simultaneously. The specific correspondence relationship may not be limited in the embodiments of the present application. In addition, the requirement for reducing the operating frequencies of the first central processor core and the second central processor core to a certain range of the operating frequency required for decoding by soft decoding and displaying the enhanced processor is met, so that the phenomenon that the video playing is blocked or the application program is crashed due to overhigh load rate of the central processor is avoided. Therefore, when the current load rate is lower than the second load rate threshold, the power consumption of the central processing unit is reduced, and the effect of reducing the power consumption of the terminal equipment is achieved.

S334: and if the load factor is not lower than the second load factor threshold, reducing the working frequency of the first central processing unit core, or reducing the working frequency of the second central processing unit core.

It can be understood that, when it is determined that the current load rate of the central processing unit is not lower than the second load rate threshold, that is, the current load rate is in the fourth level, and the load of the current central processing unit is in a low state, that is, the number of tasks that the central processing unit needs to execute is less, that is, the current number of threads is lower, but is more than the number of tasks that the central processing unit needs to execute in the third level, and the number of threads is also higher than the number of threads in the third level. Therefore, the operating frequency of the first central processing unit core can be reduced only, or the operating frequency of the second central processing unit core can be reduced only, so that the phenomenon that the load of the central processing unit is too high and video playing is blocked due to the fact that the operating frequencies of the first central processing unit core and the second central processing unit core are reduced simultaneously is avoided.

Step S340: the operating frequency of the image processor is reduced.

In the embodiment of the present application, step S340 may refer to the contents of the above embodiments, and is not described herein again.

In the method provided by the embodiment of the application, when the mode of the display enhancement processing is started during video playing, a decoding mode for decoding the played video is detected, and then when the decoding mode is a soft decoding mode, the working frequency of the first central processing unit core is reduced, and/or the working frequency of the second central processing unit core is reduced. In addition, according to the current load rate of the central processing unit, the working frequency of the first central processing unit core is reduced, and/or the working frequency of the second central processing unit core is reduced, and the blocking after the power consumption is reduced is avoided. In addition, the working frequency of the image processor is also reduced, so that the power consumption of the image processor is reduced. Therefore, the power consumption of the electronic equipment in the video playing display enhancement process is reduced, and the cruising ability of the terminal equipment is improved.

Referring to fig. 8, a block diagram of an apparatus for reducing power consumption of a device according to an embodiment of the present application is shown. The apparatus 400 for reducing power consumption of a device may include: an enhancement detection module 410, a decode detection module 420, and a power consumption processing module 430. The enhancement detection module 410 is configured to determine whether a mode of display enhancement processing is turned on when a video is played, where the display enhancement processing improves the quality of the played video by processing an image in the played video through an optimized parameter; the decoding detection module 420 is configured to detect a decoding mode of decoding a currently played video if the decoding detection module is turned on; the power consumption processing module 430 is configured to perform power consumption reduction processing for reducing the operating frequency of the processor according to the power consumption reduction processing method corresponding to the decoding manner.

As an embodiment, the processor includes a central processing unit, the central processing unit includes a first central processing unit core and a second central processing unit core, a maximum operating frequency of the first central processing unit core is greater than a maximum operating frequency of the second central processing unit core, and the power consumption processing module 430 may specifically be configured to: and when the decoding mode is a hard decoding mode, controlling the first central processor core to be closed and/or reducing the working frequency of the second central processor core, wherein the maximum working frequency of the first central processor core is greater than that of the second central processor core.

Further, referring to fig. 9, the power consumption processing module 430 may include: a first load detection unit 431, a first load judgment unit 432, a first execution unit 433, and a second execution unit 434. The first load detection unit 431 is configured to detect a current load rate of the central processing unit when the decoding mode is a hard decoding mode; the first load determining unit 432 is configured to determine whether the current load rate is lower than a first load rate threshold; the first execution unit 433 is configured to control the first central processor core to turn off and reduce the operating frequency of the second central processor core if the first load factor is lower than the first load factor threshold; the second execution unit 434 is configured to control the first central processor core to turn off or reduce the operating frequency of the second central processor core if the first load factor is not lower than the first load factor threshold.

As an embodiment, the power consumption processing module 430 may be specifically configured to: and if the decoding mode is a soft decoding mode, reducing the working frequency of the first central processing unit core and/or reducing the working frequency of the second central processing unit core.

Further, referring to fig. 10, the power consumption processing module 430 may include: a second load detection unit 435, a second load determination unit 436, a third execution unit 437, and a fourth execution unit 438. The second load detection unit 435 is configured to detect a current load rate of the central processing unit if the decoding mode is a soft decoding mode; the second load determination unit 436 is configured to determine whether the current load rate is lower than a second load rate threshold; the third execution unit 437 is configured to decrease the operating frequency of the first central processor core and decrease the operating frequency of the second central processor core if the second load factor is lower than the second load factor threshold; the fourth execution unit 438 is configured to decrease the operating frequency of the first central processor core or decrease the operating frequency of the second central processor core if the second load factor is not lower than the second load factor threshold.

In an embodiment of the present application, the processor further includes an image processor, and the power consumption processing module is further configured to: reducing the operating frequency of the image processor.

Further, the power consumption processing module reduces the operating frequency of the image processor, and may include: judging whether the current video playing mode is a full-screen playing mode or not; if the mode is not the full screen playing mode, the working frequency of the image processor is reduced.

It can be clearly understood by those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described apparatuses and modules may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, the coupling between the modules may be electrical, mechanical or other type of coupling.

In addition, functional modules in the embodiments of the present application may be integrated into one processing module, or each of the modules may exist alone physically, or two or more modules are integrated into one module. The integrated module can be realized in a hardware mode, and can also be realized in a software functional module mode.

To sum up, according to the scheme provided by the application, whether the mode of the display enhancement processing is started or not is judged when the video is played, when the mode of the display enhancement processing is started, the decoding mode of decoding the played video at present is detected, and the power consumption reduction processing for reducing the working frequency of the processor is performed according to the power consumption reduction processing method corresponding to the decoding mode, so that the power consumption reduction processing is performed according to the decoding mode when the mode of the display enhancement processing is started, and the effect of reducing the power consumption of the electronic equipment when the video is played is achieved.

Referring to fig. 11, a block diagram of an electronic device according to an embodiment of the present application is shown. The electronic device 100 may be a smart phone, a tablet computer, an electronic book, or other electronic devices capable of running an application. The electronic device 100 in the present application may include one or more of the following components: a processor 110, a memory 120, a screen 130, and one or more applications, wherein the one or more applications may be stored in the memory 120 and configured to be executed by the one or more processors 110, the one or more programs configured to perform the methods as described in the aforementioned method embodiments.

Processor 110 may include one or more processing cores. The processor 110 connects various parts within the overall electronic device 100 using various interfaces and lines, and performs various functions of the electronic device 100 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 120 and calling data stored in the memory 120. Alternatively, the processor 110 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA).

The processor 110 may integrate one or more of a Central Processing Unit (CPU) 111, a Graphics Processing Unit (GPU) 112, a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 110, but may be implemented by a communication chip.

The Memory 120 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 120 may be used to store instructions, programs, code sets, or instruction sets. The memory 120 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The storage data area may also store data created by the terminal 100 in use, such as a phonebook, audio-video data, chat log data, and the like.

The screen 130 is used to display information input by a user, information provided to the user, and various graphic user interfaces of the electronic device, which may be configured by graphics, text, icons, numbers, video, and any combination thereof, and in one example, a touch screen may be provided on the display panel so as to be integrated with the display panel.

Referring to fig. 12, a block diagram of a computer-readable storage medium according to an embodiment of the present application is shown. The computer-readable medium 800 has stored therein a program code that can be called by a processor to execute the method described in the above-described method embodiments.

The computer-readable storage medium 800 may be an electronic memory such as a flash memory, an EEPROM (electrically erasable programmable read only memory), an EPROM, a hard disk, or a ROM. Alternatively, the computer-readable storage medium 800 includes a non-volatile computer-readable storage medium. The computer readable storage medium 800 has storage space for program code 810 to perform any of the method steps of the method described above. The program code can be read from or written to one or more computer program products. The program code 810 may be compressed, for example, in a suitable form.

Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit the same; although the present application has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical solutions described in the foregoing embodiments may still be modified, or some technical features may be equivalently replaced; such modifications and substitutions do not necessarily depart from the spirit and scope of the corresponding technical solutions in the embodiments of the present application.

Claims

1. A method for reducing power consumption of a device, the method comprising:

when video playing is carried out, whether a mode of display enhancement processing is started or not is judged, and the display enhancement processing improves the image quality of the played video by processing images in the played video through optimizing parameters;

if the video playing mode is started, detecting a decoding mode for decoding the playing video at present;

and performing power consumption reduction processing for reducing the working frequency of the processor according to the power consumption reduction processing method corresponding to the decoding mode, wherein the decoding mode comprises hard decoding and soft decoding, and the reduction degree of the working frequency of the central processing unit in the hard decoding mode is greater than that in the soft decoding mode.

2. The method according to claim 1, wherein the processor includes a central processing unit, the central processing unit includes a first central processing unit core and a second central processing unit core, a maximum operating frequency of the first central processing unit core is greater than a maximum operating frequency of the second central processing unit core, and the power consumption reduction processing for reducing the operating frequency of the processor according to the power consumption reduction processing method corresponding to the decoding manner includes:

and when the decoding mode is a hard decoding mode, controlling the first central processor core to be closed and/or reducing the working frequency of the second central processor core, wherein the working frequency of the first central processor core is greater than the working frequency of the second central processor core.

3. The method of claim 2, wherein controlling the first central processor core to turn off and/or reduce the operating frequency of the second central processor core when the decoding mode is a hard decoding mode comprises:

when the decoding mode is a hard decoding mode, detecting the current load rate of the central processing unit; judging whether the current load rate is lower than a first load rate threshold value or not;

if the load rate is lower than the first load rate threshold value, controlling the first central processor core to be closed, and reducing the working frequency of the second central processor core; and if the load rate is not lower than the first load rate threshold, controlling the first central processor core to be closed, or reducing the working frequency of the second central processor core.

4. The method according to claim 1, wherein the processor includes a central processing unit, the central processing unit includes a first central processing unit core and a second central processing unit core, a maximum operating frequency of the first central processing unit core is greater than a maximum operating frequency of the second central processing unit core, and the power consumption reduction processing for reducing the operating frequency of the processor according to the power consumption reduction processing method corresponding to the decoding manner includes:

and if the decoding mode is a soft decoding mode, reducing the working frequency of the first central processing unit core and/or reducing the working frequency of the second central processing unit core.

5. The method of claim 4, wherein said reducing the operating frequency of the first central processing unit and/or reducing the operating frequency of the second central processing unit core if the decoding mode is a soft decoding mode comprises: if the decoding mode is a soft decoding mode, detecting the current load rate of the central processing unit;

judging whether the current load rate is lower than a second load rate threshold value or not;

if the load factor is lower than the second load factor threshold, reducing the working frequency of the first central processor core and reducing the working frequency of the second central processor core;

and if the load factor is not lower than the second load factor threshold, reducing the working frequency of the first central processing unit core, or reducing the working frequency of the second central processing unit core.

6. The method of any of claims 2-5, wherein the processor further comprises an image processor, the method further comprising:

reducing the operating frequency of the image processor.

7. The method of claim 6, wherein the reducing the operating frequency of the image processor comprises:

judging whether the current video playing mode is a full-screen playing mode or not;

and if the mode is not the full-screen playing mode, reducing the working frequency of the image processor.

8. An apparatus for reducing power consumption of a device, the apparatus comprising: an enhanced detection module, a decoding detection module and a power consumption processing module, wherein,

the enhancement detection module is used for judging whether a mode of display enhancement processing is started or not when video playing is carried out, wherein the display enhancement processing comprises processing the played video by utilizing a preset image processing algorithm;

the decoding detection module is used for detecting the current decoding mode for decoding the played video if the decoding detection module is started;

the power consumption processing module is used for performing power consumption reduction processing for reducing the working frequency of the processor according to the power consumption reduction processing method corresponding to the decoding mode, wherein the decoding mode comprises hard decoding and soft decoding, and the reduction degree of the working frequency of the central processing unit in the hard decoding mode is greater than that in the soft decoding mode.

9. An electronic device, comprising: one or more processors;

a memory;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method of any of claims 1-7.

10. A computer-readable storage medium, characterized in that the computer-readable storage medium

Stored with program code which can be invoked by a processor for carrying out the method according to any one of claims 1 to 7.