CN113052748A

CN113052748A - Graphics processor and video decoding display method

Info

Publication number: CN113052748A
Application number: CN202110228958.6A
Authority: CN
Inventors: 敬念
Original assignee: Changsha Jingmei Integrated Circuit Design Co ltd; Changsha Jingjia Microelectronics Co ltd
Current assignee: Changsha Jingmei Integrated Circuit Design Co ltd; Changsha Jingjia Microelectronics Co ltd
Priority date: 2021-03-02
Filing date: 2021-03-02
Publication date: 2021-06-29
Anticipated expiration: 2041-03-02
Also published as: CN113052748B

Abstract

The embodiment of the application provides a graphic processor and a decoding display method, wherein the graphic processor comprises a hardware decoding module, a double-rate synchronous dynamic random access memory, an output module and a 2D hardware module; the double-rate synchronous dynamic random access memory is used for storing the acquired video data; the hardware decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory; and the 2D hardware module is used for copying the decoded video data from the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for displaying through the output module. The video decoding, the data copying and the output display are executed by the graphic processor, so that the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding and displaying efficiency is improved.

Description

Graphics processor and video decoding display method

Technical Field

The present application relates to the field of computer graphics processing technologies, and in particular, to a graphics processor and a video decoding display method.

Background

The video card supports video decoding and display in addition to image processing and display. The video decoding and displaying is usually realized by software or hardware, color conversion or scaling processing is often required to be performed by software or other modules after the video decoding, and after the decoded video is processed, a central processing unit is required to copy data to display equipment for displaying. However, performing video decoding display in this way not only increases the CPU utilization, but also the efficiency of video display is not high.

Disclosure of Invention

The embodiment of the application provides a graphic processor and a video decoding display method, which can effectively solve the problems of high utilization rate of a CPU (Central processing Unit) and low video display efficiency.

According to a first aspect of embodiments of the present application, there is provided a graphics processor, the graphics processor including a hardware decoding module, a double rate synchronous dynamic random access memory, an output module, and a 2D hardware module; the double-rate synchronous dynamic random access memory is used for storing the acquired video data; the hardware decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory; and the 2D hardware module is used for copying the decoded video data from the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for displaying through the output module.

According to a second aspect of the embodiments of the present application, there is provided a video decoding display method, including: acquiring video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video data to display equipment for displaying.

According to a third aspect of embodiments of the present application, there is provided a video decoding display apparatus, including: the acquisition module is used for acquiring video data; the decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in a double-rate synchronous dynamic random access memory; and the display module is used for copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for displaying.

According to a fourth aspect of embodiments herein, there is provided an electronic device comprising one or more processors; a memory; one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more programs configured to perform the method as applied to an electronic device, as described above.

According to a fifth aspect of the embodiments of the present application, there is provided a computer-readable storage medium having a program code stored therein, wherein the method described above is performed when the program code runs.

By adopting the graphic processor and the video decoding display method provided by the embodiment of the application, the graphic processor decodes the acquired video data and stores the decoded video data in the double-rate synchronous dynamic random access memory; and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for displaying. The video decoding, copying the decoded video data to a video window and outputting and displaying are all executed by the graphic processor, so that the utilization rate of a central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding and displaying efficiency is improved.

Drawings

The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiment(s) of the application and together with the description serve to explain the application and not to limit the application. In the drawings:

FIG. 1 is a block diagram of a graphics processor provided in an embodiment of the present application;

fig. 2 is a schematic diagram illustrating a connection between a graphics processor and a cpu and a system memory according to an embodiment of the present application;

fig. 3 is a flowchart of a video decoding display method according to an embodiment of the present application;

FIG. 4 is a schematic diagram of an interface for displaying video data according to an embodiment of the present application;

FIG. 5 is a functional block diagram of a video decoding display apparatus according to an embodiment of the present application;

fig. 6 is a block diagram of an electronic device for performing a video decoding display method according to an embodiment of the present application.

Detailed Description

Video decoding display is a common graphics processing technique. The traditional video decoding is realized by software or hardware, firstly, the video is decoded to obtain decoded video data, and after the decoding, color conversion or scaling is required to be carried out by software or other modules. After Processing, a Central Processing Unit (CPU) is also required to copy the data to a display device for display.

The inventor finds in research that, in displaying, the CPU usually copies data to a display device for displaying, that is, after decoding and processing video, data interaction with the CPU is also required for displaying. In this way, because the CPU needs to copy data, the utilization rate of the CPU is increased, and it takes a certain time to transmit data when the CPU copies data, thereby causing video decoding display inefficiency.

In view of the foregoing problems, an embodiment of the present application provides a graphics processor and a video decoding display method, where the graphics processor decodes acquired video data, and stores the decoded video data in a double-rate synchronous dynamic random access memory; and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window for displaying. The video decoding, copying the decoded video data to a video window and outputting and displaying are all executed by the graphic processor, so that the utilization rate of a central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding and displaying efficiency is improved.

The solution in the embodiment of the present application may be implemented by using various computer languages, for example, object-oriented programming language Java and transliterated scripting language JavaScript.

In order to make the technical solutions and advantages of the embodiments of the present application more apparent, the following further detailed description of the exemplary embodiments of the present application with reference to the accompanying drawings makes it clear that the described embodiments are only a part of the embodiments of the present application, and are not exhaustive of all embodiments. It should be noted that the embodiments and features of the embodiments in the present application may be combined with each other without conflict.

Referring to fig. 1, a diagram of a graphics processor architecture according to an embodiment of the present application is shown. A Graphics Processing Unit (GPU) 10 includes a 2D hardware module 11, a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM)12, a hardware decoding module 13, and an output module 14. The double-rate synchronous dynamic random access memory 12 is configured to store the video data acquired by the GPU 10; the hardware decoding module 13 is configured to decode the video data according to the size of a video window, and store the decoded video data in the DDR SDRAM 12; the 2D hardware module is configured to copy the decoded video data from the DDR SDRAM12 to the video window, and output the video data to a display device for displaying through the output module 14.

The 2D hardware module 11, the DDR SDRAM12, the hardware decoding module 13, and the output module 14 are connected through an AXI bus. AXI is a bus protocol, which is a high performance, high bandwidth, low latency on-chip bus. The 2D hardware module 11, the DDR SDRAM12, the hardware decoding module 13, and the output module 14 in the GPU10 are connected by an AXI bus so as to communicate with each other.

Fig. 2 is a schematic diagram illustrating a connection between a GPU and a Central Processing Unit (CPU) and a system memory according to an embodiment of the present disclosure.

The 2D hardware module 11, the DDR SDRAM12, the hardware decoding module 13, and the output module 14 in the GPU10 are connected by an AXI bus, and the AXI bus is connected with the CPU10 and the system memory 30 by a PCIe bus. Therefore, the GPU10 can perform data transmission with the CPU 20 and the system memory 30, so that the GPU10 can acquire video data from the system memory 30 through the CPU 20, and the GPU10 can decode and display the acquired video data. After acquiring the video data, the GPU10 may store the video data in the DDR SDRAM12, and the hardware decoding module 13 may acquire the video data from the DDR SDRAM12 through an AXI bus and decode the video data.

When the hardware decoding module 13 decodes the video data, the parameters of a video window for displaying the video data may be acquired, and the video data is decoded according to the parameters of the video window, so that the decoded video data is matched with the video window. The parameter of the video window may be a display position of the video window, a size of the video window, a rotation angle of the video window, or an output format of the video window.

The hardware decoding module 13 may decode the video data according to the parameter of the video window to obtain YVU data, convert the YVU data into RGB data, and write the RGB data into the DDR SDRAM 12. YUV data and RGB data are data formats of images, video frames. Y in YUV, corresponds to the "luminance" component of the gray scale, and UV is two "chrominance" components, where U is the blue projection and V is the red projection. The hardware decoding module 13 may obtain the YUV component of each pixel in the video frame, decode the video data into YUV data, convert the YUV data into RGB data, and store the RGB data in the DDR SDRAM12 for subsequent use.

It can be understood that if the video data needs to be displayed by using YUV data, it is not necessary to convert the YUV data into RGB data, and the embodiment of the present application only uses RGB data as an example for the following description.

After the video decoding is completed, a series of processing, such as size conversion, rotation, etc., is usually performed on the decoded data to adapt to the video window, and since the decoding is performed according to the parameters of the video window in the embodiment of the present application, the obtained decoded video data is directly adapted to the video window. After decoding, if the decoded video data is to be displayed, the decoded video data needs to be copied to a display frame memory.

Since the decoded video data is stored in the DDR SDRAM12, the 2D hardware module 11 may read the decoded video data from the DDR SDRAM12, and copy the decoded data to a display frame memory for display. That is, the 2D hardware module 11 reads the RGB data from the DDR SDRAM12, and copies the RGB data to a display frame memory, so as to display the video data. Because the video data needs to be displayed in a video window, a region corresponding to the video window in a display frame memory may be acquired, the decoded video data, that is, the RGB data, is copied to the region corresponding to the video window in the display frame memory, and the video data is displayed in the video window on a display device through the output module 14.

When the video data is displayed on the display device in the video window, the video data may be output to the display device through the output module 14 for displaying, and the output module 14 may be a High Definition Multimedia Interface (HDMI), and is connected to a display screen through the HDMI, so as to display the video data in the video window. The output module 14 may also be a Video Graphics Array (VGA) and is connected to the display screen through a VGA interface, so that the output module 14 can display the Video data on the display device in the Video window. The display device may be a display screen of an electronic device installed in the GPU, or may be a display device connected to the HDMI or VGA interface, such as a display, a television, or the like.

The graphics processor provided by the embodiment of the application comprises a hardware decoding module, a double-rate synchronous dynamic random access memory, an output module and a 2D hardware module; the double-rate synchronous dynamic random access memory stores the acquired video data; the hardware decoding module decodes the video data according to the parameters of the video window and stores the decoded video data in the double-rate synchronous dynamic random access memory; and the 2D hardware module copies the decoded video data to the video window from the double-rate synchronous dynamic random access memory and outputs the video data to display equipment for displaying through the output module. The 2D hardware module replaces a CPU to execute data copy, so that the utilization rate of the CPU can be effectively reduced, the data processing and data copy transmission time is also reduced, and the efficiency of video decoding and displaying is improved.

Referring to fig. 3, an embodiment of the present application provides a video decoding display method, which can be applied to the graphics processor provided in the foregoing embodiment, where the graphics processor can be installed in an electronic device, and the electronic device can be a computer or a server, and the method specifically includes the following steps.

Step 110, video data is acquired.

A Graphics Processing Unit (GPU) is connected to a Central Processing Unit (CPU) and a system memory via a PCIe bus. Therefore, the GPU may retrieve the video data from the system memory through the CPU. After the GPU acquires the video data, the GPU may process the video data to display the video data.

And 120, decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory.

After the GPU acquires the video data, the GPU may acquire parameters of a video window for displaying the video data, and decode the video data according to the parameters of the video window, so that the video data is matched with the video window when being displayed. The parameter of the video window may be a display position of the video window, a size of the video window, an output format of the video window, and the like.

After the GPU obtains the parameters of the video window, the GPU may decode the video data according to the parameters of the video window to obtain the decoded video data, and the GPU may store the decoded video data. The GPU is internally provided with a Double Data Rate Synchronous Dynamic Random Access Memory (DDR SDRAM), so that the GPU can store decoded Data in the internal DDR SDRAM for further processing.

Specifically, when the GPU decodes the video data, the GPU may decode the video data into YUV data according to the parameter of the video window, and after obtaining the YUV data, convert the YUV data into RGB data for display.

Step 130, copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video data to a display device for displaying.

And decoding the acquired video data at the GPU to obtain the decoded video data, namely RGB data, and storing the decoded video data in the DDR SDRAM. Generally, if the video data is to be displayed, the video data needs to be copied to a display frame memory, and the video data is displayed on a display screen while waiting for a screen refresh. Therefore, the GPU may copy the decoded video data stored in the DDR SDRAMSDRAM to a display frame memory for display while waiting for a screen refresh. Because the video data is displayed in the video window, the GPU may copy the decoded video data to a corresponding area of the video window in the display frame memory, and wait for a screen refresh to display the video data.

It will be appreciated that the GPU may be installed in an electronic device and the video data may be displayed in a variety of ways.

In some embodiments, when the electronic device is equipped with a display function, the GPU may directly display the video data on a display screen of the electronic device.

In some embodiments, the GPU may further include a plurality of Graphics output interfaces, such as a High Definition Multimedia Interface (HDMI), a Video Graphics Array (VGA), and the like. Through HDMI and VGA interface, can be connected with display device to can export the video data to display device shows.

Referring to fig. 4, a schematic diagram of an interface for displaying video data is shown. In the display interface shown in fig. 4, various elements 41 may be displayed, and in the area of the dashed box indicated at 42, the video data may be displayed, i.e. the dashed box is the video window within which the video data is displayed.

This process is described below as a specific example. Assuming that the GPU is installed on a computer display card, a user can use a player to play video on a computer, and when a multimedia video file is played, the GPU can acquire the video data from a system memory through a CPU. After the video data are obtained, decoding the video data into YUV data according to parameters of a video window, converting the YUV data into RGB data, storing the RGB data in DDR SDRAM inside a GPU, copying the RGB data stored in the DDR SDRAM to a region corresponding to the video window in a display frame memory by the GPU, and outputting the RGB data to a screen for displaying, thereby realizing the display of the video data in the video window. The user can then view the video on the computer.

The decoding display method provided by the embodiment of the application acquires video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video data to display equipment for displaying. The GPU is used for executing video decoding, the video data after being copied to the video window and output display are all executed by the graphics processor, the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding and display efficiency is improved.

Referring to fig. 5, an embodiment of the present application provides a video decoding display apparatus 200, which can be applied to an electronic device, where the video decoding display apparatus 200 includes an obtaining module 210, a decoding module 220, and a display module 230. The obtaining module 210 is configured to obtain video data; the decoding module 220 is configured to decode the video data according to a parameter of a video window, and store the decoded video data in a double-rate synchronous dynamic random access memory; the display module 230 is configured to copy the decoded video data in the double-rate sdram to the video window, and output the video data to a display device for displaying.

Further, the decoding module 220 is further configured to decode the video data into YUV data according to the parameter of the video window; and converting the YUV data into RGB data.

Further, the display module 230 is further configured to obtain RGB data in the double-rate sdram; and copying the RGB data to an area corresponding to the video window in a display frame memory and outputting the RGB data to display equipment for displaying.

The video decoding display device provided by the embodiment of the application acquires video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video data to display equipment for displaying. The GPU is used for executing video decoding, the video data after being copied to the video window and output display are all executed by the graphics processor, the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding and display efficiency is improved.

It should be noted that, as will be clear to those skilled in the art, for convenience and brevity of description, the specific working process of the above-described apparatus may refer to the corresponding process in the foregoing method embodiment, and is not described herein again.

Referring to fig. 6, an embodiment of the present application provides a block diagram of an electronic device, where the electronic device 300 includes a processor 310, a memory 320 and one or more application programs, where the one or more application programs are stored in the memory 320 and configured to be executed by the one or more processors 310, and the one or more programs are configured to perform the above-mentioned method for displaying decoded video.

The electronic device 300 may be a terminal device such as a notebook computer or a computer capable of running an application program, or may be a server. The electronic device 300 in the present application may include one or more of the following components: a processor 310, a memory 320, and one or more applications, wherein the one or more applications may be stored in the memory 320 and configured to be executed by the one or more processors 310, the one or more programs configured to perform a method as described in the aforementioned method embodiments.

Processor 310 may include one or more processing cores. The processor 310 connects various parts throughout the electronic device 300 using various interfaces and lines, and performs various functions of the electronic device 300 and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 320 and calling data stored in the memory 320. Alternatively, the processor 310 may be implemented in hardware using at least one of Digital Signal Processing (DSP), Field-Programmable Gate Array (FPGA), and Programmable Logic Array (PLA). The processor 310 may integrate one or more of a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), a modem, and the like. Wherein, the CPU mainly processes an operating system, a user interface, an application program and the like; the GPU is used for rendering and drawing display content; the modem is used to handle wireless communications. It is understood that the modem may not be integrated into the processor 310, but may be implemented by a communication chip.

The Memory 320 may include a Random Access Memory (RAM) or a Read-Only Memory (Read-Only Memory). The memory 320 may be used to store instructions, programs, code sets, or instruction sets. The memory 320 may include a stored program area and a stored data area, wherein the stored program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing various method embodiments described below, and the like. The data storage area may also store data created by the electronic device 300 during use (e.g., phone book, audio-video data, chat log data), etc.

The electronic equipment provided by the embodiment of the application acquires video data; decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory; and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video data to display equipment for displaying. The GPU is used for executing video decoding, the video data after being copied to the video window and output display are all executed by the graphics processor, the utilization rate of the central processing unit can be effectively reduced, the data processing and data copying transmission time is also reduced, and the video decoding and display efficiency is improved.

As will be appreciated by one skilled in the art, embodiments of the present application may be provided as a method, system, or computer program product. Accordingly, the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present application may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.

The present application is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.

These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A graphics processor is characterized by comprising a hardware decoding module, a double-rate synchronous dynamic random access memory, an output module and a 2D hardware module;

the double-rate synchronous dynamic random access memory is used for storing the acquired video data;

the hardware decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in the double-rate synchronous dynamic random access memory;

and the 2D hardware module is used for copying the decoded video data from the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for displaying through the output module.

2. The graphics processor of claim 1, wherein the hardware decode module, double rate synchronous dynamic random access memory, output module, and 2D hardware module are connected by an AXI bus, the AXI bus connected to a central processor and system memory by a PCIe bus.

3. The graphics processor of claim 2, wherein the graphics processor obtains the video data from the system memory via the cpu and stores the video data in the ddr sdram.

4. The graphics processor of claim 1, wherein the hardware decoding module decodes the video data into YUV data and converts the YUV data into RGB data.

5. The graphics processor of claim 1, wherein the output module comprises a high definition multimedia interface or a video graphics array.

6. A video decoding display method applied to the graphics processor of any one of claims 1 to 5, the method comprising:

acquiring video data;

decoding the video data according to the parameters of the video window, and storing the decoded video data in a double-rate synchronous dynamic random access memory;

and copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window, and outputting the video data to display equipment for displaying.

7. The method of claim 6, wherein the decoding the video data according to the parameters of the video window comprises:

decoding the video data into YUV data according to the parameters of the video window;

and converting the YUV data into RGB data.

8. The method of claim 7, wherein copying the decoded video data in the double rate synchronous dynamic random access memory to the video window and outputting the video data to a display device for display comprises:

acquiring RGB data in the double-rate synchronous dynamic random access memory;

and copying the RGB data to an area corresponding to the video window in a display frame memory and outputting the RGB data to display equipment for displaying.

9. A video decoding display apparatus, characterized in that the apparatus comprises:

the acquisition module is used for acquiring video data;

the decoding module is used for decoding the video data according to the parameters of the video window and storing the decoded video data in a double-rate synchronous dynamic random access memory;

and the display module is used for copying the decoded video data in the double-rate synchronous dynamic random access memory to the video window and outputting the video data to display equipment for displaying.

10. An electronic device, characterized in that the electronic device comprises:

one or more processors;

a memory electrically connected with the one or more processors;

one or more applications, wherein the one or more applications are stored in the memory and configured to be executed by the one or more processors, the one or more applications configured to perform the method of any of claims 6 to 8.

11. A computer-readable storage medium, having stored thereon program code that can be invoked by a processor to perform the method according to any one of claims 6 to 8.