CN113039761A - Cross Reference to Related Applications - Google Patents
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- CN113039761A CN113039761A CN202080006170.4A CN202080006170A CN113039761A CN 113039761 A CN113039761 A CN 113039761A CN 202080006170 A CN202080006170 A CN 202080006170A CN 113039761 A CN113039761 A CN 113039761A
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4917—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using multilevel codes
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M5/00—Conversion of the form of the representation of individual digits
- H03M5/02—Conversion to or from representation by pulses
- H03M5/20—Conversion to or from representation by pulses the pulses having more than three levels
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M7/00—Conversion of a code where information is represented by a given sequence or number of digits to a code where the same, similar or subset of information is represented by a different sequence or number of digits
- H03M7/02—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word
- H03M7/04—Conversion to or from weighted codes, i.e. the weight given to a digit depending on the position of the digit within the block or code word the radix thereof being two
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- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L25/00—Baseband systems
- H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
- H04L25/40—Transmitting circuits; Receiving circuits
- H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
- H04L25/4906—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes
- H04L25/4908—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using binary codes using mBnB codes
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L27/00—Modulated-carrier systems
- H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
- H04L27/04—Modulator circuits; Transmitter circuits
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Abstract
PAM4 or PAM8 symbols are encoded to have a Power Spectral Density (PSD) similar to that of a standard 8b10b non-return-to-zero stream. In one embodiment, the transmitter includes first and second 8b10b encoders that receive first and second streams separated from an original byte stream. The first and second 8b10b encoders output first and second 8b10b streams, respectively. The first and second 8b10b streams are fed to a 2-bit combiner that performs linear combining of the first and second 8b10b streams. A 4-level pulse amplitude modulation encoder (PAM4 encoder) converts the linear combination of every two bits received from the combiner into a PAM4 symbol. The resulting stream with PAM4 symbols has a PSD similar to that of the standard 8b10b non-return-to-zero stream.
Description
This application claims priority from U.S. provisional patent application No.62/873, 965 filed on 7, 14, 2019.
Background
8b/10b (referred to as 8b10b) is a line code that maps 8-bit words to 10-bit symbols to achieve DC balance and limited diversity. Non-return-to-zero (NRZ) codes are binary codes where a positive voltage represents a 1 and a negative voltage represents a 0, with no zero line condition. 8b10b NRZ has a unique Power Spectral Density (PSD) as is well known in the art.
Disclosure of Invention
When transmitting with 4-level pulse amplitude modulation (PAM4), the 8b10b NRZ Power Spectral Density (PSD) needs to be preserved to improve the transmission throughput while preserving compatibility with the 8b10b NRZ characteristic. However, the standard PAM4 modulation has a different power spectral density than the standard 8b10b NRZ modulation.
Thus, in one embodiment, two 8b10b encoders are linearly combined to form a PAM4 modulation having a PSD substantially the same as that of the standard 8b10b NRZ modulation, as shown below. The transmitter comprises first and second 8b10b encoders configured to receive first and second streams separated from an original byte stream; the first and second 8b10b encoders are configured to output first and second 8b10b streams, respectively. A 2-bit combiner configured to perform linear combining of the first and second 8b10b streams. And a 4-level pulse amplitude modulation encoder (PAM4 encoder) configured to convert a linear combination of every two bits received from the combiner into a PAM4 symbol.
Optionally, the first and second 8b10b encoders are standard 8b10b encoders, each outputting a bit stream having half the rate of the original byte stream. Optionally, the PAM4 symbol preserves the 8b10b non-return-to-zero line code transmit power spectral density with substantially the same overhead, which is about 25% for the standard 8b10 b. In one example, the implementation may be close to, but not identical to, the standard's 8b10b NRZ, and then the overhead may be slightly higher, e.g., up to 35% overhead. Optionally, the resulting stream of PAM4 symbols preserves the Power Spectral Density (PSD) of the standard 8b10b non-return-to-zero stream, which enables band separation between downlink and uplink channels of a transceiver including the transmitter. Optionally, the band separation enables the transceiver to transmit on the uplink channel without having to implement echo (echo) cancellation in both the uplink and downlink receivers. Optionally, a separation from the original byte stream is performed such that odd bits of the original byte stream are forwarded to the first 8b10b encoder and even bits of the original byte stream are forwarded to the second 8b10b encoder. Optionally, a separation from the original byte stream is performed such that two consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next two consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders. Optionally, four consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next four consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders. Alternatively, the conversion of each linear combination of two bits includes converting pair (0,0) to 1, converting pair (0,1) to 1/3, converting pair (1,0) to-1/3, and converting pair (1,1) to-1.
In another embodiment, a method comprises: receiving, by the first and second 8b10b encoders, the first and second streams separated from the original byte stream and outputting first and second 8b10b streams, respectively; performing linear combining of the first and second 8b10b streams by a 2-bit combiner; and converting the linear combination of every two bits received from the combiner into a PAM4 symbol.
Optionally, the resulting stream of PAM4 symbols preserves the Power Spectral Density (PSD) of the standard 8b10b non-return-to-zero stream, which enables band separation between downlink and uplink channels of a transceiver implementing the method. Optionally, a separation from the original byte stream is performed such that odd bits of the original byte stream are forwarded to the first 8b10b encoder and even bits of the original byte stream are forwarded to the second 8b10b encoder. Optionally, a separation from the original byte stream is performed such that two consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next two consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders. Optionally, four consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next four consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders.
In yet another embodiment, the transmitter includes first, second and third 8b10b encoders configured to receive first, second and third streams separated from an original byte stream. The first, second and third 8b10b encoders are configured to output first, second and third 8b10b streams, respectively. A 3-bit combiner is configured to perform linear combining of the first, second and third 8b10b streams. The PAM8 encoder is configured to convert a linear combination of every three bits received from the 3-bit combiner into a PAM8 symbol.
Drawings
Embodiments are described herein, by way of example only, with reference to the accompanying drawings. No attempt is made to show structural details of the embodiments in more detail than is necessary for a fundamental understanding of the embodiments. In the drawings:
fig. 1 shows one embodiment of a system 50, the system 50 outputting PAM4 symbols that preserve the 8b10b NRZ line code transmit PSD;
FIG. 2 shows a graph comparing transmit power spectral densities of various modulation schemes;
fig. 3 shows an embodiment of a method of outputting a PAM4 symbol, the PAM4 symbol preserving the 8b10b NRZ line code transmit PSD; and
fig. 4 and 5 are schematic diagrams of possible embodiments of a computer.
Description of the preferred embodiments
Fig. 1 illustrates an embodiment of a system 50 that outputs a 4-level pulse amplitude modulation (PAM4) symbol that preserves the 8b10b non-return to zero (NRZ) line code transmit Power Spectral Density (PSD) with a similar (e.g., 25%) overhead. The system 50 includes first and second 8b10b encoders (22,24) that receive first and second bitstreams separated from an original byte stream 20. As described below, the separation of the original byte stream into the first and second bit streams may take various forms. The first and second 8b10b encoders output first and second 8b10b streams, respectively. The first and second 8b10b streams are fed to a 2-bit combiner 26 that performs linear combining of the first and second 8b10b streams. PAM4 encoder 28 converts each linear combination of two corresponding bits into a PAM4 symbol. Due to the linear combination of the combiner 26 on the first and second 8b10b streams, the resulting stream of PAM4 symbols 30 has a PSD similar to that of the standard 8b10b NRZ stream.
The splitting of the original byte stream into the first and second streams may take various forms, such as (i) forwarding odd bits of the original byte stream to the first 8b10b encoder, and forwarding the even bits of the original byte stream to the second 8b10b encoder, (ii) forwarding two consecutive bits of the original byte stream to the first 8b10b encoder, forwarding the next two consecutive bits of the original byte stream to the second 8b10b encoder, and continues in such a manner as to flip the original byte stream between the first and second 8b10b encoders, or (iii) forward four consecutive bits of the original byte stream to the first 8b10b encoder, forward the next four consecutive bits of the original byte stream to the second 8b10b encoder, and continues in such a manner as to flip the original byte stream between the first and second 8b10b encoders.
In one embodiment, the first and second 8b10b encoders (22,24) are standard 8b10b encoders, each outputting a bit stream having half the rate of the original byte stream 20.
In one embodiment, the 2-bit combiner 26 performs linear combining of the first and second 8b10b streams by generating bit pairs from respective bits from the first and second 8b10b streams. The linear combination may have bits from the first 8b10b stream as valid bits and bits from the second 8b10b stream as invalid bits, or bits from the first 8b10b stream as invalid bits and bits from the second 8b10b stream as valid bits.
The PAM4 encoder 28 maps each bit pair to a PAM4 symbol, for example, by converting pair (0,0) to 1, pair (0,1) to 1/3, pair (1,0) to-1/3, and pair (1,1) to-1. The resulting stream of PAM4 symbols 30 has a PSD similar to that of the standard 8b10b NRZ stream, possibly due to the linear combination of the 8b10b streams performed by the combiner 26. In one example, the resulting stream of PAM4 symbols has a PSD with an overhead of 25% (which is similar to the overhead of the standard 8b10b NRZ stream).
In one embodiment, the system 50 does not use gray codes (also known as reflective binary codes). Gray codes are not linear operations and therefore the PSD of a PAM4 symbol generated by a similar system that does apply gray codes (optionally after a PAM4 encoder) should show sub-optimal low frequency rejection compared to this PAM4 symbol 30 generated by a system 50 that does not use gray codes.
Fig. 2 shows a graph comparing the transmitted PSD of 8b10b NRZ (referred to as 8b10b NRZ 500Vpp-3 dB; 60) and the transmitted PSD of PAM4 symbol 30 generated by system 50 (referred to as "8 b10b PAM 4" 500m Vpp; 61), the transmitted PSD of 8b10b PAM4500mVpp with gray code 62, and the transmitted PSD of standard PAM4500mVpp 63.
As shown in fig. 2, the PSD of "8 b10b PAM 4" with 500mVpp 61 at 4 gbaud (8Gbps) is very close to the low frequency rejection of PAM4 symbols 30 generated at 4 gbaud (4Gbps) with a similar maximum PSD system 50 (8b10b NRZ; 60). Since the root mean square value of PAM4 is 2.55 dB lower than NRZ, half-rate PAM4 at Full amplitude (Full-Amp) generates a transmit PSD similar to half-rate NRZ at Full amplitude-3 dB.
Still referring to fig. 2, the PSD of 8b10b PAM4500mVpp with gray code 62 at 4G baud shows sub-optimal rejection (band separation) relative to the PSD of 8b10b NRZ 60. When compared to the PSD of 8b10b NRZ 60, the PSD of ordinary PAM4500mVpp 63 is even worse than the PSD of 8b10b PAM4 with gray code 62.
In one embodiment, reserving the 8b10b NRZ PSD in PAM4 transmissions keeps the low frequency energy suppressed, which enables band separation between the downlink and uplink channels. This band separation enables the transceiver to transmit at low bit rates on the uplink channel at the low frequencies without having to implement echo cancellation in the uplink and downlink receivers.
In another embodiment, the 8b10b encoding concentrates its energy between the Nyquist (Nyquist) frequency and the Nyquist (Nyquist)/10 frequency, so it is easy to equalize such signals at the receiver using a low power, low complexity analog equalizer. Therefore, 8b10b is very popular in many PAM2 solutions. By maintaining the 8b10b NRZ PSD in PAM4, an embodiment of the system retains all the advantages of 8b10b NRZ, thus allowing an upgrade path to existing 8b10b PAM2 solutions that hope to add higher bit rate modes to existing PAM2 solutions. For example, PAM2 embodiments transmitting up to 4Gbps may be scaled to transmit up to 8Gbps at the same symbol rate, but using substantially the same receiver at PAM 4.
Fig. 3 shows an embodiment of a method of outputting a PAM4 symbol, which PAM4 symbol preserves the 8b10b NRZ line code transmit PSD. The method comprises the following steps. At step 70, the first and second streams separated from the original byte stream are received by the first and second 8b10b encoders and output first and second 8b10b streams, respectively. In step 71, linear combining of the first and second 8b10b streams is performed by a 2-bit combiner. And in step 72, converting the linear combination of every two bits received from the combiner into a PAM4 symbol.
Still referring to the method, optionally, the resulting stream of PAM4 symbols preserves the PSD of the standard 8b10b non-return-to-zero stream, which enables band separation between downlink and uplink channels of a transceiver implementing the method. Optionally, a separation from the original byte stream is performed such that odd bits of the original byte stream are forwarded to the first 8b10b encoder and even bits of the original byte stream are forwarded to the second 8b10b encoder. Optionally, a separation from the original byte stream is performed such that two consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next two consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders. And optionally four consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next four consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders.
In another embodiment, the system outputs 8-level pulse amplitude modulation (PAM8) symbols, the PAM8 symbols preserving the 8b10b NRZ line code transmit Power Spectral Density (PSD) with similar overhead. The system includes three 8b10b encoders for receiving three streams separated from the original byte stream. In a manner similar to the explanation provided above, the splitting of the original byte stream into three bit streams may take various forms. The three 8b10b encoders output three 8b10b streams, respectively. The three 8b10b streams are fed to a 3-bit combiner that performs linear combination of the three 8b10b streams. Every linear combination of three corresponding bits is converted to a PAM8 symbol by a PAM8 encoder. Since the combiner linearly combines the three 8b10b streams, the resulting stream of PAM8 symbols has a PSD similar to that of the standard 8b10bNRZ stream. In a similar manner, higher order PAM modulations (e.g., PAM16) may be generated by adding an additional 8b10b encoder and using a suitable PAM encoder.
The elements used by the embodiments may be implemented in various ways, for example using a processor. A "processor" may refer to one or more of the following components: a general purpose processing device, a microprocessor, a central processing unit, a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a Digital Signal Processor (DSP), and/or a network processor.
Elements, such as modules used by the systems described herein, may be implemented using a combination including one or more of the following hardware, firmware, and software elements: an Application Specific Integrated Circuit (ASIC), a Field Programmable Gate Array (FPGA), a processor, a memory block, a discrete circuit, an integrated circuit, at least one processor to execute commands stored in at least one memory block, a non-transitory computer-readable medium comprising computer-executable instructions that, when executed on a computing device, cause the computing device to perform certain operations, a processor and a computer-readable storage medium comprising a program of instructions executable by the processor, wherein the processor performs certain operations when the instructions are executed, a computer system comprising one or more processing units and a memory to store one or more programs, the system being configured to be executed by the one or more processor units, wherein the one or more programs comprise instructions for certain operations, a non-transitory computer-readable medium comprising data processing means and instructions to store instructions executable by the data processing means (in such a way Which when executed, causes the data processing apparatus to perform certain operations). The buffer may be implemented by using a memory to store data, and a processor to access the data through a communication channel, such as a parallel bus or a serial bus.
Fig. 4 and 5 are schematic diagrams of possible additional or alternative embodiments of computers (400,410) capable of implementing one or more embodiments discussed herein, including a "computer". The computer (400,410) may be implemented in various ways, such as, but not limited to, a microcontroller, a computer on a chip (SoC), a system on module (SoM), a processor with required peripherals, a server computer, a client computer, a personal computer, a cloud computer, a network device, a communication device, a handheld device, a wearable device, and/or any other form of computer capable of executing a set of computer instructions. Further, reference to a computer or processor includes any collection of one or more computers and/or processors (which may be in different locations) that individually or collectively execute one or more sets of computer instructions. This means that the singular term "computer" is intended to mean one or more computers, which collectively perform the functions attributed to that computer.
The computer 400 includes one or more of the following components: a processor 401, a memory 402, a computer-readable medium 403, a user interface 404, a communication interface 405, and a bus 406. The computer 410 includes one or more of the following components: a processor 411, a memory 412, and a communication interface 413.
The functionality of the various embodiments may be implemented in hardware, software, firmware, or any combination thereof. If implemented at least partially in software, implementing the functionality may involve a computer program comprising one or more instructions or code stored or transmitted on a computer-readable medium and executed by one or more processors. Computer-readable media may include computer-readable storage media corresponding to tangible media, such as data storage media, or communication media including any medium that facilitates transfer of a computer program from one place to another. A computer-readable medium may be any medium that can be accessed by one or more computers to retrieve instructions, code, data and/or data structures to implement the described embodiments.
The computer program product may include a computer-readable medium. In one example, the computer-readable medium 403 may include one or more of the following: random Access Memory (RAM), Read Only Memory (ROM), Electrically Erasable Programmable Read Only Memory (EEPROM), optical memory, magnetic memory, biological memory, flash memory, or any other medium capable of storing computer-readable data.
A computer program (also known as a program, software application, script, program code, or code) can be written in any form of programming language, including compiled or interpreted languages, declarative or procedural languages. The program may be deployed in any form, including as a stand-alone program or as a module, component, subroutine, object, or other unit suitable for use in a computing environment. A computer program may correspond to a file in a file system, may be stored in a portion of a file that holds other programs or data, and/or may be stored in one or more files dedicated to the program. A computer program can be deployed to be executed on one or more computers at one or more sites interconnected by a communication network.
A computer-readable medium may include a single medium and/or multiple media storing one or more sets of instructions. In various embodiments, the computer program and/or portions of the computer program may be stored on a non-transitory computer readable medium and may be updated and/or downloaded via a communication network such as the internet. At least some of the methods described herein are "computer-implemented methods" implemented on a computer, such as the computer (400,410), by executing instructions on the processor (401, 411). Additionally, at least some of the instructions may be stored on a non-transitory computer readable medium.
Although the methods disclosed herein have been described and illustrated with reference to particular steps performed in a particular order, it should be understood that these steps may be combined, sub-divided, and/or re-ordered to form an equivalent method without departing from the teachings of the embodiments. Accordingly, unless specifically indicated herein, the order and grouping of the steps is not a limitation of the embodiments. Furthermore, the methods and mechanisms of the embodiments will sometimes be described in the singular for the sake of clarity. However, unless otherwise noted, some embodiments may include multiple iterations of a method or multiple instantiations of a mechanism. For example, when a processor is disclosed in one embodiment, the scope of the embodiment is intended to also encompass the use of multiple processors. Certain features of the embodiments that have been described in the context of separate embodiments may also be provided in various combinations in a single embodiment, for clarity. Conversely, various features of the embodiments that have been described in the context of a single embodiment may also be provided separately or in any suitable subcombination for the sake of brevity. Embodiments described in connection with specific examples are presented by way of illustration and not limitation.
Reference herein to "one embodiment" means that the feature so indicated may be included in at least one embodiment of the invention. Furthermore, separate references to "one embodiment" or "some embodiments" in this description do not necessarily refer to the same embodiments. Furthermore, references to "one embodiment" and "another embodiment" do not necessarily refer to different embodiments, but rather are terms sometimes used to describe different aspects of an embodiment.
Embodiments may include any of a variety of combinations and/or integrations of the features of the embodiments described herein. Although some embodiments may depict serial operations, the embodiments may perform certain operations in parallel and/or in a different order than depicted. Moreover, the use of repeated reference numbers and/or letters in the text and/or drawings is for the sake of brevity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed. The embodiments are not limited in their application to the details of the order or sequence of steps of the method's operations or to the details of implementation of the apparatus set forth in the description, drawings, or examples. Furthermore, the individual blocks illustrated in the figures may be functional in nature and thus do not necessarily correspond to discrete hardware elements.
It is evident that many alternatives, modifications, and variations will be apparent to those skilled in the art. It is to be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the embodiments.
Claims (15)
1. A transmitter, comprising:
first and second 8b10b encoders configured to receive first and second streams separated from an original byte stream; the first and second 8b10b encoders are configured to output first and second 8b10b streams, respectively;
a 2-bit combiner configured to perform linear combining of the first and second 8b10b streams; and
a 4-level pulse amplitude modulation encoder (PAM4 encoder) configured to convert the linear combination of every two bits received from the combiner into a PAM4 symbol.
2. The transmitter of claim 1, wherein the first and second 8b10b encoders are standard 8b10b encoders, each encoder outputting a bitstream having one-half the rate of the original byte stream.
3. The transmitter of claim 1 wherein the PAM4 symbol preserves an 8b10b non-return-to-zero line code transmit power spectral density at approximately 25% overhead.
4. The transmitter of claim 1, wherein the resultant stream of PAM4 symbols preserves the Power Spectral Density (PSD) of a standard 8b10b non-return-to-zero stream, which enables band separation between downlink and uplink channels of a transceiver including the transmitter.
5. The transmitter of claim 4, wherein the band separation enables the transceiver to transmit on the uplink channel without implementing echo cancellation in both the uplink and downlink receivers.
6. The transmitter of claim 1, wherein separation from the original byte stream is performed such that odd bits of the original byte stream are forwarded to the first 8b10b encoder and even bits of the original byte stream are forwarded to the second 8b10b encoder.
7. The transmitter of claim 1, wherein a separation from the original byte stream is performed such that two consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next two consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders.
8. The transmitter of claim 1 wherein four consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next four consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders.
9. The transmitter of claim 1 wherein the conversion of each linear combination of two bits comprises converting pair (0,0) to 1, converting pair (0,1) to 1/3, converting pair (1,0) to-1/3, and converting pair (1,1) to-1.
10. A method, comprising:
receiving, by the first and second 8b10b encoders, the first and second streams separated from the original byte stream and outputting first and second 8b10b streams, respectively;
performing linear combining of the first and second 8b10b streams by a 2-bit combiner; and
converting the linear combination of every two bits received from the combiner into a PAM4 symbol.
11. The method of claim 10, wherein the resultant stream of PAM4 symbols preserves the Power Spectral Density (PSD) of the standard 8b10b non-return-to-zero stream, which enables band separation between downlink and uplink channels of a transceiver implementing the method.
12. The method of claim 10, wherein separation from the original byte stream is performed such that odd bits of the original byte stream are forwarded to the first 8b10b encoder and even bits of the original byte stream are forwarded to the second 8b10b encoder.
13. The method of claim 10, wherein separation from the original byte stream is performed such that two consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next two consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders.
14. The method of claim 10, wherein four consecutive bits of the original byte stream are forwarded to the first 8b10b encoder, the next four consecutive bits of the original byte stream are forwarded to the second 8b10b encoder, and so on, thereby flipping the original byte stream between the first and second 8b10b encoders.
15. A transmitter, comprising:
first, second and third 8b10b encoders configured to receive first, second and third streams separated from an original byte stream; the first, second and third 8b10b encoders are configured to output first, second and third 8b10b streams, respectively;
a 3-bit combiner configured to perform linear combining of the first, second and third 8b10b streams; and
an 8-level pulse amplitude modulation encoder (PAM8 encoder) configured to convert a linear combination of every three bits received from the 3-bit combiner into PAM8 symbols.
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| EP4270887A1 (en) | 2022-04-25 | 2023-11-01 | Samsung Electronics Co., Ltd. | Transmitter and receiver for 3-level pulse amplitude modulation signaling and system including the same |
| US20240097877A1 (en) * | 2022-09-16 | 2024-03-21 | Apple Inc. | Encoding and Decoding for PAM Transmitter and Receiver |
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