CN112825558B

CN112825558B - Encoding method, decoding method and device

Info

Publication number: CN112825558B
Application number: CN201911147234.8A
Authority: CN
Inventors: 何玉杰; 李莹; 涂建平
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2019-11-20
Filing date: 2019-11-20
Publication date: 2022-11-18
Anticipated expiration: 2039-11-20
Also published as: CN112825558A

Abstract

The embodiment of the application discloses an encoding method, a decoding method and equipment, which are used for reducing the error rate so as to ensure the system performance when external noise is large. The encoding method of the embodiment of the application comprises the following steps: firstly, generating K second bit blocks with preset length according to a first bit block, wherein the bit of the first bit block is filled with first effective information, the bit of each second bit block is filled with a group of second effective information, K groups of second effective information corresponding to the K second bit blocks form the first effective information, and in addition, each second bit block is also filled with redundant information; then, coding the K second bit blocks respectively to obtain K code words, wherein any code word in the K code words comprises bit information in one second bit block and check information corresponding to the bit information; and finally, modulating the K code words and then transmitting the modulated K code words. Since there is a large amount of redundant information in each of the K codewords, the error rate can be reduced.

Description

Encoding method, decoding method and device

Technical Field

The embodiment of the application relates to the technical field of communication, in particular to an encoding method, a decoding method and equipment.

Background

With the development of communication technology, the network standard of ethernet is continuously updated, and the target bearing rate is correspondingly continuously improved.

Existing network standards define coding schemes that allow a single cable of a particular wire length to achieve a target bearer rate. For example, one network standard defines a coding scheme for 100m single cables to 5Gbps with background noise of no more than-150 dBm/Hz; another network standard defines a coding scheme for 100m single cables to reach 10Gbps with background noise of no more than-150 dBm/Hz. Regardless of the network standard, the coding scheme includes: after receiving the data block, the physical coding PCS sublayer constructs a bit block with a length corresponding to a coding scheme according to the data block, and then codes the bit block and transmits the coded bit block.

However, the encoding method is only suitable for a single cable with a certain background noise, and when electromagnetic compatibility EMC interference exists outside or crosstalk occurs between cables due to binding of multiple cables, the background noise is increased, and at this time, if a target bearing rate is to be maintained, the bit error rate is increased, and the system performance is reduced.

A method is needed to reduce the bit error rate to guarantee the system performance when the external noise is large.

Disclosure of Invention

The embodiment of the application provides an encoding method, a decoding method and equipment, which are used for reducing the bit error rate so as to ensure the system performance when external noise is large.

A first aspect of an embodiment of the present application provides an encoding method, including:

at a sending end, a PCS sublayer generates K second bit blocks with preset length according to a first bit block, bit positions of the first bit block are filled with first effective information, bit positions of each second bit block are filled with redundant information and a group of second effective information, K groups of second effective information corresponding to the K second bit blocks form the first effective information, wherein K is an integer greater than 1;

then the PCS sublayer encodes the K second bit blocks respectively to obtain K code words, wherein any one code word in the K code words comprises bit information in one second bit block and check information corresponding to the bit information, and the check information is used for checking the bit information;

and finally, modulating the K code words and sending the modulated K code words to a receiving end.

In the embodiment of the present application, there are more redundant information in the K code words, and since the redundant information can be used for error correction in the decoding process, the embodiment of the present application can use more redundant information to correct the second valid information, thereby reducing the error rate and increasing the coding benefit, so as to ensure the system performance when the external noise is large.

Based on the first aspect, an embodiment of the present application provides a first implementation manner of the first aspect, where generating K second bit blocks with preset lengths according to the first bit block includes:

dividing the first effective information in the first bit block into K groups of second effective information according to a preset grouping mode;

and adding redundant information corresponding to each group of second effective information to generate a second bit block with a preset length, wherein the preset length can be determined according to a coding scheme adopted by coding.

This embodiment provides a possible solution for generating K second bit blocks, each of which contains redundant information that can be used for error correction of the second useful information.

Based on the first aspect, an embodiment of the present application provides a second implementation manner of the first aspect, where the first valid information includes one or more of data information, auxiliary information, and control information.

In this embodiment, the content of the auxiliary information may be set according to actual needs.

Based on the first aspect, or the first implementation manner of the first aspect, or the second implementation manner of the first aspect, an embodiment of the present application provides a third implementation manner of the first aspect, where modulating and transmitting the K codewords includes:

firstly, generating a third bit block according to the K code words, wherein the third bit block comprises effective information and check information in the K code words but does not comprise redundant information in the K code words;

and then the third bit block is modulated and transmitted.

In this embodiment, the third bit block does not contain redundant information, and the length of the third bit block can be shortened to accommodate modulation needs.

Based on the third implementation manner of the first aspect, an example of the present application provides a fourth implementation manner of the first aspect, and at least a part of bits in the third bit block are filled with random information.

Random information is added in the third bit block, the length of the third bit block can be adjusted to adapt to the modulation requirement, and the random information can play a role in adjusting the power spectral density PSD.

Based on the third implementation manner of the first aspect or the fourth implementation manner of the first aspect, an embodiment of the present application provides a fifth implementation manner of the first aspect, where modulating and transmitting the third bit block includes: and modulating the third bit block into a PAM symbol by adopting a pulse amplitude PAM modulation mode and transmitting the PAM symbol on the cable.

The third bit block is modulated in various modes, and the embodiment adopts a PAM mode for modulation, so that the control is simple, the efficiency is high, and a good harmonic elimination effect can be achieved.

A second aspect of the embodiments of the present application provides a decoding method, including:

a receiving end receives modulated data sent by a cable, and then demodulates the modulated data to obtain K code words, wherein the information in any one of the K code words corresponds to the bit information in one second bit block and the check information corresponding to the bit information;

the PCS sublayer of the receiving end respectively decodes the K code words to obtain K second bit blocks with preset lengths, wherein the bit of each second bit block comprises redundant information and a group of second effective information, and K groups of second effective information corresponding to the K second bit blocks form first effective information, wherein K is an integer greater than 1;

and finally, the PCS sublayer determines a first bit block for generating K second bit blocks, and the bit of the first bit block is filled with first effective information.

In the embodiment of the application, more redundant information is contained in the K code words, so that more redundant information can be used for correcting the second effective information in the decoding process, the error rate can be reduced, and the coding benefit can be increased so as to ensure the system performance when the external noise is larger.

Based on the second aspect, the present application provides a first implementation manner of the second aspect, and since the redundant information is known, determining to generate the first bit block of the K second bit blocks includes:

determining a group of second effective information in each second bit block according to the redundant information;

and the first valid information consists of K sets of second valid information, so that the first bit block can be determined according to the first valid information consisting of K sets of second valid information.

This embodiment provides a feasible solution for determining the first bit block according to the second bit block, and in particular, the first valid information of the first bit block is determined according to the redundant information, so that the first bit block can be determined.

Based on the second aspect, the present application provides a second implementation manner of the second aspect, and the first valid information includes one or more of data information, auxiliary information, and control information.

Based on the second aspect, or the first implementation manner of the second aspect, or the second implementation manner of the second aspect, an embodiment of the present application provides a third implementation manner of the second aspect, where the demodulating to obtain K codewords includes:

demodulating received modulated data to obtain a third bit block, wherein the third bit block comprises effective information and check information in K code words but does not comprise redundant information in the K code words;

the redundancy information is a preset specific value at the PCS sublayer so that the PCS sublayer can determine K codewords for generating the third bit block according to the redundancy information.

Based on the third implementation manner of the second aspect, this application provides a fourth implementation manner of the second aspect, and at least a part of bits in the third bit block are filled with random information.

Based on the third implementation manner of the second aspect or the fourth implementation manner of the second aspect, in an embodiment of the present application, the demodulating to obtain the third bit block includes:

and demodulating the PAM symbols transmitted on the cable into a third bit block by adopting a pulse amplitude PAM demodulation mode.

The third bit block is modulated in various modes, and the PAM mode is adopted at the transmitting end, so that the PAM mode is also adopted at the receiving end for demodulation, the control is simple, the efficiency is high, and a good harmonic wave elimination effect can be achieved.

A third aspect of an embodiment of the present application provides an encoding apparatus, including:

the generating unit is used for generating K second bit blocks with preset lengths according to the first bit block, the bit of the first bit block is filled with first effective information, the bit of each second bit block is filled with redundant information and a group of second effective information, and K groups of second effective information corresponding to the K second bit blocks form the first effective information, wherein K is an integer greater than 1;

the encoding unit is used for respectively encoding the K second bit blocks to obtain K code words, and any one of the K code words comprises bit information in one second bit block and check information corresponding to the bit information;

and the modulation unit is used for modulating the K code words and then transmitting the K code words.

Based on the third aspect, an embodiment of the present application provides a first implementation manner of the third aspect, where the generating unit is configured to:

dividing the first effective information in the first bit block into K groups of second effective information;

and adding redundant information corresponding to each group of second effective information to generate a second bit block with a preset length.

Based on the third aspect, an embodiment of the present application provides a second implementation manner of the third aspect, and the first valid information includes one or more of data information, auxiliary information, and control information.

Based on the third aspect, or the first implementation manner of the third aspect, or the second implementation manner of the third aspect, in an embodiment of the present application, a modulation unit is configured to:

generating a third bit block according to the K code words, wherein the third bit block comprises valid information and check information in the K code words but does not comprise redundant information in the K code words;

and modulating the third bit block and then transmitting.

Based on the third implementation manner of the third aspect, this application provides an example of a fourth implementation manner of the third aspect, where at least a part of bits in the third bit block are filled with random information.

Based on the third implementation manner of the third aspect or the fourth implementation manner of the third aspect, in an embodiment of the present application, a fifth implementation manner of the third aspect is provided, where the modulation unit is configured to: and modulating the third bit block into a PAM symbol by adopting a pulse amplitude PAM modulation mode and transmitting the PAM symbol on the cable.

A fourth aspect of embodiments of the present application provides a decoding apparatus, including:

the demodulation unit is used for demodulating K code words to obtain information in any one of the K code words, wherein the information in any one of the K code words corresponds to bit information in one second bit block and check information corresponding to the bit information;

the decoding unit is used for decoding the K code words respectively to obtain K second bit blocks with preset lengths, wherein the bit of each second bit block comprises redundant information and a group of second effective information, and K groups of second effective information corresponding to the K second bit blocks form first effective information, wherein K is an integer greater than 1;

a determining unit for determining a first bit block for generating the K second bit blocks, bits of the first bit block being filled with the first valid information.

Based on the fourth aspect, an embodiment of the present application provides a first implementation manner of the fourth aspect, where the determining unit is configured to:

and determining the first bit block according to the first effective information consisting of the K groups of second effective information.

Based on the fourth aspect, the present embodiments provide a second implementation manner of the fourth aspect, where the first valid information includes one or more of data information, auxiliary information, and control information.

Based on the fourth aspect, or the first implementation manner of the fourth aspect, or the second implementation manner of the fourth aspect, an embodiment of the present application provides a third implementation manner of the fourth aspect, and the demodulation unit is configured to:

demodulating to obtain a third bit block, wherein the third bit block comprises effective information and check information in the K code words but does not comprise redundant information in the K code words;

k codewords that generate a third block of bits are determined.

Based on the third implementation manner of the fourth aspect, this application provides a fourth implementation manner of the fourth aspect, and at least a part of bits in the third bit block are filled with random information.

Based on the third implementation manner of the fourth aspect or the fourth implementation manner of the fourth aspect, an embodiment of the present application provides a fifth implementation manner of the fourth aspect, where the demodulation unit is configured to: and demodulating the PAM symbol transmitted on the cable into a third bit block by adopting a pulse amplitude PAM demodulation mode.

A fifth aspect of embodiments of the present application provides an encoding apparatus, including: one or more processors and a memory, the memory storing computer-executable instructions executable on the processors, the encoding apparatus performing the method as described in the first aspect or any one of the embodiments of the first aspect as described above when the computer-executable instructions are executed by the processors.

A sixth aspect of embodiments of the present application provides a decoding apparatus, including: one or more processors and memory storing computer-executable instructions operable on the processors, the decoding apparatus performing the method according to any one of the embodiments of the second aspect or the first aspect when the computer-executable instructions are executed by the processors.

A seventh aspect of an embodiment of the present application provides an encoding system, including:

encoding means for performing a method as described in the first aspect above or in any one of the embodiments of the first aspect above; and

decoding means for performing the method according to any of the embodiments of the second aspect or the second aspect.

An eighth aspect of the embodiments of the present application provides a chip or a chip system, where the chip or the chip system includes at least one processor and a communication interface, where the communication interface and the at least one processor are interconnected by a line, and the at least one processor is configured to execute a computer program or instructions to perform an encoding method as described in any one of the first aspect or the first aspect above, or perform a decoding method as described in any one of the second aspect or the second aspect above.

The communication interface in the chip may be an input/output interface, a pin, a circuit, or the like.

Based on the eighth aspect, an embodiment of the present application further provides the first implementation manner of the eighth aspect, where the chip or the chip system described above in the embodiment of the present application further includes at least one memory, and the at least one memory stores instructions therein. The memory may be a storage unit inside the chip, such as a register, a cache, etc., or may be a storage unit of the chip (e.g., a read-only memory, a random access memory, etc.). A ninth aspect of an embodiment of the present application provides a computer storage medium for storing computer software instructions for the encoding apparatus or the decoding apparatus, which includes a program for executing the program designed for the encoding apparatus or the decoding apparatus.

The encoding apparatus may be as described in the aforementioned third aspect.

The decoding apparatus may be as described in the fourth aspect above.

A tenth aspect of embodiments of the present application provides a computer program product, where the computer program product includes computer software instructions, and the computer software instructions are loadable by a processor to implement a flow in an encoding method of any of the above first aspects or a flow in a decoding method of any of the above second aspects.

According to the technical scheme, the embodiment of the application has the following advantages:

generating K second bit blocks with preset length according to a first bit block, wherein bit positions of the first bit block are filled with first effective information, bit positions of each second bit block are filled with redundant information and a group of second effective information, K groups of second effective information corresponding to the K second bit blocks form the first effective information, and K is an integer greater than 1; then, coding the K second bit blocks respectively to obtain K code words, wherein any code word in the K code words comprises bit information in one second bit block and check information corresponding to the bit information; in the embodiment of the present application, the redundant information in each K codeword is more than that in 1 codeword in the existing encoding method, and since the redundant information can be used for error correction in the decoding process, the embodiment of the present application can reduce the error rate, increase the encoding yield, and ensure the system performance when the external noise is large.

Drawings

Fig. 1 is a schematic diagram of a seven-layer structure of network communication in an embodiment of the present application;

FIG. 2 is a schematic diagram of an embodiment of an encoding method in an embodiment of the present application;

FIG. 3 is a schematic diagram of another embodiment of an encoding method in the embodiment of the present application;

FIG. 4 is a schematic diagram of PAM modulation in the embodiment of the present application;

FIG. 5 is a schematic diagram illustrating an application of the encoding method in the embodiment of the present application;

FIG. 6 is a schematic diagram of an embodiment of a decoding method in an embodiment of the present application;

FIG. 7 is a schematic diagram of another embodiment of a decoding method in the embodiment of the present application;

FIG. 8 is a schematic diagram of an embodiment of an encoding apparatus in an embodiment of the present application;

FIG. 9 is a schematic diagram of an embodiment of a decoding apparatus in an embodiment of the present application;

FIG. 10 is a schematic diagram of an embodiment of an encoding apparatus in an embodiment of the present application;

fig. 11 is a schematic diagram of an embodiment of a decoding device in an embodiment of the present application.

Detailed Description

The embodiment of the application provides an encoding method, a decoding method and equipment, which are used for reducing the error rate so as to ensure the system performance when the external noise is large.

Referring to fig. 1, in an embodiment of the present application, a seven-layer structure diagram of network communication is shown, in an existing network standard, an open system interconnection divides network communication into 7 layers, which are a physical layer, a data link layer, a network layer, a transport layer, a session layer, a presentation layer, and an application layer. As shown in fig. 1, the physical layer specifically includes a reconciliation RS sublayer, an XGMII interface, a PCS sublayer, a physical medium access PMA sublayer, a physical medium dependent PMD sublayer, and a medium dependent interface.

Among them, the PCS sublayer is mainly used for encoding and decoding. At a sending end, after a PCS sublayer receives a data block through an XGMII interface, the data block is coded to obtain a code word, then the code word is modulated into data of other forms through a PMA sublayer and then is transmitted to the PMD sublayer, and finally the data of other forms are sent to a receiving end; correspondingly, the receiving end receives the data in other forms, the PMA sublayer demodulates the data in other forms after receiving the data in other forms from the PMD sublayer, then the PCS sublayer decodes the demodulated data, and finally transmits the decoded data block to the reconciliation sublayer through the XGMII interface.

In order to reduce the error rate, an error correction coding method is usually adopted for coding, that is, redundant information and valid information are coded together, so that a receiving end can correct errors of the valid information according to the redundant information in a decoding process to reduce the error rate. Therefore, the embodiment of the present application provides an encoding method and a decoding method, in the encoding process, the data block is subjected to multi-path encoding to improve the proportion of redundant information, and accordingly, in the decoding process, the data block is finally obtained through multi-path decoding, so as to achieve the purposes of reducing the error rate and increasing the encoding benefit, and ensure the system performance when the external noise is large.

For better understanding of the encoding method in the embodiment of the present application, please refer to fig. 2, which illustrates an embodiment of the encoding method in the embodiment of the present application. As shown in fig. 2, an embodiment of an encoding method provided in this application may be applied to a transmitting end, and includes:

and 101, generating K second bit blocks with preset length according to the first bit block.

It is understood that the sender needs to obtain the first bit block before performing operation 101. Specifically, in the process of sending data to the receiving end by the sending end, the PCS sublayer of the sending end receives a data block from the XGMII interface, and then generates a first bit block according to the data block by the PCS sublayer, where the method for generating the first bit block according to the data block includes multiple methods, which is not limited in this embodiment.

For example, the PCS sublayer receives two data blocks from the XGMII interface, combines the two data blocks to form a fourth bit block, and generates the first bit block from the fourth bit blocks. To improve security, the fourth bit block may be scrambled before the first bit block is generated. In order to facilitate data alignment at the receiving end, bits filled with control information may be added in the fourth bit block, and the number of bits filled with control information is not limited in the embodiment of the present application; according to actual needs, bits filled with auxiliary information may also be added in the first bit block, and the content of the auxiliary information and the number of the bits filled with the auxiliary information are not specifically limited in the embodiments of the present application.

Wherein the bits of the first bit block are filled with first useful information, as a realizable way, the first useful information may include one or more of data information, side information, and control information, wherein the data information refers to information in the data block.

For ease of understanding, the process of generating the first bit block is described below with a specific example. Assuming that two data blocks each include 32 bits, the 32 bits are filled with data information, the two data blocks are combined to form a fourth bit block, and meanwhile, 1 bit filled with control information is added to the fourth bit block, then the fourth bit block includes 65 bits, then the fourth bit block is scrambled, then a first bit block is generated based on the 25 scrambled fourth bit blocks, and 1 bit filled with auxiliary information is added to the first bit block, then the first bit block includes 1626 bits in total, and accordingly, the first valid information includes data information, control information, and auxiliary information.

After the first bit block is obtained, K second bit blocks need to be generated, and there are various methods for generating the K second bit blocks according to the first bit block, which are not limited in the embodiment of the present application; the preset lengths corresponding to any two second bit blocks in the K second bit blocks may be the same or different, that is, the number of bits included in any two second bit blocks may be the same or different; since the operation 102 is to encode the second bit block, the preset length corresponding to the second bit block should be adapted to the encoding scheme corresponding to the second bit block, for example, the encoding scheme corresponding to the second bit block needs to input a bit block containing 1723 bits, and then the preset length corresponding to the second bit block should be 1723 bits.

The bits of each second bit block are filled with redundant information and a set of second valid information, the content of the redundant information is not limited in the embodiment of the present application, for example, multiple 0 s in a binary system may be used as the redundant information; and K groups of second effective information corresponding to the K second bit blocks form the first effective information, and K is an integer greater than 1.

And 102, respectively coding the K second bit blocks to obtain K code words.

Wherein, any code word in the K code words comprises bit information in a second bit block and check information of the corresponding bit information.

The PCS sublayer may adopt a plurality of coding schemes for coding the second bit block, which is not limited in the embodiment of the present application, for example, the second bit block may be coded by adopting an LDPC coding scheme; the coding schemes corresponding to any two bit blocks in the K second bit blocks may be the same or different.

For example, assuming that K is 2, the two second bit blocks correspond to a first coding scheme and a second coding scheme, respectively, the first coding scheme being to code a bit block comprising 1723 bits as a bit block comprising 2048 bits, the second coding scheme being to code a bit block comprising 1823 bits as a bit block comprising 2058 bits; then the second block of bits encoded using the first coding scheme should have a length of 1723 bits, i.e. contain 1723 bits, corresponding to the resulting codeword should contain 2048 bits, the second block of bits encoded using the second coding scheme should have a length of 1823 bits, i.e. contain 1823 bits, corresponding to the resulting codeword should contain 2058 bits.

Any code word comprises the bit information and the check information in the second bit block, so that any code word comprises the redundant information in the second bit block, the second effective information can be corrected according to the redundant information in the decoding process, and the check information can be used for a receiving end to check the bit information in the second bit block.

103, modulating the K code words and then transmitting.

There are various ways to modulate the K codewords, which is not limited in the embodiment of the present application; after being modulated, the K code words are sent to a receiving end through a cable.

In the embodiment of the present application, K second bit blocks are generated according to a first bit block, then the K second bit blocks are respectively encoded to obtain K codewords, and finally the K codewords are modulated and transmitted, whereas in the existing encoding manner, one bit block is encoded to obtain 1 codeword, and then the 1 codeword is modulated and transmitted, since redundant information included in the K codewords is more than redundant information included in the 1 codeword, the embodiment of the present application can use more redundant information to perform error correction in the decoding process, thereby reducing the error rate, increasing the encoding benefit, and ensuring the system performance when the external noise is large.

One embodiment of the encoding method in the embodiment of the present application is described above, and another embodiment of the encoding method is described below. Referring to fig. 3, another embodiment of the encoding method in the embodiment of the present application is shown.

As shown in fig. 3, another embodiment of an encoding method provided in this application may be applied to a transmitting end, and includes:

the first valid information in the first bit block is divided into K groups of second valid information 201.

As can be seen from the foregoing embodiments, there are various methods for generating the second bit block, and an embodiment of the present application provides a method for generating the second bit block, that is, first effective information in the first bit block is grouped to obtain K groups of second effective information, where there are various methods for grouping, and this is not limited in this application.

For example, grouping may be performed in an evenly distributed manner, that is, the number of bits occupied by the K groups of second effective information is the same; specifically, assuming that the first valid information is represented as a binary sequence 00001111, where k is 2, the first four-bit binary system may be selected as a set of second valid information, and the last four-bit binary system may be selected as another set of second valid information, where the two sets of second valid information are 0000 and 1111, in addition, the second valid information may be selected from the first valid information according to other manners, for example, selecting binary systems corresponding to odd bits in the first valid information to form a set of second valid information, selecting binary systems corresponding to even bits in the first valid information to form another set of valid information, and then the two sets of second valid information are 0011 and 0011, respectively.

For another example, grouping may also be performed in a random distribution manner, that is, the number of bits occupied by the K groups of second effective information may be different; specifically, still assuming that the first valid information is represented by binary as 00001111 and k is 2, the first three-bit binary may be selected as one set of second valid information, and the last five-bit binary may be selected as another set of valid information, so that the two sets of second valid information are 000 and 01111, respectively; similarly, it is also possible to randomly select three bits of binary information in the first valid information as a group of second valid information, and select the remaining five bits of binary information as another group of valid information.

And 202, adding redundant information corresponding to each group of second effective information to generate a second bit block with a preset length.

According to the foregoing embodiment, the predetermined length of the second bit block corresponds to the coding scheme, and the number of bits occupied by the second valid information of different groups may be different, so that the number of bits filled with the redundant information is determined by the predetermined length and the number of bits filled with the second valid information.

For example, assuming that the preset lengths of the K second bit blocks are all 1000 bits, each group of second valid information occupies 600bits, and then the number of bits filled with redundant information in each second bit block is 400; assuming that K is 2, two groups of second valid information respectively occupy 500 bits and 600bits, and correspondingly, the number of bits filled with redundant information in the second bit block is 500 and 400, respectively.

And 203, respectively encoding the K second bit blocks to obtain K code words.

Operation 203 in the embodiment of the present application is the same as operation 102 in the previous embodiment, and can be understood by referring to the related description of operation 102 in the previous embodiment.

And 204, generating a third bit block according to the K code words, wherein the third bit block comprises valid information and check information in the K code words but does not comprise redundant information in the K code words.

There are various methods for generating the third bit block according to the K code words, which are not limited in this embodiment of the present application.

In the embodiment of the present application, the third bit block does not include redundant information, i.e., the redundant information is removed in the process of generating the third bit block. In an implementation, at least a portion of the bits in the third bit block are filled with random information, wherein the random information can function to adjust a Power Spectral Density (PSD).

The random information may be padded to the bits in the third bit block in a variety of ways. Specifically, since the third bit block does not include redundant information, the redundant information in the K code words can be directly replaced with random information; in order to adapt to the modulation requirement, the bit positions partially filled with redundant information can be removed, and the residual redundant information is replaced by random information; in order to adapt to the modulation requirement, the redundant information can be replaced by random information, and simultaneously, the bits filled with the random information are additionally added.

Wherein the random information may be a random binary sequence.

And 205, modulating the third bit block and then transmitting.

There are various modulation methods, which are not limited in this embodiment of the present application, for example, the third bit block may be modulated into PAM symbols by using a pulse amplitude PAM modulation method, and transmitted over the cable, where operation 205 may be performed by the PMA sublayer.

Referring to fig. 4, a principle schematic diagram of PAM modulation in the embodiment of the present application is shown, as shown in fig. 4, a signal a represents a sinusoidal analog signal, the signal a is modulated to become a pulse signal B, the pulse signal B specifically includes 18 pulses, a level order of the pulse signal B determines a PAM modulation order, which may be represented as PAMN, where N represents a modulation order, a level order corresponding to the pulse signal B in fig. 4 is 10 orders, and correspondingly, the PAM modulation order may be represented as PAM10.

In order to better understand the encoding method in the embodiment of the present application, the encoding method is further described in an application example. Referring to fig. 5, an exemplary application of the encoding method in the embodiment of the present application is shown. The application example comprises the following steps:

first, assuming that K is 2, in fig. 5, the fourth bit block includes 64 bits filled with data information and 1 bit filled with control information, the auxiliary information bit is 1 bit filled with auxiliary information, the first bit block is composed of 25 fourth bit blocks and auxiliary information bits, that is, the first bit block includes 1626 bits, the redundant information bits are bits filled with redundant information, and the LDPC encoding adopts a coding scheme in which a bit block including 1723 bits is encoded into a bit block including 2048 bits.

As shown in fig. 5, the first valid information in the first bit block is equally distributed into 2 second bit blocks, each second bit block contains 813 bits filled with the second valid information, and then 910 bits filled with redundant information are added to each second bit block to form a second bit block containing 1723 bits.

And then, respectively encoding the two second bit blocks by adopting the encoding scheme to obtain two code words containing 2048 bit positions, wherein the number of the bit positions filled with redundant information in each code word is still 910.

In order to meet the modulation requirement, 910 bits filled with redundant information in the two code words are replaced by 142 bits filled with random information to obtain two third bit blocks containing 1280 bits, and the two third bit blocks are combined into one bit block containing 2560 bits to be modulated, specifically, the PAM symbol is transmitted on the cable.

Specifically, in this application, 2560 bits are modulated onto 4 twisted pairs of a single cable, each twisted pair corresponds to 160 PAM16 symbols, in fig. 5, PAM16< n > is used to represent a specific symbol, where n is from 0 to 639, PAM16 indicates that the level order is 16, then one PAM16 symbol may be represented by 4 bits, and finally 640 PAM16 symbols are sent to the receiving end.

In the process of single cable transmission, the baud rate is set to 500baud, the time required for the single cable to transmit 640 PAM16 symbols is 160/500=0.32 μ s, and within 0.32 μ s, the data information actually transmitted by 4 twisted pairs is 64 × 25=1600bits, so the target carrying rate of the single cable is 1600bits/0.32 μ s =5Gbps.

The existing coding method is adopted to process the first bit block, and the process is as follows:

adding 97 bits filled with redundant information to the first bit block to form a bit block containing 1723 bits, then coding the bit block by adopting the same coding scheme to obtain a bit block containing 2048 bits, then replacing the redundant information on the 97 bits with random information, and finally modulating the bit block containing 2048 bits of random information onto 4 pairs of twisted wires in a single cable, wherein each pair of twisted wires corresponds to 128 PAM16 symbols. Then, the 512 PAM16 symbols are transmitted by using a baud rate of 400baud, so that the time required for transmitting the 512 PAM16 symbols by the single cable is 128/400=0.32 μ s, and within 0.32 μ s, data information actually transmitted by the 4 twisted pairs is 64 × 25=1600bits, so that the target carrying rate of the single cable is 1600/bits0.32 μ s =5Gbps.

Comparing the encoding method in the embodiment of the present application with the existing encoding method, it can be known that the embodiment of the present application can ensure that the target bearing rate is the same as the target bearing rate of a single cable, and meanwhile, in the embodiment of the present application, 2 code words obtained by encoding include 1820 code words filled with redundant information, and in the existing encoding method, the number of the bits filled with redundant information is only 97 in 1 code word obtained by encoding and including 2048 bits, so that it can be seen that the encoding method in the embodiment of the present application enables the redundant information used for error correction to be far more than the redundant information available in the existing encoding method in the decoding process, so the embodiment of the present application can reduce the error rate and increase the encoding yield.

It should be noted that the encoding method and the decoding method in the embodiments of the present application may be applied to any scenario that requires ensuring a target rate and reducing a bit error rate, for example, may be applied to vehicle-mounted communication.

The above is a specific description of the encoding method, and the decoding method corresponds to the encoding method, and the decoding method is described below. Referring to fig. 6, a schematic diagram of an embodiment of a decoding method in the embodiment of the present application is shown.

As shown in fig. 6, an embodiment of a decoding method provided in this application may be applied to a receiving end, and includes:

and 301, demodulating to obtain K code words.

The transmitting end modulates the K code words into data in other forms and transmits the data through cables, and correspondingly, the receiving end receives the data in other forms and demodulates the data in other forms to obtain the K code words.

It should be noted that, information in any one of the K codewords corresponds to bit information in a second bit block and check information of corresponding bit information, for example, information in any one codeword may be information obtained by hard decision or soft decision of a noisy pulse signal, when information in any one codeword is information obtained by hard decision of a noisy pulse signal, the information is check information of bit information in a second bit block and corresponding bit information, and when information in any one codeword is information obtained by soft decision of a noisy pulse signal, the information may be converted into check information of bit information in a second bit block and corresponding bit information.

Since there may be a delay in the transmission of the other form of data, the receiving end may align the other form of data after receiving the other form of data.

Wherein demodulation is the inverse of modulation, so the manner of demodulation corresponds to the manner of modulation.

And 302, decoding the K code words respectively to obtain K second bit blocks with preset lengths.

It can be understood that the decoding scheme of the receiving-end PCS sublayer corresponds to the coding scheme of the transmitting-end PCS sublayer, and the decoding schemes corresponding to any two of the K codewords may be the same or different.

Assuming that K is 2, the two second codewords correspond to a first decoding scheme of decoding a block of bits including 2048 bits into a block of bits including 1723 bits and a second decoding scheme of decoding a block of bits including 2058 bits into a block of bits including 1823 bits, respectively; then the second block of bits decoded using the first decoding scheme comprises 1723 bits and the second block of bits decoded using the second decoding scheme comprises 1823 bits.

The bits of each second bit block contain redundant information and a group of second effective information, the redundant information is the same as the redundant information in the encoding process, and can also be represented by a plurality of 0 in binary, and K groups of second effective information corresponding to K second bit blocks form the first effective information, wherein K is an integer greater than 1.

The check information in the codeword can be used to check the bit information in the second bit block; in addition, any code word contains the bit information in the second bit block, so that any code word contains redundant information in the second bit block, and the second effective information can be corrected according to the redundant information in the decoding process.

303, determining to generate a first bit block of the K second bit blocks, bits of the first bit block being filled with the first valid information.

As one implementation, the first valid information includes one or more of data information, side information, and control information.

The process of determining the first bit block by the PCS sublayer at the receiving end is the inverse process of generating the second bit block by the PCS sublayer at the transmitting end according to the first bit block, which is not described in this embodiment of the present application.

After the first bit block is obtained, the PCS sublayer will continue to determine the fourth bit block that generates the first bit block, then determine two data blocks according to the fourth bit block, and finally transmit the two data blocks through the XGMII interface.

It is understood that, during the encoding process, if bits filled with auxiliary information are added to the first bit block, the bits filled with auxiliary information may be known at the PCS sublayer at the receiving end, so that the PCS sublayer at the receiving end may determine the fourth bit block according to the bits filled with auxiliary information and the first bit block; in the encoding process, if bits filled with control information are added in the fourth bit block, the PCS sublayer at the receiving end of the bits filled with control information may also be known, so that the PCS sublayer at the receiving end may determine two data blocks according to the bits filled with control information and the fourth bit block; in the encoding process, if the fourth bit block is scrambled before the first bit block is generated, the PCS sublayer at the receiving end determines the fourth bit block according to the first bit block and then descrambles the fourth bit block.

In the embodiment of the present application, K code words are obtained by demodulation, then K code words are decoded respectively to obtain K second bit blocks, and then a first bit block is determined according to the K second bit blocks, whereas in the existing decoding manner, 1 code word is obtained by demodulation, and then the code word is decoded to obtain one bit block, and since the redundant information included in the K code words is more than the redundant information included in the 1 code word, more redundant information can be used for error correction in the decoding process, so that the error rate can be reduced, and the coding benefit can be increased to ensure the system performance when the external noise is large.

One embodiment of the decoding method in the embodiment of the present application is described above, and another embodiment of the decoding method is described below. Referring to fig. 7, another embodiment of a decoding method in the embodiment of the present application is shown.

As shown in fig. 7, another embodiment of a decoding method provided in this application may be applied to a PCS sublayer at a receiving end, and includes:

and 401, demodulating to obtain a third bit block.

The demodulation method corresponds to the modulation method, and if the pulse amplitude PAM modulation scheme is adopted to modulate the third bit block into a PAM symbol for transmission on the cable, in this embodiment of the application, the pulse amplitude PAM demodulation scheme may be adopted to demodulate the PAM symbol transmitted on the cable into the third bit block, where the PAM modulation scheme has been introduced in operation 205, and the PAM demodulation scheme is an inverse process of the PAM modulation scheme, which may be specifically understood with reference to operation 205, where operation 401 may be performed by a PMA sublayer.

And the third bit block comprises valid information and check information in the K code words but does not comprise redundant information in the K code words.

At 402, K codewords for generating a third block of bits are determined.

The process of determining the K code words is an inverse process of generating a third bit block according to the K code words, which is not described herein any more in the embodiments of the present application, and since the redundant information is removed in the process of generating the third bit block, the redundant information needs to be added in the process of determining the K code words. In an implementation manner, at least a part of bits in the third bit block is filled with random information, and the random information may be a random binary sequence, which can play a role in adjusting the PSD; accordingly, the random information needs to be discarded in the process of determining K codewords.

The method of rejecting random information is the inverse of filling random information in bits during the encoding process. Specifically, if the redundant information in the K code words is directly replaced with the random information in the encoding process, the random information in the K code words may be directly replaced with the redundant information in operation 402; if part of the bits filled with the redundant information are removed in the encoding process, and the remaining redundant information is replaced with random information, the random information can be replaced with the redundant information in operation 402, and part of the bits filled with the redundant information is additionally added; if the redundant information is replaced with the random information during the encoding process and the bits filled with the random information are additionally added, the additionally added bits filled with the random information are removed in operation 402, and then the remaining random information is replaced with the redundant information.

And 403, decoding the K code words respectively to obtain K second bit blocks with preset lengths.

Operation 403 in the present embodiment is the same as operation 302 in the previous embodiment, and can be understood by referring to the related description of operation 302 in the previous embodiment.

A set of second valid information in each second bit block is determined 404 based on the redundant information.

Since the bits of the second bit block are filled with redundant information and a set of second valid information, which is known at the PCS sublayer at the receiving end, the set of second valid information in each second bit block can be determined from the redundant information.

The first bit block is determined 405 based on the first valid information consisting of K sets of second valid information.

The process of forming the first useful information from the K sets of the second useful information is the reverse process of dividing the first useful information into the K sets of the second useful information.

Specifically, if the first valid information is represented as a binary sequence 00001111, where k is 2, the first four-bit binary system is selected as a set of second valid information during the encoding process, and the second four-bit binary system is selected as another set of valid information, so as to obtain two sets of second valid information 0000 and 1111, then in operation 405, a set of second valid information 0000 is used as the first four bits of the first valid information, and another set of second valid information 1111 is used as the second four bits of the first valid information, and the first valid information is obtained by combining the two sets of second valid information 0000.

Similarly, if the binary bits corresponding to the odd bits in the first valid information are selected to form a group of second valid information, and the binary bits corresponding to the even bits in the first valid information are selected to form another group of valid information, so as to obtain two groups of second valid information 0011 and 0011, in operation 405, the group of second valid information 0011 is respectively used as the odd bits of the first valid information, and the other group of second valid information 0011 is respectively used as the even bits of the first valid information, so as to obtain the first valid information by combining.

Similarly, if the first three bits binary system is selected as a group of second valid information and the last five bits binary system is selected as another group of valid information to obtain two groups of second valid information 000 and 01111 during the encoding process, then in operation 405, the first three bits of the first valid information are selected as one group of second valid information 000, and the last five bits of the first valid information are selected as another group of second valid information 01111, and the first valid information is obtained by combining the first three bits of the first valid information and the second valid information 01111.

Corresponding to the application example shown in fig. 5, the PCS sublayer at the receiving end receives 640 PAM symbols on 4 twisted pairs in a single cable, and then demodulates the 640 PAM symbols into a bit block containing 2560 bits; as can be seen from fig. 5, the positions of PAM16<0>, PAM16<1>, PAM16<2> and PAM16<3> on the 4 twisted pairs are aligned, but when the PCS sublayer at the receiving end receives the 640 PAM symbols, since delay may cause the reception times of PAM16<0> and PAM16<1>, PAM16<2> and PAM16<3> to be different, that is, PAM16<1>, PAM16<2> and PAM16<3> are aligned, and PAM16<0> is aligned with PAM16<5>, PAM16<6> and PAM16<7>, the PAM symbols on the 4 twisted pairs may be aligned before demodulation.

Then, 2 third bit blocks are determined according to the bit block containing 2560 bits, then, code words corresponding to the 2 third bit blocks are determined, then, the 2 code words are decoded respectively to obtain 2 second bit blocks, and finally, the first bit block is determined according to the 2 second bit blocks.

The encoding apparatus and the decoding apparatus will be described below.

Referring to fig. 8, an embodiment of an encoding apparatus in an embodiment of the present application is shown in fig. 8, and as shown in fig. 8, an embodiment of an encoding apparatus provided in this application is applied to a transmitting end, and includes:

a generating unit 501, configured to generate K second bit blocks with preset lengths according to a first bit block, where bits of the first bit block are filled with first valid information, bits of each second bit block include redundant information and a set of second valid information, and K sets of second valid information corresponding to the K second bit blocks constitute the first valid information, where K is an integer greater than 1;

the encoding unit 502 is configured to encode the K second bit blocks respectively to obtain K code words, where any one of the K code words includes bit information in one second bit block and check information corresponding to the bit information;

a modulating unit 503, configured to modulate the K code words and then transmit the K code words.

In another embodiment of the encoding apparatus provided in the embodiment of the present application, the generating unit 501 is configured to:

In another embodiment of the encoding apparatus provided in the embodiment of the present application, the first valid information includes one or more of data information, auxiliary information, and control information.

In another embodiment of the encoding apparatus provided in the embodiment of the present application, the modulation unit 503 is configured to:

and modulating the third bit block and then transmitting.

In another embodiment of the encoding apparatus provided in the embodiment of the present application, at least a part of bits in the third bit block is filled with random information.

In another embodiment of the encoding apparatus provided in the embodiment of the present application, the modulation unit 503 is configured to: and modulating the third bit block into a PAM symbol by adopting a pulse amplitude PAM modulation mode and transmitting the PAM symbol on the cable.

Referring to fig. 9, a schematic diagram of an embodiment of a decoding apparatus in an embodiment of the present application is shown in fig. 9, and an embodiment of the decoding apparatus provided in the present application is applied to a receiving end, and includes:

a demodulating unit 601, configured to demodulate to obtain K code words, where any code word in the K code words includes bit information in a second bit block and check information corresponding to the bit information;

a decoding unit 602, configured to decode the K codewords respectively to obtain K second bit blocks with preset lengths, where a bit of each second bit block is filled with redundant information and a set of second valid information, and K sets of second valid information corresponding to the K second bit blocks form first valid information, where K is an integer greater than 1;

a determining unit 603 configured to determine a first bit block for generating the K second bit blocks, bits of the first bit block being filled with the first valid information.

In another embodiment of the decoding apparatus provided in the embodiment of the present application, the determining unit 603 is configured to:

In another embodiment of the decoding apparatus provided in the embodiment of the present application, the first valid information includes one or more of data information, side information, and control information.

In another embodiment of the decoding apparatus provided in the embodiment of the present application, the demodulation unit 601 is configured to:

k codewords that generate a third block of bits are determined.

In another embodiment of the decoding apparatus provided in the embodiment of the present application, at least a part of bits in the third bit block is filled with random information.

In another embodiment of the decoding apparatus provided in the embodiment of the present application, the demodulation unit 601 is configured to: and demodulating the PAM symbol transmitted on the cable into a third bit block by adopting a pulse amplitude PAM demodulation mode.

Referring to fig. 10, an embodiment of an encoding apparatus in the embodiment of the present application may include one or more processors 701, a memory 702, and a communication interface 703.

The memory 702 may be transient storage or persistent storage. Still further, the processor 701 may be configured to communicate with the memory 702 to execute a series of instruction operations in the memory 702 on the transmitting side.

In this embodiment, the processor 701 may perform the operations performed by the transmitting-end PCS sublayer in the embodiments shown in fig. 2 to fig. 3, which are not described herein again.

In this embodiment, the specific functional block division in the processor 701 may be similar to the functional block division manner of the generating unit, the encoding unit, the modulating unit, and the like described in fig. 8, and is not described herein again.

Referring to fig. 11, an embodiment of a decoding apparatus in the embodiment of the present application may include one or more processors 801, a memory 802, and a communication interface 803.

The memory 802 may be transient storage or persistent storage. Still further, the processor 801 may be configured to communicate with the memory 802 to execute a series of instruction operations in the memory 802 on the receiving side.

In this embodiment, the processor 801 may perform the operations performed by the receiving-end PCS sublayer in the embodiments shown in fig. 6 to fig. 7, which are not described herein again.

In this embodiment, the specific functional block division in the processor 801 may be similar to the functional block division manner of the units such as the demodulation unit, the decoding unit, and the determination unit described in fig. 9, and is not described herein again.

An embodiment of the present application further provides an encoding system, including:

encoding means for performing the operations performed by the PCS sublayer as in the embodiments of fig. 2 and 3 described above; and

decoding means for performing the operations performed by the PCS sublayer as in the embodiments shown in fig. 6 and 7 above.

The present invention also provides a computer storage medium for storing computer software instructions for the encoding apparatus or the decoding apparatus, which includes a program designed for executing the encoding apparatus or the decoding apparatus.

The encoding apparatus may be as described in the foregoing description of fig. 8.

The decoding apparatus may be as described in the foregoing description of fig. 9.

An embodiment of the present application further provides a chip or a chip system, where the chip or the chip system includes at least one processor and a communication interface, the communication interface and the at least one processor are interconnected by a circuit, and the at least one processor is configured to run a computer program or an instruction to execute operations executed by the encoding apparatus in the embodiment illustrated in fig. 8 and the decoding apparatus in the embodiment illustrated in fig. 9, which are not described herein again in detail.

The embodiments of the present application further provide a first implementation manner of a chip or a chip system, where the chip or the chip system described above in the present application further includes at least one memory, and the at least one memory stores instructions therein. The memory may be a storage unit inside the chip, such as a register, a cache, etc., or may be a storage unit of the chip (e.g., a read-only memory, a random access memory, etc.). Embodiments of the present application further provide a computer program product, which includes computer software instructions that can be loaded by a processor to implement the processes of the methods in fig. 2, fig. 3, fig. 6, and fig. 7.

It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the above-described systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.

In the several embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the above-described apparatus embodiments are merely illustrative, and for example, the division of the units is only one type of logical functional division, and other divisions may be realized in practice, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection through some interfaces, devices or units, and may be in an electrical, mechanical or other form.

The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.

In addition, functional units in the embodiments of the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit. The integrated unit can be realized in a form of hardware, and can also be realized in a form of a software functional unit.

The integrated unit, if implemented in the form of a software functional unit and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be substantially implemented or contributed to by the prior art, or all or part of the technical solution may be embodied in a software product, which is stored in a storage medium and includes instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.

Claims

1. A method of encoding, comprising:

generating K second bit blocks with preset length according to a first bit block, wherein bits of the first bit block are filled with first effective information, bits of each second bit block are filled with redundant information and a group of second effective information, and K groups of second effective information corresponding to the K second bit blocks form the first effective information, wherein K is an integer greater than 1;

respectively encoding the K second bit blocks to obtain K code words, wherein any one code word in the K code words comprises bit information in one second bit block and check information corresponding to the bit information;

and modulating the K code words and then transmitting.

2. The method of claim 1, wherein generating K second bit blocks of preset length from the first bit block comprises:

dividing the first valid information in the first bit block into K groups of second valid information;

and adding redundant information corresponding to each group of the second effective information to generate a second bit block with a preset length.

3. The method of claim 1,

the first valid information includes one or more of data information, auxiliary information, and control information.

4. The method according to any one of claims 1 to 3, wherein the modulating the K codewords and then transmitting the modulated K codewords comprises:

and modulating the third bit block and then transmitting.

5. The method of claim 4, wherein at least a portion of the bits in the third bit block are filled with random information.

6. The method of claim 4, wherein the modulating the third bit block for transmission comprises: and modulating the third bit block into a PAM symbol by adopting a pulse amplitude PAM modulation mode and transmitting the PAM symbol on a cable.

7. A method of decoding, comprising:

demodulating to obtain K code words, wherein information in any one code word in the K code words corresponds to bit information in a second bit block and check information corresponding to the bit information;

decoding the K code words respectively to obtain K second bit blocks with preset lengths, wherein the bit of each second bit block comprises redundant information and a group of second effective information, and K groups of second effective information corresponding to the K second bit blocks form first effective information, wherein K is an integer greater than 1;

determining a first bit block generating the K second bit blocks, wherein bits of the first bit block are filled with first effective information.

8. The method of claim 7, wherein the determining to generate a first bit block of the K second bit blocks comprises:

determining a group of the second effective information in each second bit block according to the redundant information;

and determining a first bit block according to the first effective information consisting of the K groups of the second effective information.

9. The method of claim 7, wherein the first valid information comprises one or more of data information, side information, and control information.

10. The method according to any of claims 7 to 9, wherein the demodulating K codewords comprises:

demodulating to obtain a third bit block, wherein the third bit block comprises valid information and check information in the K code words, but does not comprise redundant information in the K code words;

k codewords that generate a third block of bits are determined.

11. The method of claim 10, wherein at least a portion of the bits in the third bit block are filled with random information.

12. The method of claim 10, wherein the demodulating into the third bit block comprises:

and demodulating the PAM symbol transmitted on the cable into the third bit block by adopting a pulse amplitude PAM demodulation mode.

13. An encoding apparatus, comprising:

a generating unit, configured to generate K second bit blocks with preset lengths according to a first bit block, where bits of the first bit block are filled with first valid information, bits of each second bit block are filled with redundant information and a set of second valid information, and K sets of second valid information corresponding to the K second bit blocks constitute the first valid information, where K is an integer greater than 1;

the encoding unit is configured to encode the K second bit blocks respectively to obtain K codewords, where any codeword in the K codewords includes bit information in one second bit block and check information corresponding to the bit information;

14. A decoding apparatus, comprising:

a demodulation unit, configured to demodulate to obtain K code words, where information in any code word of the K code words corresponds to bit information in a second bit block and check information corresponding to the bit information;

a decoding unit, configured to decode the K codewords respectively to obtain K second bit blocks with preset lengths, where a bit of each second bit block includes redundant information and a group of second valid information, and K groups of second valid information corresponding to the K second bit blocks form first valid information, where K is an integer greater than 1;

a determining unit, configured to determine a first bit block for generating the K second bit blocks, where bits of the first bit block are filled with first valid information.

15. An encoding device, characterized by comprising: at least one processor and a memory, the memory storing computer-executable instructions executable on the processor, the encoding device performing the method of any one of claims 1-6 when the computer-executable instructions are executed by the processor.

16. A decoding device, characterized by comprising: at least one processor and a memory storing computer-executable instructions executable on the processor, the decoding device performing the method of any one of the preceding claims 7-12 when the computer-executable instructions are executed by the processor.

17. An encoding system, characterized in that the encoding system comprises:

encoding means for performing the method of any one of claims 1-6; and

decoding means for performing the method of any one of claims 7-12.

18. A chip comprising at least one processor and a communication interface, the communication interface and the at least one processor interconnected by a line, the at least one processor being configured to execute computer instructions to perform the method of any one of claims 1-12.

19. A computer-readable storage medium storing one or more computer-executable instructions that, when executed by a processor, perform the method of any one of claims 1-12.