WO2020108771A1

WO2020108771A1 - Device and method for probabilitic constellation shaping

Info

Publication number: WO2020108771A1
Application number: PCT/EP2018/083149
Authority: WO
Inventors: Onurcan ISCAN; Wen Xu
Original assignee: Huawei Technologies Co., Ltd.
Priority date: 2018-11-30
Filing date: 2018-11-30
Publication date: 2020-06-04

Abstract

The present invention relates to the technical field of probabilistic constellation shaping, in particular in combination with polar coding. The invention accordingly proposes a device for probabilistic constellation shaping. In particular, the device is configured to: receive a first bit sequence including at least two sub-sequences; separately interleave each of the sub-sequences, form a second bit sequence including the at least two sub-sequences after interleaving; and map the second bit sequence to a plurality of symbols and thereby map at least one of the sub-sequences to one or more pre-defined bit-levels.

Description

DEVICE AND METHOD FOR PROBABILITIC CONSTELLATION SHAPING

TECHNICAL FIELD

The present invention relates to the technical field of probabilistic constellation shaping, in particular in combination with polar coding. The invention accordingly proposes a device for probabilistic constellation shaping. Further, the invention proposes a transmitter, which includes a polar encoder and the device for probabilistic constellation shaping. The invention is particularly concerned with enabling both interleaving and symbol mapping that is compatible with probabilistic shaping (PS) and polar coding.

BACKGROUND Capacity of a channel is the maximum rate at which information can be reliably transmitted to the destination. The channel capacity mainly depends on the characteristics of the channel (e.g., signal-to-noise ratio (SNR), multipath). However, the transmitter needs to adjust its transmission signal to obtain (or approach) this rate. In particular, the channel input symbols need to have a certain probability distribution. For example, the channel input symbols need to be Gaussian distributed to achieve the capacity of an Additive White Gaussian Noise (AWGN) channel. The loss due to utilizing non-optimal symbol distribution is called‘shaping loss’.

The shaping loss becomes significant especially with higher order modulation. A common approach for transmission with such higher order modulation is bit-interleaved coded modulation (BICM) and is shown in FIG. 7. Here, data is first encoded by a channel encoder to a codeword e , which is then interleaved by an interleaver to form the sequence /, and finally mapped to channel input symbols x by a symbol mapper. In many systems, binary channel codes are used, such that the codewords are binary sequences. In general, the distribution of l’s and 0’s in such a codeword is uniform. This causes also the channel input symbols to have a uniform distribution. Accordingly, a shaping loss is observed.

PS or probabilistically shaped coded modulation (PSCM) is a promising approach to combat this shaping loss. In PS schemes, codewords at the output of the channel encoder have certain properties, which results in non-uniform distribution of the channel input symbols after symbol mapping. Below two examples of PS approaches are described with respect to FIG. 8:

• A first approach to obtain such codewords is to use a distribution matcher (DM) or shaping encoder prior to the channel encoder. A DM converts the data sequence to a sequence with a target probability distribution. By using a systematic channel encoder, the generated codewords, or parts of them, also have a non-uniform distribution, and the desired distribution of the channel input symbols can be obtained after symbol mapping.

• In a second approach suitable for polar codes, a precoder (PC) is placed prior to the channel encoder, which results in the same effect as for the first approach. The difference compared to the first approach is that the channel encoder is not systematic and the PC is not a DM. Instead, the PC modifies the input of the channel encoder in such a way that the generated codewords have a desired distribution.

Both approaches rely on non-uniformly distributed sequences at the output of the channel encoder, which are then mapped to channel input symbols. To provide the channel input symbols with the desired non-uniform distribution, the codewords should be carefully processed by the interleaver and by the symbol mapper, respectively.

Note that the probability distributions of the sequences can be conditional probability distributions, e.g., the non-uniform distribution of the bits in a sequence can be conditioned on the bits in another predefined sequence. For example, the zth bit of a sequence can have the value 1 with probability p, when the /th bit of a predefined sequence is 1, i.e. the probability of the bits in the sequence may be conditioned on the values of the bits in another predefined sequence. This may be especially important, if a predefined sequence is used to scramble the output of the channel encoder, before the symbol mapper.

In general, conventional interleavers and symbol mappers are not designed considering the distribution of their inputs. Therefore, if a PS approach as in FIG. 8 is combined with a conventional interleaver or symbol mapper, which is not adjusted to this property of the codewords, the resulting channel input symbols will not have the desired property. Particularly, interleavers are conventionally designed in a way such that they shuffle their input as randomly as possible, such that undesired channel effects are averaged out.

For example, if the channel effects on the successive symbols are correlated (i.e. if the channel disturbs successive symbols in a similar way), the interleaver ensures that successive codeword bits are not mapped to successive channel input symbols, which improves the error correction performance. A random (or pseudo-random) interleaver ensures that each bit of the codeword experience the random and uncorrelated channel effects on average. However, such interleavers do not consider the distribution of the bits within the codewords. If a PS scheme is considered, the mapping between the codeword bits and the symbol mapper should not be arbitrary, since an interleaver before the symbol mapper will impact the distribution of the symbols after the symbol mapping.

For conventional PS, the interleaver is not considered in detail. Instead, usually either no interleaver is employed (i.e. the codeword bits are directly mapped to symbol mapper) like, or simple bit-mappers between codewords and symbol mappers are employed, which are purely used to obtain the desired distribution at the output, without benefiting from the useful effects of the interleavers. SUMMARY

In view of the above-mentioned disadvantages, the present invention aims to improve the conventional PS approaches. An objective is to provide a device that supports PS, particularly supports constellation shaping (i.e. PS of symbols). The device should be able to provide interleaving that is compatible with probabilistically shaped input data. The interleaving provided by the device should be such that the resulting channel input symbols, i.e. the data output by the device, have a desired probability distribution and are at the same time shuffled, particularly randomly enough that undesired channel effects can be averaged out. Accordingly, a goal of the invention is to define required properties of such a device including an interleaver suitable for PS, particularly also for polar codes. The device can, for instance, be compatible with a 5G-New Radio (NR) transmission chain with polar codes, such that the desired shaping gain is obtained. The objective is achieved by embodiments of the invention as provided in the enclosed independent claims. Advantageous implementations of the embodiments are further defined in the dependent claims.

In particular the present invention proposes a device that is configured to perform interleaving (i.e. includes an interleaver) and symbol mapping (i.e. includes a symbol mapper). The interleaver is particularly between e.g. an encoder, from which the device receives input data, and the symbol mapper. The device may perform an intra bit-level interleaving for certain bit-levels, where the distribution of the bits in that bit-level is preserved. The proposed interleaver of the device may be modulation dependent, i.e. depending on the choice of the modulation order (e.g. number of bit- levels), the interleaver may be different.

More generally, the interleaving is performed by the device considering the distribution of sub-sequences in an input sequence (received e.g. from the encoder). Alternatively, the interleaving is performed such by the device that at least one sub- sequence in an output sequence has a target probability distribution.

A first aspect of the invention provides a device for supporting probabilistic constellation shaping, configured to: receive a first bit sequence including at least two sub-sequences, separately interleave each of the sub-sequences, form a second bit sequence including the at least two sub-sequences after interleaving, map the second bit sequence to a plurality of symbols and thereby map at least one of the sub- sequences to one or more pre-defined bit- levels.

Thereby the symbols resulting from the mapping performed by the device of the first aspect can have a pre-defined target probability distribution. At the same time, interleaving is performed to preserve its advantageous effects. Accordingly, the device supports PS, particularly constellation shaping, and is able to provide interleaving compatible with the PS.

In an implementation form of the first aspect, the mapping of the second bit sequence is performed by a symbol mapper and wherein the forming of the second bit sequence depends on the structure of the symbol mapper. Thereby, the second bit sequence can be formed such that at least one of the sub-sequences is mapped to one or more pre-defined bit-levels, in particular when using common symbol mappers. In other words, the second bit sequence is arranged in a smart way such that it matches to a particular symbol mapper, in particular with a target symbol probability distribution.

There may be different implementations of the symbol mapper. To form the second bit sequence such that at least one of the at least two sub-sequences is entirely mapped by the symbol mapper to one or more pre-defined bit-levels, the interleaver may form the second bit sequence such that each of the symbols includes the same number of bits, and bits of different symbols and at same positions within each of the symbols define a bit-level.

In an implementation form of the first aspect, the at least one of the sub-sequences, which is mapped to the one or more pre-defined bit-levels, includes bits distributed according to a target probability distribution.

Accordingly, the device supports PS, and also the symbols will be distributed to a desired target probability distribution.

In an implementation form of the first aspect, the at least one of the sub-sequences, which is mapped to the one or more pre-defined bit-levels, includes bits distributed according to a non-uniform probability distribution.

Thus, also a non-uniform distribution of symbols can be achieved.

In an implementation form of the first aspect, at least two different sub-sequences, which are each mapped to one or more pre-defined bit-levels, include bits distributed according to different probability distributions.

For instance, one sub- sequence may have a uniform probability distribution, while the other sub-sequence has a non-uniform probability distribution, or both sub-sequences may have different non-uniform distributions. At least one of the sub- sequences may have a certain desired probability distribution. Thus, PS with high flexibility is provided. In an implementation form of the first aspect, the device is configured to map the at least one of the sub-sequences to two or more pre-defined bit-levels.

This may be advantageous, if pairs of bit- levels have similar properties.

In an implementation form of the first aspect, the plurality of symbols is a plurality of Quadrature Amplitude Modulation (QAM) symbols, and the two pre-defined bit-levels are the third bit-level and the fourth bit-level.

This is beneficial, if the symbol mapping is 16-QAM, 64-QAM, or 256-QAM in the 5G standard, since the third and fourth bit-levels distinguish between high-energy and low- energy symbols.

In an implementation form of the first aspect, the one or more pre-defined bit-levels determine for each of the plurality of symbols whether the symbol is a high-energy symbol or a low-energy symbol.

In an implementation form of the first aspect, the device is configured to generate a high- energy symbol with a lower probability than a low-energy symbol.

Accordingly, more energy efficient transmission is enabled.

In an implementation form of the first aspect, the device comprises a first interleaver connected in series to a second interleaver, wherein the second interleaver is configured to interleave the at least one of the sub-sequences, which is mapped to the one or more pre defined bit- levels, and the first interleaver is configured to interleave the at least one other sub-sequence.

The first interleaver may be a conventional channel interleaver, and the first and second interleaver form a serial shaping interleaver. Such a serial shaping interleaver is advantageous in the sense that it can be switched off to support backward compatibility. It does not change the structure of the conventional channel interleaver, and can be seen as an add-on to the existing transmitter chain. In an implementation form of the first aspect, the device comprises a first interleaver connected in parallel to a second interleaver, and a splitter configured to receive the first bit sequence and to direct the at least one of the sub-sequences, which is mapped to the one or more pre-defined bit-levels, to the second interleaver and the at least one other sub sequence to the first interleaver, and a combiner configured to form the second bit sequence by recombining the at least one of the sub- sequences and the at least one other sub sequence after interleaving.

The first interleaver may be a conventional channel interleaver, and the first and second interleaver form a parallel shaping interleaver. Such a parallel shaping interleaver has also advantages. First of all, two interleaving operations can be done in parallel such that no extra delay is introduced. Secondly, one can use existing interleavers for both conventional channel and shaping interleaving. For example, the 5G NR specifies the channel interleaver as a triangular interleaver with flexible length. One can use this triangular interleaver as both channel and shaping interleavers, such that the same hardware is used for both of them, reducing the cost for the storage on an extra interleaver.

In an implementation form of the first aspect, the device is configured to receive the first bit sequence from an encoder, in particular a channel encoder, e.g. a polar encoder, an LDPC encoder, a turbo encoder, a convolutional encoder.

In an implementation form of the first aspect, the encoder is configured to perform polar coding.

Thus, the device of the first aspect is compatible with polar coding.

In an implementation form of the first aspect, the first bit sequence is a probabilistically shaped bit sequence.

A second aspect of the invention provides a transmitter device for probabilistic constellation shaping, comprising: the device according to the first aspect or any of its implementation forms, and an encoder configured to perform polar coding to generate the first bit sequence and to provide it to the device. Thus, the transmitter of the second aspect enjoys the advantages and effects described above for the device of the first aspect and its implementation forms. The transmitter advantageously combines polar coding and PS while still applying interleaving.

A third aspect of the invention provides a method for supporting probabilistic constellation shaping, the method comprising: receiving a first bit sequence including at least two sub sequences, separately interleaving each of the sub- sequences, forming a second bit sequence including the at least two sub-sequences after interleaving, mapping the second bit sequence to a plurality of symbols and thereby mapping at least one of the sub sequences to one or more pre-defined bit- levels.

In an implementation form of the third aspect, the mapping of the second bit sequence is performed by a symbol mapper and wherein the forming of the second bit sequence depends on the structure of the symbol mapper.

In an implementation form of the third aspect, the at least one of the sub-sequences, which is mapped to the one or more pre-defined bit-levels, includes bits distributed according to a target probability distribution.

In an implementation form of the third aspect, the at least one of the sub-sequences, which is mapped to the one or more pre-defined bit-levels, includes bits distributed according to a non-uniform probability distribution.

In an implementation form of the third aspect, at least two different sub-sequences, which are each mapped to one or more pre-defined bit-levels, include bits distributed according to different probability distributions.

In an implementation form of the third aspect, the method comprises mapping the at least one of the sub-sequences to two or more pre-defined bit-levels.

In an implementation form of the third aspect, the plurality of symbols is a plurality of Quadrature Amplitude Modulation (QAM) symbols, and the two pre-defined bit-levels are the third bit-level and the fourth bit-level. In an implementation form of the third aspect, the one or more pre-defined bit-levels determine for each of the plurality of symbols whether the symbol is a high-energy symbol or a low-energy symbol.

In an implementation form of the third aspect, the method comprises generating a high- energy symbol with a lower probability than a low-energy symbol.

In an implementation form of the third aspect, the method uses a first interleaver connected in series to a second interleaver, wherein the second interleaver is configured to interleave the at least one of the sub-sequences, which is mapped to the one or more pre-defined bit- levels, and the first interleaver is configured to interleave the at least one other sub sequence.

In an implementation form of the third aspect, the method uses a first interleaver connected in parallel to a second interleaver, and a splitter configured to receive the first bit sequence and to direct the at least one of the sub- sequences, which is mapped to the one or more pre defined bit-levels, to the second interleaver and the at least one other sub-sequence to the first interleaver, and a combiner configured to form the second bit sequence by recombining the at least one of the sub-sequences and the at least one other sub-sequence after interleaving.

In an implementation form of the third aspect, the method comprises receiving the first bit sequence from an encoder.

In an implementation form of the third aspect, the method comprises that the encoder performs polar coding.

In an implementation form of the third aspect, the first bit sequence is a probabilistically shaped bit sequence.

The method of the third aspect and its implementation forms achieve the advantages and effects described above for the device of the first aspect and its respective implementation forms. It has to be noted that all devices, elements, units and means described in the present application could be implemented in the software or hardware elements or any kind of combination thereof. All steps which are performed by the various entities described in the present application as well as the functionalities described to be performed by the various entities are intended to mean that the respective entity is adapted to or configured to perform the respective steps and functionalities. Even if, in the following description of specific embodiments, a specific functionality or step to be performed by external entities is not reflected in the description of a specific detailed element of that entity which performs that specific step or functionality, it should be clear for a skilled person that these methods and functionalities can be implemented in respective software or hardware elements, or any kind of combination thereof.

BRIEF DESCRIPTION OF DRAWINGS

The above described aspects and implementation forms of the present invention will be explained in the following description of specific embodiments in relation to the enclosed drawings, in which FIG. 1 shows a device according to an embodiment of the invention.

FIG. 2 shows a device according to an embodiment of the invention, which receives a sequence from an encoder configured to perform polar coding. FIG. 3 shows a device according to an embodiment of the invention, which receives a sequence from an encoder configured to perform polar coding with support for PS.

FIG. 4 shows a device according to an embodiment of the invention with two interleavers in series.

FIG. 5 shows a device according to an embodiment of the invention with two interleavers in parallel. FIG. 6 shows a method according to an embodiment of the invention.

FIG. 7 shows a conventional BICM transmitter. FIG. 8 shows a conventional transmitter with PS.

DETAILED DESCRIPTION OF EMBODIMENTS

FIG. 1 shows a device 100 according to an embodiment of the invention. In particular, the device 100 is configured to supporting probabilistic constellation shaping, particularly in combination with polar coding. To this end, the device 100 is configured to receive a first bit sequence 101 including at least two sub- sequences 102, 103. The first bit sequence 101 may be a probabilistically shaped bit sequence. The first bit sequence 101 may be received from a polar encoder. The first bit sequence 101 is also denoted with e.

The device 100 is configured to separately interleave each of the sub- sequences 102, 103, i.e. separately interleave at least a first sub-sequence 102 and a second sub-sequence 103. This results in at least an interleaved first subsequence 102’ and an interleaved second sub sequence 103’, i.e. at least two interleaved sub-sequences 102’, 103’. To this end, the device 100 may include an interleaver.

The device 100 is further configured to form a second bit sequence 104 including the at least two sub-sequences 102’, 103’ after interleaving, i.e. the at least two interleaved sub sequences 102’, 103’ resulting from separately interleaving the at least two sub-sequences 102, 103.

Then, the device 100 is configured to map the second bit sequence 104 to a plurality of symbols 105, and thereby map at least one of the sub- sequences 102, 103 to one or more pre-defined bit-levels 106. To this end, the device 100 may include a symbol mapper. The second bit sequence 104 is also denoted with /’. The plurality of symbols 105 is also denoted with x. Notably, since each bit of the at least one sub- sequence 102, 103 is mapped to the at least one pre-defined bit levels 106, it is identical to say that the at least one sub sequence 102’, 103’ after interleaving is mapped to this at least one pre-defined bit level 106, i.e. that at least one interleaved sub-sequence 102’, 103’ is mapped to the at least one pre-defined bit level 106.

FIG. 2 shows a device 100 according to an embodiment of the invention, which builds on the device shown in FIG. 1. Same elements in FIG. 1 and FIG. 2 share the same reference signs and function likewise. The device 100 receives the first input sequence 101 (including the sub-sequences 102 and 103) from an encoder 200, exemplarily an encoder 200 configured to perform polar coding 203, like a 5G NR polar coder. In fact, FIG. 2 shows thus in total a system providing a transmitter chain of 5G NR polar coding, wherein the device 100 replaces and takes over the role of a conventional channel interleaver and a conventional symbol mapper. Without loss of generality, the system shown in FIG. 2 with the device 100 according to an embodiment of the invention, may be described as follows:

The encoder 200 outputs the first sequence 101 (codeword e) of length E, which is interleaved, by an interleaver 201 of the device 100, to obtain the sequence/’ of the same length. The device 100 thereby reorders the elements in e to generate the sequence/’ i.e., e and/’ contain the same elements, such as data bits or symbols, in different orders. The sequence/’ is obviously the second sequence 104 (including the interleaved sub- sequences 102’ and 103’).

Then,/’ is mapped, by a symbol mapper 202 of the device 100, to symbols x of length E/M, i.e. to the plurality of symbols 105. The symbol mapper 202 may particularly be a deterministic function, which maps every M (successive) bits to one symbol 105. Such a symbol mapper 202 can be considered to provide a mapping with M bit- levels. That is, the bits at the indices c, c+M, c+2 M, c+3 M,... in/’ are mapped to the bit level c, where c can have values I,. .,M, and every M successive bits are mapped to one symbol. The symbol mapper 202 can also be such a symbol mapper 202, configured to map the second bit sequence 104 to the plurality of symbols 105, and thereby‘intelligently’ map at least one of the sub-sequences 102 and 103 to one or more pre-defined bit-levels 106.

Accordingly, the distribution of the symbols x is directly related to the distribution of the bits at each bit- level. If a PS method is used, e may contain multiple sub-sequences 102, 103, wherein each of the sub- sequences 102, 103 may have a different probability distribution, which should not be mapped to an arbitrary bit- level 106. Instead, should be mapped to the one or more pre-defined bit- levels 106 that causes the symbols x to have the target probability distribution. In other words, the interleaver 201 should be configured to consider the distribution of elements in x.

On the other hand, the task of the interleaver 201 is also to shuffle its inputs, in order to gain more robustness against certain channel impairments. Therefore, the following is particularly done in the device 100 according to an embodiment of the invention:

• First, the device 100 divides the first sequence 101 received from the encoder 200 into the non- overlapping at least two sub-sequences 102, 103, e.g. based on their probability distributions. The at least two sub-sequences 102, 103 can be obtained off-line depending on the encoding parameters.

• Then, the device 100 performs interleaving to each of these at least two sub sequences 102, 103 separately.

• Then, the device 100 recombines the obtained interleaved sub-sequences 102’, 103’ in such a way, that at least one of the sub- sequences 102, 103, potentially even each one of the sub- sequences 102, 103, are mapped to predefined bit- levels 106 of the symbols 105.

For an illustrative example, it may be assumed that the first sequence 101 consists of three different sub-sequences 102, 103 and 103a with different probability distributions, and it may also be assumed that the symbol mapper 202 has M= 4 different bit-levels, Then, the first sequence 101 may be divided into three sub-sequences 102, 103, 103a. Then each sub sequence 102, 103, 103a is separately interleaved. Then, e.g. the first interleaved sub sequence 102’ is mapped to the first bit-level, the second interleaved sub-sequence 103’ is mapped to the second bit- level, and the third interleaved sub-sequence 103a’ is mapped to the third and fourth bit-levels. Notably, the number of sub-sequences and the number of bit- levels may be different. Also notably, in many cases the pairs of bit- levels 106 have similar properties due to symmetry. Therefore, each sub-sequence 102, 103 may be mapped to at least two bit- levels 106.

The approach performed by the device 100 can be considered as being intra bit-level interleaving for certain bit-levels (e.g. bit-levels 1 and 2 in the above illustrative example) and/or inter bit-level interleaving for certain other bit-levels (e.g. bit-levels 3 and 4 in the above illustrative example). Notably, conventional interleavers for higher order modulation can be seen as inter bit- level interleavers. In the device 100 there are bit-levels interleaved locally.

In the device 100, the interleaver 201 particularly works in line with the target probability of the channel input symbols 105, and does not have any negative effect on the distribution. At the same time, by performing an intra bit-level interleaving, the desired properties of the interleaver 201 are maintained.

Two exemplary embodiments specifically related to polar codes, in particular 5G NR polar codes, are now described with respect to FIG. 2-5. A brief introduction to 5G New Radio polar codes is given, and how they may be extended to support PS. Then, two different interleaver designs suitable for the device 100 are shown.

Polar codes are recently developed error correction schemes that are now a part of the 5G New Radio standard. FIG. 2 shows - as already explained above - a block diagram of the transmitter chain of 5G NR polar coding with the device 100 according to an embodiment of the invention replacing a conventional channel interleaver.

Using a data sequence c’ (which can also include CRC bits) and frozen bits, a sequence u of length N may be generated in the encoder 200. This step is called bit-channel allocation. Then, the polarized sequence d=uG may be generated in the encoder 200 by performing a polar transform G on «. This sequence may be interleaved in the encoder 200 by the sub block interleaver for simple rate matching, and a bit-selection procedure may be applied by performing puncturing, shortening or repetition to obtain the sequence e. We can call the operations to produce e from c’ as encoding performed by the encoder 200. The encoded sequence e is then provided to the device 100, where it is interleaved and mapped to the symbols x. In particular, the sequence e is interleaved using interleaver 201 and the interleaved sequence/’ is to be mapped to the channel input symbols (i.e., QAM symbols) using symbol mapper 202.

The 5G NR polar codes can be extended to include PS, which is depicted in FIG. 3. FIG. 3 particularly shows a device 100 according to an embodiment of the invention, which is the same as the device 100 in FIG. 2. Here, however, PS is introduced by using a precoder (shaping bits insertion block 300 in FIG. 3 before the encoder 200), which processes the data sequence c’ before feeding to the bit-channel allocation block of the encoder 200. This block 300 basically generates additional bits s depending on the values of the data bits, which are then appended to the data bits. If those additional bits are selected carefully, the resulting sequence d after polar transform in the encoder 200 may contain at least one sub sequence (we call this sub-sequence S) that has a target probability distribution. The bits in this sub- sequence can be called‘shaped bits’, since they are distributed according to a target probability distribution, i.e., the probability of ones and zeros of the shaped bits is p and l-p, respectively, where p is a real number between 0 and 1. The value of p depend on the choice of s, i.e. on how s is generated.

As a result, with this approach a precoder may process the data bits such that after polar transform in the encoder 200, the codeword contains a sub-sequence of bits, which has a probability distribution defined by the real number p.

In order to provide also the channel input symbols x with a desired distribution, the bits in the sub- sequence S need to be mapped by the device 100 to the correct bit- levels 106 of the channel input symbols 105 (e.g. QAM symbols). One option is to place the shaped bits of the sub-sequence S in those bit-levels 106, which distinguish between high-energy and low- energy QAM symbols, particularly such that the probability of high-energy QAM symbols are lower than the probability of low-energy QAM symbols. This would reduce the average amount of energy used for transmission.

If, for example, as symbol mapper 202 in the device 100 a symbol mapper for 16-QAM, 64-QAM and 256-QAM in the 5G standard is considered, the third and fourth bit levels 106 are the bit-levels 106 that distinguish between high-energy and low-energy symbols 105. Therefore, it may be convenient to choose the parameters in a way such that the shaped bits are mapped to the third and fourth bit-levels, if a 5G NR symbol mapper is used in the device 100.

FIG. 5 shows a device 100 according to an embodiment of the invention that builds on the device 100 shown in FIG. 4. Same elements in FIG. 4 and FIG. 5 share the same reference signs and function likewise. The device 100 includes particularly a serial shaping interleaver 201. To this end, a shaping interleaver 201b may be provided after a conventional channel interleaver 201a. According to the specification of 5G NR, the blocks ‘sub-block interleaver’ and‘bit selection’ in the encoder 200 and the conventional channel interleaver, respectively, are well defined, i.e. they are deterministic functions. The additional shaping interleaver 201 may be configured to perform an interleaving operation, which ensures that the shaped bits are mapped to the correct bit-levels (e.g. third and fourth bit levels in this case) and the rest are left as they are. The relevant steps can be summarized as follows:

• Recall that the set of indices of d with shaped bits is called S. In this example, S is particularly the last N/(M/ 2) bits of d , wherein N is the length of d and M is the number of bit-levels 106 (also called as modulation order of 2^m-QAM modulation).

• Similarly, the set of indices in f corresponding to the target bit-levels 106 may be called B. Recall that each Mbit of/’ is mapped to a single QAM symbol 105, and the third and fourth bits of those M bits define B , if 5G NR is considered, i.e. B = { 3, 3+M, 3+2 M, 3+3 M,... }U{4, 4+ M, 4+2 M, 4+3 M,... }. Those bits define the QAM bit-levels 106 that distinguish between high-energy and low-energy symbols 105.

• The aim of the shaping interleaver 201a is to make sure that the bits in the indices S of d are mapped to the indices given by B oif.

Thus, the interleaver criteria are:

• As the operations in the‘Sub-block Interleaver’ and‘Bit Selection’ in the encoder 200 and of the channel interleaver 201a are well defined in the technical specification, the indices of the bits in / (output from the channel interleaver 201a to the shaping interleaver 201b) that are shaped are known.

• For given parameters N and M, the set S is obtained (can be calculated offline).

• By using the definitions of the sub-block interleaver, bit selection and channel interleaver 201a, the set N is obtained, that includes the shaped bits in/.

• The shaping interleaver 201b is an interleaver, where the elements at the indices N are mapped to the locations at the output sequence with indices B.

• The rest of the elements in/ can be mapped arbitrarily to the rest of the indices in/’.

Such a serial shaping interleaver 201 made of channel interleaver 201a and shaping interleaver 201b as shown in FIG. 4 is advantageous in the sense that it can be switched off to support backward compatibility. It does not necessarily change the structure of the existing channel interleaver, and can be seen as an add-on to the existing transmitter chain.

FIG. 5 shows a device 100 according to an embodiment of the invention, which builds on the device 100 shown in FIG. 3. The device 100 includes particularly a parallel interleaver 201. The following steps are used and are depicted in FIG. 5:

• For given parameters N and M, the set S is obtained.

• By using the definitions of the sub-block interleaver and bit selection of the encoder 200, the set S^_ is obtained, which includes the shaped bits in e. We call the set containing the indices of the rest of the elements of e (not shaped bits) as U.

• A splitter 500 included in device 100 may extract the bits at the indices S^_ and U and the device 100 may perform interleaving separately. The interleaving can be done by using any conventional interleaver of the corresponding lengths. For example, the device 100 may include and employ a conventional channel interleaver 201a (with the corresponding length) for S^_ and may include and employ a shaping interleaver 201b, e.g. an s-random interleaver for bits in U. For the latter, it is also possible to use the conventional channel interleaver with the corresponding length for U.

• A combiner 501 included in the device 100 may then be used to generate the sequence /’, which contains the interleaved bits from S^_ at indices B (corresponding to the third and fourth bit-levels, if 5GNR is considered), and the interleaved bits from U in the rest.

The parallel shaping interleaver 201 made of channel interleaver 201a and shaping interleaver 201b as shown in FIG. 5 has also advantages. First of all, two interleaving operations can be done in parallel such that no extra delay is introduced. Secondly, a conventional interleaver could be used for both channel interleaver 201a and shaping interleaver 201b. For example, 5G NR specifies the channel interleaver as a triangular interleaver with flexible length. One can use this triangular interleaver as both channel and shaping interleavers 201a, b, such that the same hardware is used for both of them, thus reducing the cost for the storage on an extra interleaver.

FIG. 6 shows a method 600 according to an embodiment of the invention. The method 600 is particularly for supporting probabilistic constellation shaping. The method 600 can be carried out by the device 100 and comprises: a first step of receiving 601 a first bit sequence 101 including at least two sub-sequences 102, 103; a second step of separately interleaving 602 each of the sub- sequences 102, 103; a third step 603 of forming a second bit sequence 104 including the at least two sub-sequences 102’, 103’ after interleaving; and a fourth step of mapping 604 the second bit sequence 104 to a plurality of symbols 105 and thereby mapping at least one of the sub-sequences 102’, 103’ to one or more pre-defined bit-levels 106.

The present invention has been described in conjunction with various embodiments as examples as well as implementations. However, other variations can be understood and effected by those persons skilled in the art and practicing the claimed invention, from the studies of the drawings, this disclosure and the independent claims. In the claims as well as in the description the word“comprising” does not exclude other elements or steps and the indefinite article“a” or“an” does not exclude a plurality. A single element or other unit may fulfill the functions of several entities or items recited in the claims. The mere fact that certain measures are recited in the mutual different dependent claims does not indicate that a combination of these measures cannot be used in an advantageous implementation.

Claims

1. Device (100) for supporting probabilistic constellation shaping, configured to:

- receive a first bit sequence (101) including at least two sub-sequences (102, 103),

- separately interleave each of the sub-sequences (102, 103),

- form a second bit sequence (104) including the at least two sub-sequences (102’, 103’) after interleaving,

- map the second bit sequence (104) to a plurality of symbols (105) and thereby map at least one of the sub-sequences (102, 103) to one or more pre-defined bit-levels (106).

2. Device (100) according to claim 1, wherein:

the mapping of the second bit sequence (104) is performed by a symbol mapper (202) and wherein the forming of the second bit sequence (104) depends on the structure of the symbol mapper (202).

3. Device (100) according to claim 1 or 2, wherein:

the at least one of the sub-sequences (102’, 103’), which is mapped to the one or more pre-defined bit-levels (106), includes bits distributed according to a target probability distribution.

4. Device (100) according to one of the claims 1 to 3, wherein:

the at least one of the sub-sequences (102’, 103’), which is mapped to the one or more pre-defined bit- levels (106), includes bits distributed according to a non-uniform probability distribution.

5. Device (100) according to one of the claims 1 to 4, wherein:

at least two different sub-sequences (102’, 103’) , which are each mapped to one or more pre-defined bit-levels (106), include bits distributed according to different probability distributions.

6. Device (100) according to one of the claims 1 to 5, configured to:

map the at least one of the sub-sequences (102’, 103’) to two or more pre-defined bit- levels (106).

7. Device (100) according to claim 6, wherein:

the plurality of symbols (105) is a plurality of Quadrature Amplitude Modulation, QAM, symbols, and

the two pre-defined bit- levels (106) are the third bit-level and the fourth bit-level.

8. Device (100) according to one of the claims 1 to 7, wherein:

the one or more pre-defined bit- levels (106) determine for each of the plurality of symbols (105) whether the symbol (105) is a high-energy symbol or a low-energy symbol.

9. Device (105) according to claim 8, configured to:

generate a high-energy symbol with a lower probability than a low-energy symbol.

10. Device (100) according to one of the claims 1 to 9, comprising;

a first interleaver (201a) connected in series to a second interleaver (201b), wherein the second interleaver (201b) is configured to interleave the at least one of the sub-sequences (102, 103), which is mapped to the one or more pre-defined bit-levels (106), and the first interleaver (201a) is configured to interleave the at least one other sub sequence (103, 102).

11. Device (100) according to one of the claims 1 to 9, comprising:

a first interleaver (201a) connected in parallel to a second interleaver (201b), and a splitter (500) configured to receive the first bit sequence (101) and to direct the at least one of the sub-sequences (102, 103), which is mapped to the one or more pre-defined bit-levels, to the second interleaver (201b) and the at least one other sub-sequence (103, 102) to the first interleaver (201a), and

a combiner (501) configured to form the second bit sequence (104) by recombining the at least one of the sub-sequences (102’, 103’) and the at least one other sub-sequence (103’, 102’) after interleaving.

12. Device (100) according to one of the claims 1 to 11, configured to:

receive the first bit sequence from an encoder (200), in particular a channel encoder.

13. Device according to claim 12, wherein:

the encoder (200) is configured to perform polar coding (203).

14. Device (100) according to one of the claims 1 to 13, wherein:

the first bit sequence (101) is a probabilistically shaped bit sequence.

15. Transmitter device for probabilistic constellation shaping, comprising:

the device (100) according to one of the claims 1 to 14, and

an encoder (200) configured to perform polar coding (203) to generate the first bit sequence (101) and to provide it to the device (100).

16. Method (600) for supporting probabilistic constellation shaping, the method (600) comprising:

- receiving (601) a first bit sequence (101) including at least two sub- sequences (102, 103),

- separately interleaving (602) each of the sub-sequences (102, 103),

- forming (603) a second bit sequence (104) including the at least two sub sequences (102’, 103’) after interleaving,

- mapping (604) the second bit sequence (104) to a plurality of symbols (105) and thereby mapping at least one of the sub-sequences (102’, 103’) to one or more pre-defined bit- levels (106).