CN113037634A - Processing method, logic circuit and equipment of matching action table based on FPGA - Google Patents
Processing method, logic circuit and equipment of matching action table based on FPGA Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L45/00—Routing or path finding of packets in data switching networks
- H04L45/74—Address processing for routing
- H04L45/745—Address table lookup; Address filtering
- H04L45/7453—Address table lookup; Address filtering using hashing
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
- H04L69/22—Parsing or analysis of headers
Abstract
The invention provides a processing method, a logic circuit and equipment of a matching action table based on an FPGA (field programmable gate array), wherein the processing method of the matching action table based on the FPGA comprises the following steps: CPU configures searching table item; when the packet header information and the tuple data information of a network packet are input, extracting and searching keywords from the packet header information and the tuple data information; sending the keywords into a lookup table for matching lookup; after the searching is finished, the searching table outputs a signal of successful or failed matching and matching result data; if the matching is successful, selecting an action execution unit to execute the action according to the action code in the matching result, carrying out related operation on the packet header protocol field and the tuple data, and then sending the packet header protocol field and the tuple data to a lower-level matching action table for subsequent packet processing. By adopting the technical scheme of the invention, the selection of any search keyword and the logic, arithmetic operation and modification of any packet header protocol field can be realized, so that fewer FPGA logic resources are occupied and the running speed is high.
Description
Technical Field
The invention relates to the technical field of networks, in particular to a processing method, a logic circuit and equipment of a matching action table based on an FPGA (field programmable gate array).
Background
Software-Defined Networks (SDN) was born in 2006. In 2009, SDN entered "ten major breakthroughs in the future" of the science and technology review of maja province. The design core of the SDN is separation of a control plane and a data plane, which claims to implement control of a network through a centralized controller platform. In the SDN architecture, a control plane is logically centralized, and control information is issued to an underlying data plane for execution through a certain protocol. The control plane is therefore called the brain of the SDN and directs the operation of the entire data network. The existence of the control plane makes the deployment and configuration of the network more intelligent and simplified, thanks to the advantage of centralized control. The SDN control plane supporting programming enables the network to be more intelligent, more flexible and easier to expand. The controller can issue an instruction to the network element equipment of the data plane through an API of a southbound protocol of the SDN, and control transmission of the control plane and the data plane is completed.
SDN implements programmability of a control plane, but a data plane is still implemented using fixed-function switches, and these conventional switches only support existing network protocols and do not support newly defined network protocols. With the explosive development of data centers, more and more new network protocols are applied to the data centers, and the application of the new network protocols is seriously hindered by the fixed-function switches. In order to make the data plane programmable as well, the P4(Programming Protocol-Independent Packet Processors) Programming language was proposed by the teaching of Nick McKeown at stanford university 2014 and by the teaching of Jennifer Rexford at preston university.
P4 is a protocol independent data packet processing programming language, P4 supports user-defined matching field, protocol parsing process and forwarding process, thereby realizing a protocol independent programmable network data plane in the true sense. A Tofino chip developed by Barefoot corporation completely supports P4 language programming, and the functions of traditional network equipment and innovative network functions can be realized by describing a message Parser (Parser), a matching Action Table (Match-Action Table) and a message reverse Parser (Parser) by using P4. Although the Tofino chip supports P4 programming, and the interface bandwidth reaches 6.5Tbps, the Tofino chip is expensive and is not suitable for an application occasion which only needs a small interface bandwidth capacity like an intelligent network card, and the FPGA becomes the first choice for network application with a small interface bandwidth due to the relatively low programmability and price, and a P4 switch based on the FPGA becomes a current research hotspot.
As mentioned above, the matching action table is one of the programmable modules described in the three P4 languages, the P4 language allows any header protocol field to be used as a lookup key of the matching table, and allows the action execution unit to perform a logical operation or an arithmetic operation on any header protocol field, the tof chip selects the lookup key through a very large multiplexing circuit, and then several hundreds of processors with simplified instructions are preset in the action execution unit, and these hardware circuits consume a lot of logic resources, which is also a cost for the ASIC to implement the programmable switch. Because the Tofino chip adopts a 7nm process, the logic resources only occupy 7% of the whole chip area, so the influence of the matching-action circuit on the whole chip cost is not obvious, but if the FPGA uses the same circuit to realize the matching action table, the logic resources occupied by the hardware circuit are a disaster for FPGA design, taking the example of selecting 32-bit IP address search keywords from 1024-bit header data, a multi-path selection circuit occupies more than 3000 LUTs of the FPGA, if the Zynq 7z100 of Xilinx is used, the FPGA has 277400 LUTs, according to ten matching action table estimation, the search keyword selection circuit only matching the action table can use 11% of the logic resources of the Zynq 7z100, and the large logic resource occupation is unacceptable for FPGA design.
P4 SDNet is a tool from saints that converts P4 language to Px language, and then converts Px language to Verilog language using SDNet compiler, which is a general hardware logic design language; the P4FPGA is an open source tool, and the working process of the FPGA is to convert a P4 program into a Bluespec program and then convert the Bluespec program into Verilog codes by using a Bluespec compiler. The tools convert the P4 program into another high-level language, and then convert the program into a hardware description language, the conversion efficiency is not high, and the fact that the logic circuit of the converted matching action table occupies larger logic resources of the FPGA, and the clock frequency of the operation of the logic circuit is low. The practical application requirement of realizing the programmable matching action table on the FPGA can be met only by finding a hardware circuit design method which occupies less logic resources and has high-speed look-up table and action execution.
Disclosure of Invention
Aiming at the technical problems, the invention discloses a processing method, a logic circuit and equipment of a matching action table based on an FPGA (field programmable gate array), and solves the problems of large logic resource occupation and low operation speed in the process of converting the matching action table described by the existing P4 language into an FPGA hardware circuit.
In contrast, the technical scheme adopted by the invention is as follows:
a processing method of a matching action table based on FPGA is characterized in that:
the input signal of the matching action table based on the FPGA comprises packet header information and tuple data information;
the processing method of the matching action table based on the FPGA comprises the following steps:
CPU configures searching table item;
when the packet header information and the tuple data information of a network packet are input, extracting and searching keywords from the packet header information and the tuple data information;
sending the keywords into a lookup table for matching lookup;
after the searching is finished, the searching table outputs a signal of successful or failed matching and matching result data;
if the matching is successful, selecting an action execution unit to execute the action according to the action code in the matching result, carrying out logic operation, arithmetic operation, modification and addition operation on the header protocol field and the tuple data, and finally sending the newly generated header protocol field and the tuple data to a lower-level matching action table for subsequent packet processing.
By adopting the technical scheme, the matching action table can realize the selection of any search keyword and the logic, arithmetic operation and modification of any packet header protocol field, the aims of occupying few FPGA logic resources and high operation speed are achieved, the flow line modular structure is adopted, the conflict and pause are avoided in the processing of the message, the table item matching and action execution for processing one data packet in each clock period are realized, the occupation of few FPGA resources is reduced, the operation speed is high, and the method can flexibly adapt to various search algorithms.
As a further improvement of the present invention, the processing method of the matching action table based on the FPGA includes: and (3) beating the input packet header information and tuple data registers, and aligning the time sequence of the output packet header information and tuple data after beating with the matching result signal output by the lookup table module.
As a further improvement of the present invention, the CPU configures a lookup table entry, and writes the contents of the table entry to be configured into a write data register inside the CPU configuration module, then writes a table entry index register and a read/write selection register of the CPU configuration module, and finally writes a table entry access start flag bit of the CPU configuration module; wherein the entry content includes a lookup key, an action code, and action data.
As a further improvement of the present invention, the packet header information includes a protocol field of each protocol layer of the packet header analyzed by the preceding message analyzer, and an effective flag bit of the protocol field; the meta-group data information comprises an input port number, an output port number, a packet length, a priority, a multicast group number and user-defined packet information of the data packet.
The invention also discloses a logic circuit of the matching action table based on the FPGA, and an input signal of the matching action table based on the FPGA comprises packet header information and tuple data information;
the logic circuit of the FPGA-based matching action table comprises:
the CPU configuration module is used for configuring the lookup table items, and comprises read operation and write operation of the lookup table module;
the lookup key word construction module is used for generating lookup key words and outputting the lookup key words to the lookup table module;
the lookup table module is used for matching the input lookup key words with the matching key words in the lookup table items and outputting a matching success signal, a matching failure signal and matching result data to the action execution module;
the action execution module executes actions according to action codes in the matching result, performs logical operation, arithmetic operation, modification and addition operation on the header protocol field and the tuple data, and finally sends the newly generated header protocol field and the tuple data to a lower-level matching action table for subsequent packet processing; namely, modifying the header information and the tuple data, and then outputting the new header information and the tuple data to the next matching action table.
As a further improvement of the present invention, the logic circuit of the FPGA-based matching action table further includes:
and the packet header and tuple data register module is used for beating the input packet header information and tuple data register and aligning the time sequence of the output packet header information and tuple data after beating with the matching result signal output by the lookup table module.
As a further improvement of the invention, the action execution module receives the matching success, failure signals and matching result data from the lookup table module, and simultaneously receives the packet header information and the tuple data from the packet header and tuple data register module, and executes the action according to the action code in the matching result.
As a further improvement of the present invention, the packet header information includes a protocol field of each protocol layer of the packet header analyzed by the preceding message analyzer, and an effective flag bit of the protocol field; the meta-group data information comprises an input port number, an output port number, a packet length, a priority, a multicast group number and user-defined packet information of the data packet.
As a further improvement of the present invention, the CPU configuration module writes contents of a table entry to be configured into a write data register inside the CPU configuration module, then writes a table entry index register and a read/write selection register of the CPU configuration module, and finally writes a table entry access start flag bit of the CPU configuration module; wherein the entry content includes a lookup key, an action code, and action data.
The invention discloses equipment which comprises a processor and a memory which are connected, wherein the processor is used for executing a computer program stored in the memory so as to execute the processing method of the matching action table based on the FPGA.
The invention discloses a computer readable storage medium, which comprises a computer program for executing the processing method of the matching action table based on the FPGA.
The invention discloses a design method of a logic circuit of a matching action table based on an FPGA, which comprises the following steps:
instantiating a search key construction module, calculating the bit width of a search key in a P4 program, and defining search key signals with the same bit width; according to the search key defined by the P4 program, assigning a packet header protocol field or a certain tuple data field to a search key signal;
instantiating a CPU configuration module, calculating bit widths of search keywords, action codes and action data in a P4 program, and defining data writing signals and data reading signals of a lookup table module with the same bit width; calculating the bit width of the table entry size, and defining the table entry index signals with the same bit width;
selecting a statement according to a search algorithm in a P4 program, selecting a corresponding search module for instantiation, calculating the bit width of a search keyword in the P4 program, and defining search keyword input signals with the same bit width; calculating bit widths of action data and action execution unit quantity in the P4 program, and defining matching result data output signals with the same bit width;
instantiating a packet header and tuple data register module, selecting a statement according to a search algorithm in a P4 program, and setting a beating level parameter value corresponding to the search module;
instantiating an action execution module, instantiating each action of a lookup table defined in a P4 program into an action execution unit by converting a P4 statement of each action into a Verilog statement of the action execution unit;
connecting the packet header information and the tuple data information of the input signals matched with the action table to a search keyword construction module and a packet header and tuple data register module; connecting a search key word signal output by a search key word construction module to a search table module, and connecting a table entry read-write signal output by a CPU configuration module to the search table module; connecting the matching success signal, the matching failure signal and the matching result data signal output by the lookup table module to the action execution module, and connecting the packet header, the packet header output by the tuple data register module and the tuple data signal to the action execution module;
after the module connection is completed, an FPGA logic circuit with the function of a P4 definition lookup table is obtained.
Compared with the prior art, the invention has the beneficial effects that:
firstly, by adopting the technical scheme of the invention, the programmability of the search algorithm is met by the structure of the search keyword, the execution of the matching action, the function separation of the search algorithm and the pre-design and selection of various search algorithm modules. In addition, the parameterized design of the key word signal bit width, the table entry index signal bit width, the action code and the action data signal bit width provided by the technical scheme of the invention meets the programmability of searching the key word, the table entry size and executing the action.
Secondly, by adopting the technical scheme of the invention, a keyword searching signal is constructed according to the keyword definition of the P4 code, and the P4 code of the action execution unit is directly converted into the Verilog code, so that the design of a logic circuit is simplified, FPGA resources are saved, and the running speed of an action execution module is obviously improved.
Thirdly, by adopting the technical scheme of the invention, the matching action table can realize the selection of any search keyword and the logic, arithmetic operation and modification of any packet header protocol field, thereby realizing the purposes of less occupation of FPGA logic resources and high running speed, and adopting a pipeline modularized structure, having no conflict and pause on the processing of the message, and executing the table item matching and the action of processing one data packet in each clock cycle.
Drawings
FIG. 1 is a schematic diagram of a matching action table logic circuit according to an embodiment of the present invention.
FIG. 2 is a flowchart illustrating instantiation of a logic circuit of a match action table according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of a working flow of a logic circuit of a matching action table according to an embodiment of the present invention.
Detailed Description
Preferred embodiments of the present invention are described in further detail below.
An input signal of the matching action table comprises packet header information and tuple data information. The packet header information comprises protocol fields of each protocol layer of the packet header analyzed by the preceding-stage message analyzer and effective zone bits of the protocol fields; the meta-group data information comprises an input port number, an output port number, a packet length, a priority, a multicast group number and user-defined packet information of the data packet.
The processing method of the matching action table based on the FPGA comprises the following steps: the CPU configures a lookup table item, when the packet header information and the tuple data information of a network packet are input, selects a lookup key word from the packet header information and the tuple data information, then sends the key word into a lookup table for matching, then the lookup table outputs a matching success or failure signal and matching result data, if the matching is successful, selects an action execution unit to execute the action according to an action code in the matching result, performs logic operation, arithmetic operation, modification and addition operation on the packet header protocol field and the tuple data, and finally sends the newly generated packet header protocol field and the tuple data to a lower-level matching action table for subsequent packet processing.
The CPU configuration search table item comprises the steps of firstly writing the content of a table item to be configured into a data writing register in a CPU configuration module, then writing a table item index register and a read-write selection register of the CPU configuration module, and finally writing a table item access start flag bit of the CPU configuration module; wherein the entry content includes a lookup key, an action code, and action data.
Further, the processing method further comprises the following steps: and (3) beating the input packet header information and tuple data registers, and aligning the time sequence of the output packet header information and tuple data after beating with the matching result signal output by the lookup table module.
The embodiment of the invention also discloses a logic circuit of the matching action table based on the FPGA, which comprises five modules of a search keyword construction module, a CPU configuration module, a search table module, a packet header and tuple data register module and an action execution module.
The lookup key construction module is used for generating lookup keys and outputting the lookup keys to the lookup table module.
Because the search key defined in the P4 program is a certain header protocol field or a certain tuple data field, the field can be directly assigned to the search key signal by using the programmable property of the FPGA logic, and the selected field is shown to be connected to the search key signal in the FPGA, which only occupies a small amount of connection resources and almost ignores the occupation of the FPGA logic resources.
The method for directly assigning the value to the search keyword signal avoids the use of a multi-path selection circuit occupying a large amount of logic resources and reduces the use amount of the logic resources to the minimum. Because only the connection resources are used and no combinational logic is used, the operation speed of the keyword searching construction module can also reach the fastest speed.
The CPU configuration module is used for configuring the lookup table items, and comprises reading operation and writing operation of the lookup table module.
The reading and writing operation of the lookup table item adopts an indirect access mode, software firstly writes the content of the table item to be configured into a data writing register in the CPU configuration module, then writes a table item index register and a reading and writing selection register of the CPU configuration module, and finally writes a table item access starting flag bit of the CPU configuration module. Wherein the entry content includes matching keywords and matching result data. After the CPU configuration module detects that the table entry access start flag bit is valid, the CPU configuration module performs read and write operations on the lookup table module according to the table entry index and the table entry content configured by the software.
For the reading operation, the CPU configuration module stores the data returned by the lookup table module into an internal reading data register, then clears the table entry access starting flag bit, and after software inquires that the flag bit is cleared, reads the reading data register in the CPU configuration module to finish the reading of the lookup table entry.
For write operation, after receiving the write response signal of the lookup table module, the CPU configuration module clears the table entry access start flag bit, and after software queries that the flag bit is cleared, the CPU configuration module considers that the write operation on the lookup table entry is completed.
The method can realize the read-write access of software to the lookup table module of any lookup algorithm by utilizing an indirect access mode, and the bit widths of a write data register, a read data register and a table entry index register in the CPU configuration module can be defined by parameters, so that the method can be adapted to lookup table examples with any data bit width and any table entry size, and meets the programmable requirements of lookup keywords, lookup results and table entry sizes of the lookup table.
The lookup table module matches the input lookup key with the matching key in the lookup table entry, and outputs a matching success signal, a matching failure signal, and matching result data to the action execution module. The matching result data comprises action codes and action data, the action codes are used for selecting one action execution unit in the action execution module, and the action data is parameters required by the action execution unit.
The corresponding lookup modules are designed in advance according to different lookup algorithms, for example, a HASH lookup table module corresponding to an exact matching algorithm, a TCAM lookup table module corresponding to a fuzzy matching algorithm, and an LPM lookup table module corresponding to a longest prefix matching algorithm, all of which adopt a pipeline design, and each clock cycle allows a new keyword to be input for lookup, that is, the lookup performance can reach the performance of looking up a packet in one clock cycle. The input and output interfaces of the lookup table modules are completely the same, bit width of lookup key words serving as input signals can be defined by parameters, bit width of matching result data serving as output signals can also be defined by parameters, bit width of table item indexes, write table item data and read table item data of the interfaces of the CPU configuration module can be defined by parameters, and the number of table items of the lookup table can also be defined by parameters. And selecting a corresponding module from the pre-designed lookup modules according to a lookup algorithm selection statement in the P4 program, and using the instantiated module as a lookup table module.
In summary, the parameterized design of the search algorithm module and the pre-design of various search algorithm modules satisfy the requirements of searching the bit width of the keyword, the bit width of the matching result data, the number of table entries and the programmability of the search algorithm.
The packet header and tuple data register module is used for beating the input packet header information and tuple data register, so that the time sequence of the output packet header information and tuple data after beating is aligned with the signal of the matching result output by the lookup table module.
Because different search algorithms spend different clock cycles, for example, the HASH search algorithm needs three clock cycles to complete the search, and the TCAM search algorithm needs seven clock cycles to complete the search, in order to ensure that the packet header, the tuple data and the matching result reaching the action execution module are all signals of the same packet, the packet header and the tuple data must be tapped by using a register to perform the time sequence alignment operation.
The beat stage number of the packet header and the tuple data register module can be defined by parameterization, as described above, if the HASH search algorithm is adopted, the beat stage number parameter needs to be set to three beats to ensure the time sequence alignment of the packet header, the tuple data and the matching result signal output by the lookup table module, and if the TCAM search algorithm is adopted, the beat stage number parameter needs to be set to seven beats to ensure the time sequence alignment of the packet header, the tuple data and the matching result signal output by the lookup table module.
The action execution module receives matching success and failure signals and matching result data from the lookup table module, receives packet header information and tuple data from the packet header and tuple data register module, executes actions according to action codes in the matching results, namely modifies the packet header information and the tuple data, and outputs new packet header information and tuple data to a next-stage matching action table.
If the matching success signal is valid, the header information, the tuple data information and the action data are sent to the corresponding action execution unit according to the action code in the matching result data, the header protocol field, the logical operation, the arithmetic operation, the shift operation and the modification of the tuple data are executed in the action execution unit, in the P4 program, the operation for a certain header and tuple data field is determined, for example, the 1 subtraction operation for the TTL field in the IPv4 protocol header, and the operation sign of the P4 statement and the operation sign of the Verilog language are completely the same, for example, the addition operation is represented by "+", the logical AND operation is represented by "&", so the operation code in the P4 program can be directly converted into the Verilog code.
By directly converting the action statement of the P4 into the Verilog code, the design of the action execution module is simplified, a large number of processors are not required to be arranged in advance to execute operation, the occupied FPGA logic resource is reduced to the minimum, the operand used for executing the action is from a header protocol field, metadata and a lookup table matching result, the operand is sent to the action execution logic circuit through the connection resource in the FPGA, a complex multi-path selection circuit is not required to select signals, the FPGA resource is saved, and meanwhile, the operation speed of the action execution module is obviously improved.
The search keyword construction module, the lookup table module, the packet header and tuple data register module and the action execution module which participate in packet processing all adopt pipeline design, the matching and action execution functions are decomposed into a plurality of sub-functions, each sub-function can be completed only by one clock cycle, and all sub-functions can process different packet information in parallel, so that the matching action table logic circuit can realize the high performance of processing one packet in each clock cycle.
The embodiment of the invention also discloses a device, which comprises a processor and a memory which are connected, and is characterized in that: the processor is used for executing the computer program stored in the memory to execute the processing method of the matching action table based on the FPGA.
The embodiment of the invention also discloses a computer readable storage medium which comprises a computer program and is used for executing the processing method of the matching action table based on the FPGA.
The embodiment of the invention also provides a design method of the programmable matching action table, which comprises the following implementation steps:
1) and instantiating a search key construction module, calculating the bit width of the search key in the P4 program, and defining a search key signal with the same bit width. The header protocol field or some tuple data field is assigned to the lookup key signal according to the lookup key defined by the P4 program.
2) Instantiating a CPU configuration module, calculating the bit width of the lookup key, the action code and the action data in the P4 program, and defining the data signal and the data signal of the lookup table module with the same bit width. And calculating the bit width of the table entry size, and defining the table entry index signals with the same bit width.
3) Selecting a statement according to a search algorithm in the P4 program, selecting a corresponding search module for instantiation, calculating the bit width of a search key in the P4 program, and defining input signals of the search key with the same bit width. Bit widths of the action data and the number of action execution units in the P4 program are calculated, defining matching result data output signals of the same bit width.
4) Instantiating a packet header and tuple data register module, selecting a statement according to a search algorithm in a P4 program, and setting a beating level parameter value corresponding to the search module.
5) Instantiating the action execution module, each action of the lookup table defined in the P4 program is instantiated into an action execution unit by converting the P4 statements of each action into Verilog statements of the action execution unit.
6) Connecting the packet header information and the tuple data information of the input signals matched with the action table to a search keyword construction module and a packet header and tuple data register module; connecting a search key word signal output by a search key word construction module to a search table module, and connecting a table entry read-write signal output by a CPU configuration module to the search table module; the matching success signal, the matching failure signal and the matching result data signal output by the lookup table module are connected to the action execution module, and the packet header, the packet header output by the tuple data register module and the tuple data signal are also connected to the action execution module. After the module connection is completed, an FPGA logic circuit with the function of a P4 definition lookup table is obtained.
This will be described in further detail below.
As shown in fig. 1, the logic circuit of the matching action table based on the FPGA of this embodiment includes:
and the lookup key word construction module is used for generating lookup key words and outputting the lookup key words to the lookup table module.
And the CPU configuration module is used for configuring the lookup table items, and comprises reading operation and writing operation of the lookup table module.
And the lookup table module is used for matching the input lookup key words with the matching key words in the lookup table items and outputting matching success and failure signals and matching result data to the action execution module.
The header and tuple data register module is used for beating the input header information and tuple data register, aiming at aligning the time sequence of the output header information and tuple data after beating with the matching result signal output by the lookup table module, and sending the output header information and tuple data to the action execution module.
And the action execution module receives the matching success and failure signals and the matching result data from the lookup table module, receives the packet header information and the tuple data from the packet header and tuple data register module, executes actions according to action codes in the matching result, namely modifies the packet header information and the tuple data, and outputs new packet header information and tuple data to a next-stage matching action table.
The input signal of the logic circuit of the matching action table comprises header information headers _ in and tuple data information metadata _ in. The header information headers _ in is generated by a preceding-stage message parser and comprises protocol fields of all protocol layers of the header and effective zone bits of the protocol fields; the meta group data information metadata _ in is information related to packet input, packet output, and packet processing, and includes an input port number, an output port number, a packet length, a priority, a multicast group number, and user-defined packet information of a data packet.
After the header information headers _ in and the tuple data information metadata _ in are input into the matching action table logic circuit, the header information headers _ in and the tuple data information metadata _ in are sent to the lookup key construction module and the header and tuple data register module, the lookup key construction module outputs the constructed lookup key to the lookup table module, and the header and tuple data register module sends the tapped header information headers _ reg and tuple data information metadata _ reg to the action execution module.
The CPU interface signal is input into the matching action table logic circuit and then sent to the CPU configuration module, after the CPU completes the indirect access configuration and writes the table item access start flag bit, the CPU configuration module generates a lookup table read-write signal and sends the lookup table read-write signal to the lookup table module, and after the lookup table module completes the read operation, the read-data signal is returned to the CPU configuration module.
After the lookup table module finishes the keyword lookup of a packet, the lookup table module sends a matching success signal hit, a matching failure signal miss, an action code signal action code and an action data signal action data to the action execution module.
And after the action execution module finishes the action execution, outputting the modified new header information headers _ out and tuple data information metadata _ out to the next-stage matching action table logic circuit.
The instantiation process of the matching action table based on the FPGA will be described in detail below by taking a lookup table described in the P4 language as an example.
A typical look-up table described in the P4 language is as follows:
// action execution Unit 1 definition
action Drop_action() {
metadata.egress_port = DROP_PORT;
}
// action execution Unit 2 definition
action Set_nhop(bit<32> ipv4_dest, bit<9> port) {
metadata.nexthop = ipv4_dest;
headers.ip.ttl = headers.ip.ttl – 1;
metadata.egress_port = port;
}
// lookup Table definition
table ipv4_match {
Ip _ dstAddr, the search algorithm selects lpm algorithm
key = { headers.ip_dstAddr: lpm; }
The configurable action of/lookup table entry is Drop action or Set _ nhop
actions = { Drop_action;
Set_nhop;
}
// lookup table entry size 1024
size = 1024;
The default action performed when/lookup table does not match is Drop action
default_action = Drop_action;
}
As can be seen from the above P4 code, the lookup table described in the P4 language includes the following statements: the first part is an action execution unit definition statement, a plurality of action execution units may exist, the executed action comprises logical operation, arithmetic operation, modification and addition operation on packet header protocol field and tuple data, action data in a table item search result may be used for participating in the operation, and the action data are configured into a search table by a controller in the operation process of a data forwarding plane; the second part is a search keyword definition statement, and a part of fields are mainly selected from a packet header or tuple data to be used as search keywords; the third part is a search algorithm selection statement, for example, exact represents selection of an exact matching algorithm, tertiary represents selection of a fuzzy matching algorithm, and lpm represents selection of a longest prefix matching algorithm; the fourth part is the table entry size definition statement.
As shown in fig. 2, the design method of the matching action table based on the FPGA implemented in this embodiment, that is, the instantiation process, includes:
1) and instantiating a search key construction module, and constructing and outputting a search key signal. The search key defined in the above P4 code is headers, ip _ dstAddr, and as can be seen from calculation, the data bit width of the search key is 32 bits, so the bit width of the search key signal lookup key is defined as 32 bits, and the headers, ip _ dstAddr signal is assigned to the search key signal lookup key, thereby completing the construction of the search key.
2) The logic circuit of the CPU configuration module is designed in advance, so that indirect access to the lookup table module can be completed, and instantiation of the CPU configuration module can be completed only by assigning values to table entry read-write data signal bit width parameters and table entry index bit width parameters. As can be seen from the process 1, the bit width of the keyword is searched for to be 32 bits; the above-mentioned P4 code defines two kinds of action execution units, and thus the two kinds of action execution units can be represented by a 1-bit action code; the action execution unit Drop _ action has no parameter, and the parameters of the action execution unit Set _ nhop are ipv4_ dest and port, and the sum of the data bit widths is 41 bits, so the bit width of the action data is 41 bits. The elements forming a table entry include the lookup key, the action code and the action data, and as can be seen from the above calculation, the sum of the data bit widths of the three is 74 bits, so that the value 74 is assigned to the table entry read-write data signal bit width parameter. The size of the lookup table entry defined by the above P4 code is 1024, and it can be known through calculation that the 1024 table entries can be numbered by the index number of 10 bits, so that the value of 10 is assigned to the table entry index bit width parameter.
3) And selecting a lookup algorithm module, instantiating a lookup table module, and assigning values to bit width parameters of lookup keywords, action codes and action data. The search algorithm selected by the P4 code is an lpm algorithm, that is, a longest prefix matching algorithm, the search module with the lpm algorithm is designed in advance, the input and output interface signals of the search module are completely the same as the interface signals of the lookup table module in fig. 1, and the bit width of the search key input signal, the bit width of the table entry read-write data and the table entry index signal from the CPU configuration module, the bit width of the output action code, and the bit width of the action data are parametrically defined. According to the calculation results of the processes 1 and 2, the lookup key word signal bit width is assigned 32, the table entry read-write data bit width is assigned 74, the table entry index signal bit width is assigned 10, the action code bit width is assigned 1, and the action data bit width is assigned 74.
4) Instantiating a packet header and tuple data register module to assign values to the parameters of the beating stage. The lpm search algorithm selected by the P4 code needs 8 clock cycles to complete keyword search, and in order to ensure that the packet header, the tuple data and the matching result reaching the action execution module are all signals of the same packet, the beat level parameter of the packet header and the tuple data register module needs to be assigned with 8, that is, the packet header and the tuple data signals are delayed by 8 clock cycles to be output.
5) And (4) instantiating an action execution module and converting the P4 code of the action execution unit into Verilog code. The action execution unit Drop _ action in the above P4 code is converted to the following Verilog code:
headers_out0 = headers_reg;
metadata_out0 = metadata_reg;
metadata_out0.egress_port = DROP_PORT;
the action execution unit Set _ nhop is converted into the following Verilog code:
headers_out1 = headers_reg;
metadata_out1 = metadata_reg;
metadata_out1.nexthop = ipv4_dest;
headers_out1.ip.ttl = headers_reg.ip.ttl – 1;
metadata_out1.egress_port = port;
finally, the packet header and tuple data modified by the two action execution units are selected as output signals through the action code. When the operation code is 0, the heads _ out0 and metadata _ out0 are selected as output signals; when the action code is 1, heads _ out1 and metadata _ out1 are selected as output signals.
6) And connecting the interface signals of each module. Connecting the packet header information and the tuple data information of the input signals matched with the action table to a search keyword construction module and a packet header and tuple data register module; connecting a search key word signal output by a search key word construction module to a search table module, and connecting a table entry read-write signal output by a CPU configuration module to the search table module; the matching success, failure and matching result data signals output by the lookup table module are connected to the action execution module, and the packet header, the packet header output by the tuple data register module and the tuple data signals are also connected to the action execution module. After the connection of the modules is completed, an FPGA logic circuit with the function of P4 lookup table definition is obtained.
As shown in fig. 3, the processing method of the matching action table based on the FPGA of the present embodiment, that is, the workflow implemented by the matching action table based on the FPGA includes:
1) and the CPU configures a lookup table entry. The method is characterized in that a lookup table entry is configured by adopting an indirect access mode, namely, software writes the content of the table entry to be configured into a write data register in a CPU configuration module, then writes a table entry index register and a read-write selection register of the CPU configuration module, and finally writes a table entry access start flag bit of the CPU configuration module. The entry content includes a lookup key, an action code, and action data.
2) When the packet header information and the tuple data information of a packet are input into the matching-action logic circuit, the search keyword construction module extracts the search keyword from the packet header information and the tuple data information and outputs the search keyword to the lookup table module.
3) The lookup table module uses the lookup key words to perform matching lookup in the lookup table, and outputs a matching success signal, a matching failure signal, an action code and an action data signal to the action execution module after the lookup is completed.
4) And the action execution module selects a corresponding action execution unit according to the action code, executes the action and outputs the modified packet header information and the tuple data information to the lower-level matching-action logic circuit.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A processing method of a matching action table based on FPGA is characterized in that:
the input signal of the matching action table based on the FPGA comprises packet header information and tuple data information;
the processing method of the matching action table based on the FPGA comprises the following steps:
CPU configures searching table item;
when the packet header information and the tuple data information of a network packet are input, extracting and searching keywords from the packet header information and the tuple data information;
sending the keywords into a lookup table for matching lookup;
after the searching is finished, the searching table outputs a signal of successful or failed matching and matching result data;
if the matching is successful, selecting an action execution unit to execute the action according to the action code in the matching result, carrying out logic operation, arithmetic operation, modification and addition operation on the header protocol field and the tuple data, and finally sending the newly generated header protocol field and the tuple data to a lower-level matching action table for subsequent packet processing.
2. The method for processing the matching action table based on the FPGA of claim 1, wherein the method comprises the following steps: further comprising: and (3) beating the input packet header information and tuple data registers, and aligning the time sequence of the output packet header information and tuple data after beating with the matching result signal output by the lookup table module.
3. The method for processing the matching action table based on the FPGA of claim 2, wherein the method comprises the following steps: the CPU configures a lookup table entry, firstly writes the content of the table entry to be configured into a data writing register in a CPU configuration module, then writes a table entry index register and a read-write selection register of the CPU configuration module, and finally writes a table entry access start flag bit of the CPU configuration module; wherein the entry content includes a lookup key, an action code, and action data.
4. The method for processing the matching action table based on the FPGA of claim 1, wherein the method comprises the following steps: the packet header information comprises protocol fields of each protocol layer of the packet header analyzed by the preceding-stage message analyzer and effective zone bits of the protocol fields; the meta-group data information comprises an input port number, an output port number, a packet length, a priority, a multicast group number and user-defined packet information of the data packet.
5. The utility model provides a logic circuit of matching action table based on FPGA which characterized in that: the input signal of the matching action table based on the FPGA comprises packet header information and tuple data information;
the logic circuit of the FPGA-based matching action table comprises:
the CPU configuration module is used for configuring the lookup table items, and comprises read operation and write operation of the lookup table module;
the lookup key word construction module is used for generating lookup key words and outputting the lookup key words to the lookup table module;
the lookup table module is used for matching the input lookup key words with the matching key words in the lookup table items and outputting a matching success signal, a matching failure signal and matching result data to the action execution module;
and the action execution module executes actions according to the action codes in the matching result, performs logical operation, arithmetic operation, modification and addition operation on the header protocol field and the tuple data, and finally sends the newly generated header protocol field and the tuple data to a lower-level matching action table for subsequent packet processing.
6. The logic circuit of claim 5, further comprising:
the packet header and tuple data register module is used for beating the input packet header information and tuple data register and aligning the time sequence of the output packet header information and tuple data after beating with the matching result signal output by the lookup table module;
the action execution module receives matching success and failure signals and matching result data from the lookup table module, receives packet header information and tuple data from the packet header and tuple data register module, and executes an action according to an action code in a matching result.
7. The logic circuit of claim 5, wherein: the packet header information comprises protocol fields of each protocol layer of the packet header analyzed by the preceding-stage message analyzer and effective zone bits of the protocol fields; the metadata group data information comprises an input port number, an output port number, a packet length, a priority, a multicast group number and user-defined packet information of a data packet;
the CPU configuration module writes the contents of the table entries to be configured into a data writing register in the CPU configuration module, then writes a table entry index register and a read-write selection register of the CPU configuration module, and finally writes a table entry access start flag bit of the CPU configuration module; wherein the entry content includes a lookup key, an action code, and action data.
8. An apparatus comprising a processor and a memory coupled, characterized in that: the processor is used for executing the computer program stored in the memory to execute the processing method of the matching action table based on the FPGA according to any one of claims 1-4.
9. A computer-readable storage medium, characterized in that the computer-readable storage medium comprises a computer program for performing the method of processing the FPGA-based matching action table of any one of claims 1 to 4 when the computer program runs on a computer.
10. A design method of a logic circuit of a matching action table based on an FPGA is characterized by comprising the following steps:
instantiating a search key construction module, calculating the bit width of a search key in a P4 program, and defining search key signals with the same bit width; according to the search key defined by the P4 program, assigning a packet header protocol field or a certain tuple data field to a search key signal;
instantiating a CPU configuration module, calculating bit widths of search keywords, action codes and action data in a P4 program, and defining data writing signals and data reading signals of a lookup table module with the same bit width; calculating the bit width of the table entry size, and defining the table entry index signals with the same bit width;
selecting a statement according to a search algorithm in a P4 program, selecting a corresponding search module for instantiation, calculating the bit width of a search keyword in the P4 program, and defining search keyword input signals with the same bit width; calculating bit widths of action data and action execution unit quantity in the P4 program, and defining matching result data output signals with the same bit width;
instantiating a packet header and tuple data register module, selecting a statement according to a search algorithm in a P4 program, and setting a beating level parameter value corresponding to the search module;
instantiating an action execution module, wherein each action of the lookup table defined in the P4 program is instantiated into an action execution unit;
connecting the packet header information and the tuple data information of the input signals matched with the action table to a search keyword construction module and a packet header and tuple data register module; connecting a search key word signal output by a search key word construction module to a search table module, and connecting a table entry read-write signal output by a CPU configuration module to the search table module; connecting the matching success signal, the matching failure signal and the matching result data signal output by the lookup table module to the action execution module, and connecting the packet header, the packet header output by the tuple data register module and the tuple data signal to the action execution module;
after the module connection is completed, an FPGA logic circuit with the function of a P4 definition lookup table is obtained.
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