CN113037421A - Method, communication device, communication system, and storage medium for clock synchronization - Google Patents
Method, communication device, communication system, and storage medium for clock synchronization Download PDFInfo
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- CN113037421A CN113037421A CN202110569302.0A CN202110569302A CN113037421A CN 113037421 A CN113037421 A CN 113037421A CN 202110569302 A CN202110569302 A CN 202110569302A CN 113037421 A CN113037421 A CN 113037421A
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- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
- H04J3/0641—Change of the master or reference, e.g. take-over or failure of the master
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Abstract
Embodiments of the present disclosure relate to methods, communication devices, communication systems, and computer storage media for clock synchronization, and relate to the field of communications. According to the method, at a current communication device, if it is determined that a master clock lane does not exist for a current network associated with a current lane, it is determined whether a local other lane is in a master clock state; if it is determined that the local other lane is not in the master clock state: determining a current channel as a main clock channel; determining whether a master clock timing channel exists for other networks associated with the local other channels; and clock synchronizing the master clock channel with the master clock time base channel if it is determined that the master clock time base channel exists in the other network. Therefore, the communication equipment can independently perform clock synchronization in multiple channels, and hot redundancy backup of a plurality of main clock communication equipment is realized.
Description
Technical Field
Embodiments of the present disclosure relate generally to the field of communications, and more particularly, to a method, a communication device, a communication system, and a computer storage medium for clock synchronization.
Background
A bus system of a real-time communication system generally adopts periodic communication, all devices in the system are synchronized under the same time reference, one node in the system is a master clock node providing the time reference, other nodes are slave clock nodes, and all the slave clock nodes need to perform clock synchronization communication with the master clock node to realize the time synchronization of the whole network. Therefore, if the slave device loses communication with the master clock node, the slave device can immediately fall into a paralysis state, in practical application, a multi-channel redundancy mode is often adopted to prevent each node from losing connection with the master clock node, but if the master clock node fails, the whole system still can immediately fall into the paralysis state, and therefore the improvement on the network clock management reliability is very important.
Disclosure of Invention
A method, a communication device, a communication system and a computer storage medium for clock synchronization are provided, which enable the communication device to independently perform clock synchronization in multiple channels and realize hot redundancy backup of a plurality of master clock communication devices.
According to a first aspect of the present disclosure, a method for clock synchronization is provided. The method comprises the following steps: at the current communication device, if it is determined that the current network associated with the current channel does not have a master clock channel, determining whether the local other channel is in a master clock state; if it is determined that the local other lane is not in the master clock state: determining a current channel as a main clock channel; determining whether a master clock timing channel exists for other networks associated with the local other channels; and clock synchronizing the master clock channel with the master clock time base channel if it is determined that the master clock time base channel exists in the other network.
According to a second aspect of the present disclosure, a communication device is provided. The communication device includes: a plurality of channels; and a plurality of clock synchronization modules coupled to the plurality of channels, each clock synchronization module of the plurality of clock synchronization modules configured to perform the method according to the first aspect.
In a third aspect of the present disclosure, there is provided a communication system comprising: a plurality of communication devices, each of the plurality of communication devices including a plurality of channels and a plurality of clock synchronization modules correspondingly coupled to the plurality of channels, the plurality of communication devices forming a plurality of redundant networks via the plurality of channels in each of the plurality of communication devices, each of the plurality of redundant networks including a plurality of corresponding channels in the plurality of communication devices; and each of the plurality of clock synchronization modules is configured to perform the method according to the first aspect for implementing a plurality of master clock device redundancies in a communication system via a plurality of lanes.
In a fourth aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored which, when executed by a processor, implements a method according to the first aspect of the present disclosure.
It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.
Drawings
The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements.
Fig. 1 is a schematic block diagram of a communication device 100 according to an embodiment of the present disclosure.
Fig. 2 is a schematic diagram of a method 200 for clock synchronization according to an embodiment of the present disclosure.
Fig. 3 is a schematic diagram of a method 300 for clock synchronization according to an embodiment of the present disclosure.
Fig. 4 is a schematic diagram of a method 400 for clock synchronization according to an embodiment of the present disclosure.
Fig. 5 is a schematic diagram of a redundant communication network 500 according to an embodiment of the present disclosure.
Fig. 6 is a schematic block diagram of a redundant communication network 600 in accordance with an embodiment of the present disclosure.
Fig. 7 is a schematic block diagram of a redundant communication network 700 in accordance with an embodiment of the present disclosure.
Detailed Description
Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.
The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.
As described above, there is a need to improve the reliability of network clock management. According to the traditional scheme, network equipment is divided into main clock equipment, second priority main clock equipment and slave clock equipment, the second priority main clock equipment replaces the main clock equipment when the main clock equipment fails to work, the second priority main clock equipment becomes the main clock equipment, so that redundant backup (double-equipment redundancy) of the main clock equipment is realized, however, a time difference that the main clock equipment does not exist in a network exists in the switching process of the second priority main clock equipment, namely, the second priority main clock equipment firstly confirms that the identity of the second priority main clock equipment can be converted into the main clock equipment after the main clock equipment cannot be received in a preset macro period, the basis of time synchronization in the network is completely lost in the period, communication is in an uncertain state, and communication cannot be guaranteed to be influenced.
In addition, in the conventional scheme, the slave clock device needs to perform a synchronization process to the master clock device and the second priority master clock device respectively, and needs to repeatedly send messages for communication, and in the process, messages related to clock synchronization are sent for multiple times, so that network bandwidth is occupied.
In design, the traditional scheme has poor flexibility, identity conversion relations of the master clock device, the second priority master clock device and the slave clock device are closely connected, and if a third priority master clock device and a fourth priority master clock device are required to be added for higher redundancy in an actual application scene, the design is changed greatly, and the whole design is basically modified once from the lowest layer.
To address, at least in part, one or more of the above issues and other potential issues, an example embodiment of the present disclosure proposes a scheme for clock synchronization. In this scheme, at a current communication device, if it is determined that a master clock lane does not exist for a current network associated with a current lane, it is determined whether a local other lane is in a master clock state; if it is determined that the local other lane is not in the master clock state: determining a current channel as a main clock channel; determining whether a master clock timing channel exists for other networks associated with the local other channels; and clock synchronizing the master clock channel with the master clock time base channel if it is determined that the master clock time base channel exists in the other network. In this way, the communication equipment can independently perform clock synchronization in multiple channels, and hot redundancy backup of a plurality of master clock communication equipment is realized.
Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings.
Fig. 1 shows a schematic block diagram of a communication device 100 according to an embodiment of the present disclosure. The communication device 100 may include a plurality of clock synchronization modules 110-1 through 110-n (hereinafter collectively referred to as 110) and a plurality of channels 120-1 through 120-n (hereinafter collectively referred to as 120). The plurality of clock synchronization modules 110 are coupled to the plurality of channels 120. The clock synchronization module 110 may be implemented by software, hardware or a combination of software and hardware.
The plurality of channels 120 are redundant channels. The plurality of channels 120 are associated with a plurality of networks that are redundant networks to each other. For example, all channels 120-1 of all connected communication devices constitute network A, all channels 120-2 of all communication devices constitute network B, and so on, which are redundant networks of each other. There is one master clock lane (also referred to as a lane in a master clock state) in each network that provides a synchronous clock to the other lanes (referred to as slave clock lanes) in the network. Each network is independent of the other and each communication device has only one master clock channel. And a master clock time-base channel exists in all the master clock channels, and provides a synchronous clock for the network where the master clock time-base channel exists, and also indirectly provides a synchronous clock for the master clock channels in all other networks, so that the clock synchronization of the whole system is realized.
Each clock synchronization module 110 is responsible for clock synchronization of a corresponding channel and is independent of each other, e.g., clock synchronization module 110-1 is responsible for clock synchronization of a corresponding channel 120-1. The clock synchronization module 110 may, in addition to completing the clock synchronization of the corresponding channel, store the synchronization status of the network in which the channel is located, such as whether a master clock channel, a master clock time base channel, a logical address of the communication device in which the master clock channel is located, etc., exists in the network, and may provide these information to other clock synchronization modules 110 in the same communication device 100.
Each clock synchronization module 110 may be configured to determine whether a local other lane is in a master clock state if it is determined that a master clock lane does not exist for the current network associated with the current lane; if it is determined that the local other lane is not in the master clock state: determining a current channel as a main clock channel; determining whether a master clock timing channel exists for other networks associated with the local other channels; and clock synchronizing the master clock channel with the master clock time base channel if it is determined that the master clock time base channel exists in the other network.
Therefore, when the communication equipment comprising the main clock channel fails, the redundant network where the main clock channel is located is only affected briefly, and other networks are not affected, so that the reliability of the whole communication network is guaranteed.
Fig. 2 shows a flow diagram of a method 200 for clock synchronization according to an embodiment of the present disclosure. For example, the method 200 may be performed by any of the clock synchronization modules 110 in the communication device 100 shown in fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or may omit blocks shown, as the scope of the present disclosure is not limited in this respect.
At block 202, the clock synchronization module 110 determines whether a master clock lane exists for a current network associated with a current lane.
It should be understood that the current channel is the channel where the clock synchronization module 110 is located, and the clock synchronization module 110 is responsible for clock synchronization of the current channel. The current network associated with the current channel is the network in which the current channel is located.
The master clock lane may also be referred to as the lane in the master clock state.
If the clock synchronization module 110 determines at block 202 that the current network associated with the current lane does not have a master clock lane, then at block 204 it is determined whether the local other lane is in a master clock state.
The local other channel refers to one or more channels other than the current channel in the same communication device 110.
If the clock synchronization module 110 determines at block 204 that the local other lane is not in the master clock state, then at block 206, the current lane is determined to be the master clock lane.
After determining the current channel as the master clock channel, the clock synchronization module 110 will provide clock synchronization for the current network associated with the current channel.
In some embodiments, if the clock synchronization module 110 determines that the local other lane is not in the master clock state at block 204, the clock synchronization module 110 may determine whether the logical address of the current communication device among all communication devices in the current network is the smallest and determine the current lane as the master clock lane if the clock synchronization module 110 determines that the logical address of the current communication device among all communication devices in the current network is the smallest.
At block 208, the clock synchronization module 110 determines whether a master clock timing channel exists for other networks associated with the local other channels.
The current network and the other network may be redundant networks.
If the clock synchronization module 110 determines that a master clock timing channel exists for the other networks at block 208, the master clock channel is clock synchronized with the master clock timing channel at block 210.
For example, the time of the master clock lane may be replaced every communication cycle with the time of a local slave clock lane synchronized with the master clock time base lane.
Therefore, the communication equipment can independently perform clock synchronization on multiple channels, different channels have different main clock equipment, the communication of one channel can be influenced only by the fault of any 1 main clock equipment within a very short time, and other redundant channels are not influenced at all, so that the reliability of the whole communication network is ensured. In addition, because all channels independently carry out the synchronization process, the synchronous messages of different channels do not influence each other, and the synchronous messages cannot be increased due to the increase of the master clock equipment in the network. And because all channels independently carry out the synchronization process, the number of the main clock backup devices can be flexibly increased by adding the redundant channels.
Referring next to fig. 3, in some embodiments, if the clock synchronization module 110 determines at block 208 that a master clock timing channel does not exist for other networks, then at block 302 it is determined whether the logical address of the current communication device 100 is minimal among all the communication devices in which all the detected master clock channels are located.
It should be understood that all communication devices herein include the current communication device, since after the current channel is determined to be the master clock channel, the current communication device is also the communication device where the master clock channel is located. The clock synchronization module 110 may obtain from the local other clock synchronization module 110 the logical addresses of all other communication devices on other networks associated with the local other channel where all other master clock channels are located, the logical address of the current communication device being known to the clock synchronization module 110.
If the clock synchronization module 110 determines at block 302 that the logical address of the current communication device 110 is the smallest among all the communication devices in which all the detected master clock channels are located, the master clock channel is determined at block 304 as the master clock timing channel.
If the clock synchronization module 110 determines at block 302 that the logical address of the current communication device is not the smallest of all the communication devices in which all the detected master clock channels are located, then it is detected at block 306 whether a master clock timing channel is present in the other network.
If the presence of the master clock timing channel in the other network is detected at block 306, the master clock channel is clock synchronized with the master clock timing channel at block 308.
If the presence of a master clock timing channel in other networks is not detected at block 306, the detection step at block 306 may continue.
The process of clock synchronization between the master clock channel and the master clock time-base channel can be referred to above, and is not described here again.
Therefore, even if the communication equipment where the master clock time-base channel is located fails, other master clock time-base channels can regenerate one master clock time-base channel, the process still cannot influence other networks, and finally the master clock equipment redundancy hot backup of the whole network is achieved.
Referring next to FIG. 4, in some embodiments, if the clock synchronization module 110 determines that a master clock lane exists for the current network at block 202, or if the local other lanes are in a master clock state at block 204, the current lane is determined to be a slave clock lane at block 402.
At block 404, the clock synchronization module 110 clock synchronizes the current channel with the master clock channel.
At block 406, the clock synchronization module 110 obtains the logical address of the communication device where the master clock channel is located.
At block 408, the clock synchronization module 110 shares the acquired logical address with the local other lanes.
In particular, the clock synchronization module 110 may share the retrieved logical address with other clock synchronization modules on other channels locally.
In some embodiments, after the current channel is clock synchronized with the master clock channel, the clock synchronization module 110 may also continue to detect whether the master clock channel is present in the current network, and return to block 204 if the master clock channel is not detected in the current network.
Therefore, when the main clock channel exists in the current network, the current channel is determined to be the slave clock channel to realize synchronization with the main clock channel, and the logic address of the communication equipment where the main clock channel is located is recorded for sharing with other local channels. In addition, when other local channels are in the master clock state, the current channel is also determined as a slave clock channel
In some embodiments, the clock synchronization module 110 may also, after the master clock channel is synchronized with the master clock timing channel at block 210, return to step 208 to determine whether the master clock timing channel is present in the other network, and if the clock synchronization module 110 determines that the master clock timing channel is not present in the other network at block 208, perform the flow as shown in fig. 3.
An embodiment of the present disclosure also provides a communication system, including: a plurality of communication devices, each of the plurality of communication devices including a plurality of channels and a plurality of clock synchronization modules coupled to the plurality of channels. The plurality of communication devices form a plurality of redundant networks via a plurality of channels in each communication device, each redundant network of the plurality of redundant networks including a plurality of corresponding channels in the plurality of communication devices. Each of the plurality of clock synchronization modules may be configured to perform the method as described above for implementing multiple master clock device redundancy in a communication system via multiple channels. The following examples are given.
Fig. 5 shows a schematic diagram of a redundant communication network 500 according to an embodiment of the present disclosure. As shown in fig. 5, the redundant communication network 500 includes 4 communication devices 510 and 540. Each communication device comprises two channels A and B, and service data is redundantly communicated on the AB channel. All the channels A form a network A, and all the channels B form a network B. The a and B networks are redundant to each other.
The a channel of the communication device 510 is the master clock timebase channel of the entire network 500 and the B channel of the communication device 540 is the master clock channel of the B network. The A-channel of the communication device 510 provides a synchronous clock for the A-channel of the communication device 510 and 540, and the B-channel (master clock channel) of the communication device 540 indirectly through the A-channel of the communication device 540. The B channel of the communication device 540 provides a synchronous clock for the communication device 510 and the B channel of 540.
Referring next to fig. 6, fig. 6 shows a schematic diagram of a redundant communication network 600 in the event of a communication device failure according to an embodiment of the present disclosure.
As shown in fig. 6, when the communication device 640 whose B channel is the main clock channel of the B network fails, the a channel (main clock time-base channel) of the communication device 610 is not affected, and thus the a network is not affected, so that the communication between the remaining communication devices 610 and 630 in the network 600 is not affected. The B-channel of the communication device 620 with smaller logical address becomes a new main clock channel to provide a synchronous clock for the B-network because the B-network loses the main clock channel and falls into a temporary paralysis, and then the communication devices 620 and 630 except the communication device 610 in the network 5600 become the new main clock channel. It is assumed here that logical address of communication device 610 < logical address of communication device 620 < logical address of communication device 630 < logical address of communication device 640. Because the master clock lane already exists for the communication device 610, in order to avoid two master clock lanes for the same communication device, the synchronous clock is provided to the B network by the B lane of the communication device 620, referred to as the master clock lane. And the master clock timebase channel of the communication device 610 indirectly provides the synchronized clock for the B channel of the communication device 620 through the a channel of the communication device 620.
Referring next to fig. 7, fig. 7 shows a schematic diagram of a redundant communication network 700 in the event of a communication device failure according to an embodiment of the present disclosure.
As shown in fig. 7, a communication device 710 having an a-channel that is the master clock timing channel of the entire network 700 fails, and a communication device 740 having a B-channel that is the master clock timing channel can detect that the entire network 700 has lost the master clock timing channel. The B channel of the communication device 740 is referred to as the master clock timebase channel since the logical address of the communication device 740 is smallest among all the communication devices in which all the master clock channels are detected (at this time only the communication device 740). At this time, the logical address of the communication device 720 in the communication devices 720 and 740 is the smallest, and the a channel of the communication device 720 is called as a master clock channel, and provides a synchronous clock for the a channels of all the communication devices in the a network. The B-channel of the communication device 740 serves as the master clock timebase channel to provide a synchronized clock for the B-channels of all communication devices in the B-network, while the a-channel (master clock channel) of the communication device 720 is provided indirectly through the B-channel of the communication device 720.
It should be understood that although fig. 5-7 show 4 communication devices each including 2 channels, this is by way of example only, more or fewer communication devices may be included, and more channels in a communication device may be included, as the scope of the present disclosure is not limited in this respect. For example, if each communication device has n redundant channels to form an n redundant network, n devices providing synchronous clocks may exist in the network, and the communication capability of the entire network is not affected by the failure of any n-1 communication devices.
Therefore, when the communication equipment comprising the main clock channel fails, the redundant network where the main clock channel is located is only affected briefly, and other networks are not affected, so that the reliability of the whole communication network is guaranteed. Even if the communication equipment where the master clock time-base channel is located fails, other master clock time-base channels can regenerate one master clock time-base channel, the process still cannot influence other networks, and finally the master clock equipment redundancy hot backup of the whole network is achieved.
In addition, because all channels independently carry out the synchronization process, the synchronous messages of different channels do not influence each other, and the synchronous messages cannot be increased due to the increase of the master clock equipment in the network. And because all channels independently carry out the synchronization process, the number of the main clock backup devices can be flexibly increased by adding the redundant channels.
The present disclosure relates to methods, apparatuses, systems, electronic devices, computer-readable storage media and/or computer program products. The computer program product may include computer-readable program instructions for performing various aspects of the present disclosure.
The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.
The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.
The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).
Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.
These computer-readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.
The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.
The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.
Claims (11)
1. A method for clock synchronization, comprising:
at the current communication device, if it is determined that the current network associated with the current channel does not have a master clock channel, determining whether the local other channel is in a master clock state;
if it is determined that the local other lane is not in the master clock state:
determining the current channel as the master clock channel;
determining whether a master clock timing channel exists for other networks associated with the local other channel; and
clock synchronizing the master clock channel with the master clock time base channel if it is determined that the master clock time base channel exists for the other network.
2. The method of claim 1, further comprising:
determining whether a logical address of the current communication device is minimum among all communication devices in which all detected master clock channels are located, if it is determined that the master clock time base channel does not exist in the other network; and
and if the logic address of the current communication equipment in all the communication equipment in which all the detected main clock channels are positioned is determined to be the minimum, determining the main clock channel as the main clock time base channel.
3. The method of claim 2, further comprising:
detecting whether the master clock time base channel is present in the other network if it is determined that the logical address of the current communication device is not the smallest among all the communication devices in which all the detected master clock channels are present; and
and if the master clock time base channel is detected to be present in the other networks, carrying out clock synchronization on the master clock channel and the master clock time base channel.
4. The method of claim 1, further comprising:
if it is determined that the master clock lane exists for the current network, or if it is determined that the local other lane is in the master clock state:
determining the current channel as a slave clock channel; and
and carrying out clock synchronization on the current channel and the master clock channel.
5. The method of claim 4, further comprising:
if it is determined that the master clock lane exists for the current network, or if it is determined that the local other lane is in the master clock state:
acquiring a logic address of communication equipment where the main clock channel is located; and
sharing the acquired logical address with the local other channel.
6. The method of claim 1, further comprising:
determining whether the master clock timing channel exists for the other network after the master clock channel is synchronized with the master clock timing channel;
determining whether a logical address of the current communication device is minimum among all communication devices in which all detected master clock channels are located, if it is determined that the master clock time base channel does not exist in the other network; and
and if the logic address of the current communication equipment in all the communication equipment in which all the detected main clock channels are positioned is determined to be the minimum, determining the main clock channel as the main clock time base channel.
7. The method of claim 1, wherein clocking the master clock channel with the master clock time base channel comprises:
each communication cycle replaces the time of the master clock lane with the time of a local slave clock lane synchronized with the master clock time base lane.
8. The method of claim 1, wherein the current network and the other network are redundant networks.
9. A communication device, comprising:
a plurality of channels; and
a plurality of clock synchronization modules coupled to the plurality of lanes, each clock synchronization module of the plurality of clock synchronization modules configured to perform the method of any of claims 1-8.
10. A communication system, comprising:
a plurality of communication devices, each of the plurality of communication devices comprising a plurality of channels and a plurality of clock synchronization modules correspondingly coupled to the plurality of channels, the plurality of communication devices composing a plurality of redundant networks via the plurality of channels in each communication device, each of the plurality of redundant networks comprising a plurality of corresponding channels in the plurality of communication devices; and
each clock synchronization module of the plurality of clock synchronization modules is configured to perform the method of any of claims 1-8 for implementing a plurality of master clock device redundancies in the communication system via the plurality of lanes.
11. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-8.
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| CN105227289A (en) * | 2015-08-24 | 2016-01-06 | 卡斯柯信号有限公司 | A kind of clock synchronizing method of quick precise and safety and system |
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| CN105227289A (en) * | 2015-08-24 | 2016-01-06 | 卡斯柯信号有限公司 | A kind of clock synchronizing method of quick precise and safety and system |
| CN112821979A (en) * | 2021-04-16 | 2021-05-18 | 浙江国利信安科技有限公司 | Decentralized fast network time synchronization method |
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| CN113346974A (en) * | 2021-08-06 | 2021-09-03 | 浙江国利信安科技有限公司 | Method, apparatus, communication system and storage medium for clock synchronization |
| CN113346974B (en) * | 2021-08-06 | 2022-08-26 | 浙江国利信安科技有限公司 | Method, apparatus, communication system and storage medium for clock synchronization |
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