CN113346974A

CN113346974A - Method, apparatus, communication system and storage medium for clock synchronization

Info

Publication number: CN113346974A
Application number: CN202110899571.3A
Authority: CN
Inventors: 陈建飞; 王克炜; 顾昊; 王迎
Original assignee: Zhejiang Guoli Xin'an Technology Co ltd
Current assignee: Zhejiang Guoli Xin'an Technology Co ltd
Priority date: 2021-08-06
Filing date: 2021-08-06
Publication date: 2021-09-03
Anticipated expiration: 2041-08-06
Also published as: CN113346974B

Abstract

Embodiments of the present disclosure relate to a method, an apparatus, a communication system, and a storage medium for clock synchronization, and relate to the field of communications. According to the method, at a slave clock device, synchronization information with a master clock device and a plurality of items of synchronization information with a plurality of master clock devices, the plurality of master clock devices being synchronized with the master clock device, are determined; receiving a first message periodically sent by a master clock device and a plurality of second messages periodically sent by the master clock device at a first period, wherein the first message indicates a master clock state and a message sending time, and each second message indicates the master clock state and the message sending time; determining a first device from the master clock device and the plurality of master clock devices; and performing clock synchronization with the first device at a first period based on synchronization information with the first device and a message transmission time of a message received from the first device. Thus, the slave clock devices can synchronize as long as at least one master clock or the total master clock is preserved.

Description

Method, apparatus, communication system and storage medium for clock synchronization

Technical Field

Embodiments of the present disclosure relate generally to the field of communications, and more particularly, to a method, apparatus, communication system, and storage medium for clock synchronization.

Background

The distributed time-triggered network is a protocol stack composed of multiple protocols with high real-time performance, each node device is undifferentiated (the same in software and hardware), and each node device is connected through a cable to form multiple topological structures such as star-shaped and ring-shaped structures. Each node device selects one node device as a master clock through a master clock competition mechanism, and other node devices are synchronized with the master clock. Therefore, there must be and only one deterministic master clock device in the network as the time base for all devices.

The communication data scheduling message of the time-triggered network is based on time triggering, and each device schedules data according to time, so that synchronization among the devices in the network is very important for data scheduling. The synchronization process uses PTP protocol, PTP informs each slave node device of the time information of the master node by transmitting the special data frame carrying the time stamp in the Ethernet data line, and the slave nodes calculate the time deviation of the master node and the slave node according to the received time information to adjust the local clock of the slave nodes, thereby realizing the time synchronization of the whole network.

Conventionally, time triggered networks require that the individual terminal devices synchronize at intervals, and there must be and only one deterministic master clock device in the network as the time base for all devices. When the master clock fails to send master clock messages due to faults and a new master clock is generated, each terminal device needs to be synchronized with the new master clock. During the period, the data scheduling of each terminal device of the network is stopped, and the data scheduling is started again after each device is synchronized with the master clock.

Disclosure of Invention

A method for clock synchronization, a slave clock device, a master clock device, a communication system and a computer storage medium are provided, which are capable of synchronizing the slave clock devices as long as at least one master clock device or a master clock device is reserved.

According to a first aspect of the present disclosure, a method for clock synchronization is provided. The method comprises the following steps: determining, at a slave clock device, synchronization information with a master clock device and a plurality of items of synchronization information with a plurality of master clock devices, the plurality of master clock devices being clock synchronized with the master clock device; receiving a first message periodically transmitted by a master clock device and a plurality of second messages periodically transmitted by the master clock device at a first period, wherein the first message indicates a master clock state and a message transmission time, and each of the plurality of second messages indicates the master clock state and the message transmission time; determining a first device from the master clock device and the plurality of master clock devices; and performing clock synchronization with the first device at a first period based on synchronization information with the first device and a message transmission time of the first message or the second message received from the first device.

According to a second aspect of the present disclosure, a method for clock synchronization is provided. The method comprises the following steps: determining, at a master clock device, synchronization information with a master clock device; receiving a first message periodically sent by a master clock device in a first period, wherein the first message indicates the state of the master clock and the message sending time; performing clock synchronization with a master clock device in a first period based on the synchronization information and the message transmission time; and periodically sending a second message to the slave clock device, the second message indicating a master clock status and a message sending time, so that the slave clock device determines the first device to perform clock synchronization from the master clock device, the master clock device and the other master clock devices.

According to a third aspect of the present disclosure, a slave clock device is provided. The slave clock device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method according to the first aspect of the disclosure.

According to a fourth aspect of the present disclosure, a master clock device is provided. The master clock device includes: at least one processor; and a memory communicatively coupled to the at least one processor; wherein the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method according to the second aspect of the disclosure.

In a fifth aspect of the present disclosure, there is provided a communication system comprising: a plurality of slave clock devices according to the third aspect of the present disclosure; a plurality of master clock devices according to a fourth aspect of the present disclosure; and an overall master clock device configured to periodically send messages to the plurality of slave clock devices and the plurality of master clock devices, the messages indicating an overall master clock status and a message send time.

In a sixth aspect of the present disclosure, a computer readable storage medium is provided, having stored thereon a computer program which, when executed by a processor, implements a method according to the first or second aspect of the present disclosure.

It should be understood that the statements in this section do not necessarily identify key or critical features of the embodiments of the present disclosure, nor do they limit the scope of the present disclosure. Other features of the present disclosure will become apparent from the following description.

Drawings

The above and other features, advantages and aspects of various embodiments of the present disclosure will become more apparent by referring to the following detailed description when taken in conjunction with the accompanying drawings. In the drawings, like or similar reference characters designate like or similar elements.

Fig. 1 is a schematic block diagram of a communication system 100 in accordance with an embodiment of the present disclosure.

Fig. 2 is a schematic diagram of a method 200 for clock synchronization according to an embodiment of the present disclosure.

Fig. 3 is a schematic diagram of a method 300 for clock synchronization according to an embodiment of the present disclosure.

Fig. 4 is a schematic block diagram of a slave clock device 400 according to an embodiment of the present disclosure.

Fig. 5 is a schematic block diagram of a master clock device 500 according to an embodiment of the present disclosure.

Fig. 6 is a schematic block diagram of an electronic device for implementing a method for clock synchronization in accordance with an embodiment of the present disclosure.

Detailed Description

Exemplary embodiments of the present disclosure are described below with reference to the accompanying drawings, in which various details of the embodiments of the disclosure are included to assist understanding, and which are to be considered as merely exemplary. Accordingly, those of ordinary skill in the art will recognize that various changes and modifications of the embodiments described herein can be made without departing from the scope and spirit of the present disclosure. Also, descriptions of well-known functions and constructions are omitted in the following description for clarity and conciseness.

The term "include" and variations thereof as used herein is meant to be inclusive in an open-ended manner, i.e., "including but not limited to". Unless specifically stated otherwise, the term "or" means "and/or". The term "based on" means "based at least in part on". The terms "one example embodiment" and "one embodiment" mean "at least one example embodiment". The term "another embodiment" means "at least one additional embodiment". The terms "first," "second," and the like may refer to different or the same object. Other explicit and implicit definitions are also possible below.

As described above, each terminal device needs to synchronize with a new master clock after the master clock generates a new master clock during a period in which the master clock cannot transmit master clock messages due to a fault. During the period, the data scheduling of each terminal device of the network is stopped, and the data scheduling is started again after each device is synchronized with the master clock.

To address, at least in part, one or more of the above issues and other potential issues, an example embodiment of the present disclosure proposes a scheme for clock synchronization. In the scheme, at a slave clock device, determining synchronization information with a master clock device and a plurality of items of synchronization information with a plurality of master clock devices, wherein the plurality of master clock devices are clock-synchronized with the master clock device; receiving a first message periodically transmitted by a master clock device and a plurality of second messages periodically transmitted by the master clock device at a first period, wherein the first message indicates a master clock state and a message transmission time, and each of the plurality of second messages indicates the master clock state and the message transmission time; determining a first device from the master clock device and the plurality of master clock devices; and performing clock synchronization with the first device at a first period based on synchronization information with the first device and a message transmission time of the first message or the second message received from the first device.

Determining, at a master clock device, synchronization information with a master clock device; receiving a first message periodically sent by a master clock device in a first period, wherein the first message indicates the state of the master clock and the message sending time; performing clock synchronization with a master clock device in a first period based on the synchronization information and the message transmission time; and periodically sending a second message to the slave clock device, the second message indicating a master clock status and a message sending time, so that the slave clock device determines the first device to perform clock synchronization from the master clock device, the master clock device and the other master clock devices.

In this way, slave clock devices can be synchronized as long as at least one master clock device or the master clock device as a whole is reserved.

Hereinafter, specific examples of the present scheme will be described in more detail with reference to the accompanying drawings.

Fig. 1 shows a schematic block diagram of a communication system 100 according to an embodiment of the present disclosure. The communication system 100 may include a master clock device 110, a plurality of master clock devices 120-1 through 120-3 (hereinafter collectively 120), and a plurality of slave clock devices 130-1 through 130-3 (hereinafter collectively 130). It should be understood that although only 2 master clock devices and 3 slave clock devices are shown in fig. 1, this is by way of example only and that more or fewer master clock devices may be included and more or fewer slave clock devices may be included, as the scope of the present disclosure is not limited in this respect.

As shown in FIG. 1, master clock master 110, master clock 120, and slave clock 130 each include two ports A and B, respectively, connected to two switches 140-1 and 140-2, respectively, to implement a dual star topology. It should be understood that this is by way of example only, and that other star topologies may be used, or other topologies, such as a ring topology.

Master clock master device 110 may periodically send a first message to master clock master devices 120 and slave clock slave devices 130 indicating the master clock master status and the time of message transmission.

Master clock device 120 may determine synchronization information with master clock device 110. Upon receiving the first message at the first cycle, master clock device 120 may clock-synchronize with master clock device 110 at the first cycle based on synchronization information with master clock device 110 and a message transmission time of the first message. Master clock device 120 may also periodically send a second message to the plurality of slave clock devices 130, the second message indicating the master clock status and the message send time. It will be appreciated that the period for sending the second message is the same as the period for sending the first message by the master clock master.

Slave clock device 130 may determine synchronization information with master clock device 110 and multiple items of synchronization information with multiple master clock devices 120. After receiving the first message and the plurality of second messages in the first period, the slave clock device 130 may determine the first device from the master clock device 110 and the plurality of master clock devices 120 and perform clock synchronization with the first device in the first period based on synchronization information with the first device and a message transmission time of the first message or the second message received from the first device.

Therefore, as the master clock equipment is synchronous with the total master clock equipment, the slave clock equipment can realize the synchronization as long as one master clock equipment or the total master clock equipment is reserved, thereby ensuring the synchronization of the system clocks.

In some embodiments, master clock device 110 fails or malfunctions for a second period. In the second period, master clock device 120 and slave clock device 130 do not receive a third message from master clock device 110 indicating the master clock status and the message transmission time.

For master clock device 120, it determines whether itself is the new master clock device overall based on predetermined rules. If the master clock device 120-1 determines itself to be the new master clock device, a fourth message is periodically sent to the slave clock device 130 and the other master clock devices 120, the fourth message indicating the master clock status and the message sending time, so that the slave clock device 130 determines from the new master clock device (120-1) and the other master clock devices (120-2 and 120-3) that the first device is clock synchronized and the other master clock devices (120-2 and 120-3) are clock synchronized with the new master clock device (120-1).

Master clock devices 120-2 and 120-3 receive the fourth message from new master clock master 120-1 during the third cycle and time synchronize with new master clock master 120-1 during the third cycle based on the synchronization information with new master clock master 120-1 and the message transmission time of the fourth message.

Therefore, when the master clock device fails to be called as a new master clock device, the master clock device cannot synchronize with the master clock device, 1 cycle time exists in the period, the time is short, the synchronization cannot be in an allowable range, and the scheduling is not influenced.

For the slave clock device 130, it receives a plurality of third messages from the plurality of master clock devices 120 at the second cycle, the third messages indicating the master clock status and the message transmission time. Subsequently, slave clock device 130 determines a second device from the plurality of master clock devices 120.

Next, the slave clock device 130 performs clock synchronization with the second device at a second period based on the synchronization information with the second device and the message transmission time of the third message received from the second device.

The slave clock device 130 receives the fourth message from the new master clock master device 120-1 and the second messages from the master clock devices 120-2 and 120-3 in the third period, determines the third device from the new master clock master device 120-1 and the master clock devices 120-2 and 120-3, and performs time synchronization with the third device in the third period based on the synchronization information with the third device and the message transmission time of the fourth message.

Thus, in the event of a failure of the overall master clock, the slave clock device may determine from the plurality of master clock devices that the second device is performing clock synchronization, thereby ensuring overall system synchronization.

Alternatively or additionally, in some embodiments, a new master clock device is added. For example, a new master clock device joins at a first cycle, which may determine synchronization information with master clock device 110. Upon receiving the first message in the first period, the newly joined master clock device may clock-synchronize with master clock master device 110 in the first period based on the synchronization information with master clock master device 110 and the message transmission time of the first message. The newly added master clock device may also periodically send a second message to the plurality of slave clock devices 130, the second message indicating the master clock status and the message send time.

Slave clock device 130 may determine synchronization information with master clock device 110, multiple synchronization information with master clock devices 120, and synchronization information with a newly-added master clock device. After receiving the first message and the plurality of second messages in the first period, the slave clock device 130 may determine the first device from the master clock device 110, the plurality of master clock devices 120, and the newly-added master clock device, and perform clock synchronization with the first device in the first period based on synchronization information with the first device and a message transmission time of the first message or the second message received from the first device.

The method for clock synchronization at the slave clock device 130 and the method for clock synchronization at the master clock device 120 are described below in conjunction with fig. 2 and 3, respectively.

Fig. 2 shows a flow diagram of a method 200 for clock synchronization according to an embodiment of the present disclosure. For example, method 200 may be performed by slave clock device 130 as shown in fig. 1. It should be understood that method 200 may also include additional blocks not shown and/or may omit blocks shown, as the scope of the present disclosure is not limited in this respect.

At block 202, the slave clock device 130 determines synchronization information with the master clock device 110 and multiple items of synchronization information with the plurality of master clock devices 120. Where multiple master clock devices 120 are clock synchronized with master clock device 110.

Synchronization information includes, for example, but is not limited to, network latency information, such as between slave clock device 130 and master clock device 110, and between slave clock device 130 and master clock device 120.

At block 204, the slave clock device 130 receives, at a first period, a first message periodically transmitted by the master clock device 110 and a plurality of second messages periodically transmitted by the master clock device 120, the first message indicating a master clock status and a message transmission time, each of the plurality of second messages indicating a master clock status and a message transmission time.

At block 206, slave clock device 130 determines a first device from master clock device 110 and plurality of master clock devices 120.

In some embodiments, slave clock device 130 may determine the first received or last received message from the first message and the plurality of second messages, and then take the overall master clock device or master clock device from which the determined message came as the first device.

Thereby, the first device for synchronization can be determined in the order of message reception.

It should be understood that this is only one example of determining the first device and that other ways of determining the first device may be used, as the scope of the disclosure is not limited thereto.

At block 208, the slave clock device 130 clocks with the first device for a first period based on synchronization information with the first device and a message transmission time of the first message or the second message received from the first device.

For example, if it is determined that the master clock device 110 is the first device, the slave clock device 130 performs clock synchronization with the master clock device 110 at a first period based on the synchronization information with the master clock device 110 and the message transmission time of the first message, and if it is determined that one of the master clock devices 120 is the first device, the slave clock device 130 performs clock synchronization with the master clock device 120 at the first period based on the synchronization message with the master clock device 120 and the message transmission time of the corresponding second message.

A particular clock synchronization process may, for example, adjust the local clock of the slave clock device 130 based on the message transmission time and the synchronization information to achieve clock synchronization.

In some embodiments, master clock device 110 fails, and slave clock device 130 receives, at a second cycle, a third plurality of messages periodically transmitted by master clock devices 120, each of the third plurality of messages indicating a master clock status and a message transmission time.

Subsequently, the slave clock device 130 determines a second device from the plurality of master clock devices. The process of determining the second device may be similar to the process of determining the first device, and is not described in detail.

Alternatively or additionally, in some embodiments, slave clock device 130 receives a fourth message periodically sent by the newly-joined master clock device, the fourth message indicating the master clock status. Subsequently, slave clock device 130 determines synchronization information with the newly-added master clock device for clock synchronization with the newly-added master clock device.

Thus, synchronization information can be determined with the newly added master clock device for subsequent clock synchronization therewith.

Alternatively or additionally, in some embodiments, slave clock device 130 deletes the synchronization information with master clock device 110 if it determines that the first message for master clock device 110 has not been received for N consecutive cycles. N is greater than 1.

Thus, the old synchronization information with the master clock device is deleted in time.

Fig. 3 shows a flow diagram of a method 300 for clock synchronization according to an embodiment of the present disclosure. For example, method 300 may be performed by master clock device 120 as shown in FIG. 1. It should be understood that the method may also include additional blocks not shown and/or may omit blocks shown, as the scope of the disclosure is not limited in this respect.

At block 302, master clock device 120 determines synchronization information with master clock device 110.

At block 304, master clock device 120 receives a first message periodically sent by master clock device 110 at a first period, the first message indicating a total master clock status and a message send time.

At block 306, master clock device 120 performs clock synchronization with master clock device 110 for a first period based on the synchronization information and the message transmission time.

At block 308, master clock device 120 periodically sends a second message to slave clock device 130 indicating the master clock status and the message sending time in order for the slave clock devices to determine that the first device is clock synchronized from master clock device 110, master clock device 120, and other master clock devices 120.

Therefore, the system clock synchronization can be ensured by enabling the master clock device to be synchronized with the master clock device and periodically sending the second message to the slave clock device, so that the slave clock device can select any one of the master clock device and the master clock device to be synchronized.

In some embodiments, master clock device 120 determines whether it is a new master clock master device based on a predetermined rule if it determines that a third message periodically transmitted by the master clock master device is not received at the second period, the third message indicating a master clock status and a message transmission time.

The predetermined rule includes, for example, but not limited to, the master clock device with the smallest or largest physical address or IP address among the plurality of master clock devices being the new total master clock device. It should be understood that this is by way of example only and that other suitable rules may be employed to determine the new overall master clock device.

If the master clock device 120 determines itself to be the new master clock device, a fourth message is periodically sent to the slave clock device 130 and the other master clock devices 120, the fourth message indicating the master clock status and the message sending time, so that the slave clock device 130 determines that the first device performs clock synchronization from the new master clock device and the other master clock devices, and the other master clock devices perform clock synchronization with the new master clock device.

Thus, in case of a failure of the master clock master device, it is possible to automatically determine a new master clock master device from the master clock devices such that the other master clock devices are synchronized with the new master clock master device, and the slave clock devices determine the first device to be synchronized from the new master clock master device and the other master clock devices, thereby ensuring system clock synchronization.

Alternatively or additionally, in some embodiments, master clock device 120 deletes the synchronization information with master clock device 110 if it determines that the first message for master clock device 110 has not been received for N consecutive cycles.

Fig. 4 shows a schematic block diagram of a slave clock device 400 according to an embodiment of the present disclosure.

As shown in fig. 4, the slave clock device 400 includes a synchronization information determining unit 410, a message receiving unit 420, a synchronization device determining unit 430, and a synchronizing unit 440.

Regarding the synchronization information determination unit 410, it is used to determine the synchronization information with the master clock device 110 and the plurality of items of synchronization information with the plurality of master clock devices 120, which are clock synchronized with the master clock device.

Regarding the message receiving unit 420, it is configured to receive a first message periodically transmitted by the master clock device 110 and a plurality of second messages periodically transmitted by the master clock device 120 at a first period, the first message indicating a total master clock status and a message transmission time, each of the plurality of second messages indicating a master clock status and a message transmission time.

Regarding the synchronized device determining unit 430, it is used to determine the first device from the master clock device 110 and the plurality of master clock devices 120.

Regarding the synchronization unit 440, it is configured to perform clock synchronization with the first device at a first period based on synchronization information with the first device and a message transmission time of the first message or the second message received from the first device.

In some embodiments, the message receiving unit 420 is further configured to receive, at the second period, a plurality of third messages periodically transmitted by the plurality of master clock devices 120, each of the plurality of third messages indicating a master clock status and a message transmission time.

The synchronized device determination unit 430 is also used to determine a second device from the plurality of master clock devices.

The synchronization unit 440 is further configured to perform clock synchronization with the second device at the second period based on the synchronization information with the second device and the message transmission time of the third message received from the second device.

In some embodiments, the synchronization device determination unit 430 is further configured to determine a first received or a last received message from the first message and the plurality of second messages; and using the total master clock device or the master clock device from which the determined message came as the first device.

In some embodiments, the message receiving unit 420 is further configured to receive a fourth message periodically sent by the newly-added master clock device, where the fourth message indicates the master clock status. The synchronization information determination unit is further configured to determine synchronization information with the newly added master clock device for clock synchronization with the newly added master clock device.

Fig. 5 shows a schematic block diagram of a master clock device 500 according to an embodiment of the present disclosure.

As shown in fig. 5, the master clock device 500 includes a synchronization information determination unit 510, a message reception unit 520, a synchronization unit 530, and a message transmission unit 540.

Regarding the synchronization information determination unit 510, it is used to determine the synchronization information with the master clock device 110.

Regarding the message receiving unit 520, it is used to receive a first message periodically transmitted by the master clock device 110 at a first period, the first message indicating the master clock status and the message transmission time.

Regarding the synchronization unit 530, it is used to perform clock synchronization with the master clock device 110 at a first cycle based on the synchronization information and the message transmission time.

Regarding the message sending unit 540, it is used to periodically send a second message to the slave clock device 130, the second message indicates the master clock status and the message sending time, so that the slave clock device 130 determines the first device performs clock synchronization from the master clock device 110, the master clock device 500 and the other master clock devices 120.

In some embodiments, master clock device 500 further includes a master clock device determining unit configured to determine whether itself is a new master clock device based on a predetermined rule if it is determined that a third message periodically transmitted by master clock device 110 is not received at the second period, the third message indicating a master clock status and a message transmission time.

The message sending unit 540 is further configured to periodically send a fourth message to the slave clock device 130 and the other master clock devices 120 if determining that the slave clock device is the new master clock master device, where the fourth message indicates the master clock master status and the message sending time, so that the slave clock device 130 determines that the first device performs clock synchronization from the new master clock master device 500 and the other master clock devices 120, and the other master clock devices 120 perform clock synchronization with the new master clock master device 500.

Fig. 6 illustrates a schematic block diagram of an example device 600 that can be used to implement embodiments of the present disclosure. For example, master clock device 110, master clock device 120, and slave clock device 130 as shown in FIG. 1 may be implemented by device 600. As shown, device 600 includes a Central Processing Unit (CPU) 601 that may perform various appropriate actions and processes in accordance with computer program instructions stored in a Read Only Memory (ROM) 602 or loaded from a storage unit 608 into a Random Access Memory (RAM) 603. In the random access memory 603, various programs and data required for the operation of the device 600 can also be stored. The central processing unit 601, the read only memory 602, and the random access memory 603 are connected to each other via a bus 604. An input/output (I/O) interface 605 is also connected to bus 604.

A number of components in the device 600 are connected to the input/output interface 605, including: an input unit 606 such as a keyboard, a mouse, a microphone, and the like; an output unit 607 such as various types of displays, speakers, and the like; a storage unit 608, such as a magnetic disk, optical disk, or the like; and a communication unit 609 such as a network card, modem, wireless communication transceiver, etc. The communication unit 609 allows the device 600 to exchange information/data with other devices via a computer network such as the internet and/or various telecommunication networks.

The various processes and processes described above, such as the

method

200 and 300, may be performed by the central processing unit 601. For example, in some embodiments, the method 200-300 may be implemented as a computer software program tangibly embodied in a machine-readable medium, such as the storage unit 608. In some embodiments, part or all of the computer program may be loaded and/or installed onto the device 600 via the read only memory 602 and/or the communication unit 609. When the computer program is loaded into the random access memory 603 and executed by the central processing unit 601, one or more of the actions of the method 200-300 described above may be performed.

The present disclosure relates to methods, apparatuses, systems, electronic devices, computer-readable storage media and/or computer program products. The computer program product may include computer-readable program instructions for performing various aspects of the present disclosure.

The computer readable storage medium may be a tangible device that can hold and store the instructions for use by the instruction execution device. The computer readable storage medium may be, for example, but not limited to, an electronic memory device, a magnetic memory device, an optical memory device, an electromagnetic memory device, a semiconductor memory device, or any suitable combination of the foregoing. More specific examples (a non-exhaustive list) of the computer readable storage medium would include the following: a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a Static Random Access Memory (SRAM), a portable compact disc read-only memory (CD-ROM), a Digital Versatile Disc (DVD), a memory stick, a floppy disk, a mechanical coding device, such as punch cards or in-groove projection structures having instructions stored thereon, and any suitable combination of the foregoing. Computer-readable storage media as used herein is not to be construed as transitory signals per se, such as radio waves or other freely propagating electromagnetic waves, electromagnetic waves propagating through a waveguide or other transmission medium (e.g., optical pulses through a fiber optic cable), or electrical signals transmitted through electrical wires.

The computer-readable program instructions described herein may be downloaded from a computer-readable storage medium to a respective computing/processing device, or to an external computer or external storage device via a network, such as the internet, a local area network, a wide area network, and/or a wireless network. The network may include copper transmission cables, fiber optic transmission, wireless transmission, routers, firewalls, switches, gateway computers and/or edge servers. The network adapter card or network interface in each computing/processing device receives computer-readable program instructions from the network and forwards the computer-readable program instructions for storage in a computer-readable storage medium in the respective computing/processing device.

The computer program instructions for carrying out operations of the present disclosure may be assembler instructions, Instruction Set Architecture (ISA) instructions, machine-related instructions, microcode, firmware instructions, state setting data, or source or object code written in any combination of one or more programming languages, including an object oriented programming language such as Smalltalk, C + + or the like and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer-readable program instructions may execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the case of a remote computer, the remote computer may be connected to the user's computer through any type of network, including a Local Area Network (LAN) or a Wide Area Network (WAN), or the connection may be made to an external computer (for example, through the Internet using an Internet service provider). In some embodiments, the electronic circuitry that can execute the computer-readable program instructions implements aspects of the present disclosure by utilizing the state information of the computer-readable program instructions to personalize the electronic circuitry, such as a programmable logic circuit, a Field Programmable Gate Array (FPGA), or a Programmable Logic Array (PLA).

Various aspects of the present disclosure are described herein with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the disclosure. It will be understood that each block of the flowchart illustrations and/or block diagrams, and combinations of blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer-readable program instructions.

These computer-readable program instructions may be provided to a processing unit of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processing unit of the computer or other programmable data processing apparatus, create means for implementing the functions/acts specified in the flowchart and/or block diagram block or blocks. These computer-readable program instructions may also be stored in a computer-readable storage medium that can direct a computer, programmable data processing apparatus, and/or other devices to function in a particular manner, such that the computer-readable medium storing the instructions comprises an article of manufacture including instructions which implement the function/act specified in the flowchart and/or block diagram block or blocks.

The computer readable program instructions may also be loaded onto a computer, other programmable data processing apparatus, or other devices to cause a series of operational steps to be performed on the computer, other programmable apparatus or other devices to produce a computer implemented process such that the instructions which execute on the computer, other programmable apparatus or other devices implement the functions/acts specified in the flowchart and/or block diagram block or blocks.

The flowchart and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of instructions, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Having described embodiments of the present disclosure, the foregoing description is intended to be exemplary, not exhaustive, and not limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope and spirit of the described embodiments. The terms used herein were chosen in order to best explain the principles of the embodiments, the practical application, or technical improvements to the techniques in the marketplace, or to enable others of ordinary skill in the art to understand the embodiments disclosed herein.

Claims

1. A method for clock synchronization, comprising:

determining, at a slave clock device, synchronization information with a master clock device and a plurality of items of synchronization information with a plurality of master clock devices, the plurality of master clock devices being clock synchronized with the master clock device;

receiving a first message periodically transmitted by the master clock device and a plurality of second messages periodically transmitted by the plurality of master clock devices at a first period, wherein the first message indicates a master clock state and a message transmission time, and each of the plurality of second messages indicates a master clock state and a message transmission time;

determining a first device from the master clock device and the plurality of master clock devices; and

clock-synchronizing with the first device at the first period based on synchronization information with the first device and a message transmission time of a first message or a second message received from the first device.

2. The method of claim 1, further comprising:

receiving a plurality of third messages periodically transmitted by the plurality of master clock devices at a second period, each of the plurality of third messages indicating a master clock status and a message transmission time;

determining a second device from the plurality of master clock devices; and

performing clock synchronization with the second device at the second period based on synchronization information with the second device and a message transmission time of a third message received from the second device.

3. The method of claim 1, wherein determining the first device comprises:

determining a first received or a last received message from the first message and the plurality of second messages; and

the total master clock device or master clock device from which the determined message originates is taken as the first device.

4. The method of claim 1, further comprising:

receiving a fourth message periodically sent by newly-added master clock equipment, wherein the fourth message indicates the state of the master clock; and

synchronization information with the newly added master clock device is determined for clock synchronization with the newly added master clock device.

5. A method for clock synchronization, comprising:

determining, at a master clock device, synchronization information with a master clock device;

receiving a first message periodically sent by the master clock master device at a first period, wherein the first message indicates master clock status and message sending time;

performing clock synchronization with the master clock device in the first period based on the synchronization information and the message transmission time; and

periodically sending a second message to the slave clock device, the second message indicating a master clock status and a message sending time, so that the slave clock device determines that the first device is clock synchronized from the master clock device, and the other master clock devices.

6. The method of claim 5, further comprising:

if it is determined that a third message periodically sent by the master clock master device is not received in a second period, the third message indicating the master clock state and the message sending time, determining whether the third message is a new master clock master device or not based on a predetermined rule; and

and if the master clock device is determined to be the new master clock device, periodically sending a fourth message to the slave clock device and other master clock devices, wherein the fourth message indicates the state of the master clock device and the message sending time, so that the slave clock device determines that the first device performs clock synchronization from the new master clock device and other master clock devices, and the other master clock devices perform clock synchronization with the new master clock device.

7. A slave clock device, comprising:

at least one processor; and

a memory communicatively coupled to the at least one processor; wherein the content of the first and second substances,

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-4.

8. A master clock device, comprising:

at least one processor; and

the memory stores instructions executable by the at least one processor to enable the at least one processor to perform the method of any one of claims 5-6.

9. A communication system, comprising:

a plurality of slave clock devices according to claim 7;

a plurality of master clock devices according to claim 8; and

an overall master clock device configured to periodically send messages to the plurality of slave clock devices and the plurality of master clock devices, the messages indicating an overall master clock status and a message send time.

10. A non-transitory computer readable storage medium having stored thereon computer instructions for causing the computer to perform the method of any one of claims 1-6.