CN113037074A - Bridgeless voltage reduction power factor correction circuit - Google Patents
Bridgeless voltage reduction power factor correction circuit Download PDFInfo
- Publication number
- CN113037074A CN113037074A CN202110218853.2A CN202110218853A CN113037074A CN 113037074 A CN113037074 A CN 113037074A CN 202110218853 A CN202110218853 A CN 202110218853A CN 113037074 A CN113037074 A CN 113037074A
- Authority
- CN
- China
- Prior art keywords
- power
- unit circuit
- diode
- circuit
- vout
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Images
Classifications
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/42—Circuits or arrangements for compensating for or adjusting power factor in converters or inverters
- H02M1/4208—Arrangements for improving power factor of AC input
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/32—Means for protecting converters other than automatic disconnection
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/02—Conversion of ac power input into dc power output without possibility of reversal
- H02M7/04—Conversion of ac power input into dc power output without possibility of reversal by static converters
- H02M7/12—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/21—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/217—Conversion of ac power input into dc power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P80/00—Climate change mitigation technologies for sector-wide applications
- Y02P80/10—Efficient use of energy, e.g. using compressed air or pressurized fluid as energy carrier
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Rectifiers (AREA)
Abstract
The invention discloses a bridgeless step-down power factor correction circuit, which comprises an MOS tube Q1, an MOS tube Q2, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, an inductor L1, an inductor L2 and a resistor R1.
Description
Technical Field
The invention relates to the technical field of AC-DC switching power supplies, in particular to a bridgeless step-down power factor correction circuit.
Background
In the application of the switching power supply, performance parameters such as efficiency, harmonic current, power-on impact current and the like of the switching power supply are often listed as one of main indexes, so that most of the switching power supplies adopt measures such as active power factor correction, limitation of power-on impact current and the like, and as the output power of the switching power supply increases, particularly at a lower input voltage, the rectification loss of full-bridge rectification cannot be ignored, usually 2% -3.5% of the output power of the switching power supply, and the reduction of the rectification loss of full-bridge rectification is urgent.
Along with the improvement of the performance of the switching power supply, the input voltage range of the power supply is larger and larger, the power supply voltage difference of different areas is as the single highest power supply voltage reaches 300 VAC-420 VAC, the power supply voltage of special occasions such as mines, power plants and the like is higher, the output voltage of a circuit for correcting the traditional power factor is higher, great difficulty is brought to the design of a post converter of the switching power supply, and the correction of the power factor by using the voltage reduction is very important.
Fig. 1 is a schematic block diagram of a conventional power factor correction circuit, which includes, as shown in fig. 1, a resistor R1, a capacitor C1, a capacitor C2, a MOS transistor Q1, an inductor L2, a diode D1, a diode D2, a diode D3, a diode D4, and a diode D5.
Diode D1, diode D3, diode D4 and diode D5 form a full-bridge rectifier circuit, so when MOS transistor Q1 is turned on, the main circuit has two diodes D1 and diode D4 or the series connection of diode D5, diode D3 and MOS transistor Q1, so the rectification loss of the circuit is large.
The related device definition is extended as follows:
MOS transistor Q1, MOS transistor Q2: the switch tube can be understood as a switch tube, and the switch tube comprises an MOS tube, an IGBT and other electronic switch devices.
Diode D1, diode D3, diode D4, and diode D5: it can also be understood as a synchronous rectifier composed of MOS transistors.
Disclosure of Invention
In view of the above, the present invention provides a bridgeless buck power factor correction circuit, which not only can implement buck power factor correction, but also can make the circuit have the characteristics of the bridgeless power factor correction circuit.
The technical scheme provided by the invention is as follows:
a bridgeless buck power factor correction circuit is characterized in that: the circuit comprises a MOS transistor Q1, a MOS transistor Q2, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, an inductor L1, an inductor L2 and a resistor R1, wherein the electrical connection relations are as follows: the alternating current POWER supply input AC POWER L is connected with the drain electrode of a MOS tube Q2 and the cathode of a diode D3, the source electrode of the MOS tube Q2 is connected with the cathode of a diode D4 and the dotted terminal of an inductor L2, the anode of a diode D4 is connected with one end of a capacitor C1, the anode of a diode D1, one end of a resistor R1 and the output end VOUT +, the alternating current POWER supply input AC POWER is connected with the cathode of a diode D2 and the source electrode of a MOS tube Q2, the anode of a diode D2 is connected with the dotted terminal of an inductor L2, the other end of a capacitor C1 and the other end of a resistor R1, the other end of the resistor R1 is connected with the output end VOUT +, the source electrode of the MOS tube Q1 is connected with the cathode of a diode D1 and the dotted terminal of the inductor L1, and the dotted terminal of the.
Preferably, the MOS transistor Q1 and the MOS transistor Q2 work alternately in the positive half cycle and the negative half cycle of the alternating current.
Preferably, the inductor L2 in the bridgeless buck power factor correction circuit is replaced by a transformer TX2, the inductor L1 is replaced by a transformer TX1, and the electrical connection relationship is as follows: the source of the MOS tube Q2 is connected with the homonymous terminal of the primary winding of the transformer TX2, the anode of the diode D2 is connected with the synonym terminal of the primary winding of the transformer TX2, the cathode of the diode D4 is connected with the homonymous terminal of the secondary winding of the transformer TX2, and the other end of the capacitor C1 is connected with the synonym terminal of the secondary winding of the transformer TX 2; the source of the MOS transistor Q1 is connected with the homonymous terminal of the primary winding of the transformer TX1, the anode of the diode D3 is connected with the synonym terminal of the primary winding of the transformer TX1, the cathode of the diode D1 is connected with the homonymous terminal of the secondary winding of the transformer TX1, the output terminal VOUT + is connected with the synonym terminal of the secondary winding of the transformer TX1, and other electrical connection relations are unchanged.
Preferably, the bridgeless buck power factor correction circuit is electrically connected in a delta connection mode as a combination of the unit circuit 1, the unit circuit 2 and the unit circuit 3 to form a three-phase bridgeless buck power factor correction circuit, and the electrical connection relationship is as follows: the AC POWER input AC POWER L in the unit circuit 1 is connected to the AC POWER input AC POWER L in the unit circuit 2 as an AC POWER input AC POWER, the AC POWER input AC POWER L in the unit circuit 2 is connected to the AC POWER input AC POWER L in the unit circuit 3 as an AC POWER input AC POWER B, the AC POWER input AC POWER in the unit circuit 3 is connected to the AC POWER input AC POWER L in the unit circuit 1 as an AC POWER input AC POWER C, the output terminal VOUT + in the unit circuit 1 is electrically connected to the output terminals VOUT + in the unit circuit 2 and the unit circuit 3, respectively, and as the output terminal VOUT +, the output terminal VOUT-in the unit circuit 1 is electrically connected with the output terminals VOUT-in the unit circuit 2 and the unit circuit 3, respectively, and as the output terminal VOUT-, other electrical connection relations are not changed.
Preferably, the bridgeless buck power factor correction circuit is electrically connected in a star connection mode as a combination of the unit circuit 1, the unit circuit 2 and the unit circuit 3 to form a three-phase bridgeless buck power factor correction circuit, and the electrical connection relationship is as follows: the AC POWER input AC POWER N in the unit circuit 1 is electrically connected to the AC POWER input AC POWER N in the unit circuit 2 and the unit circuit 3, respectively, and is an AC POWER input AC POWER N in a three-phase star connection method, the AC POWER input AC POWER L in the unit circuit 1, the unit circuit 2, and the unit circuit 3 are sequentially and respectively used as an AC POWER input AC POWER a, an AC POWER input AC POWER B, and an AC POWER input AC POWER C, the output terminal VOUT + in the unit circuit 1 is electrically connected to the output terminals VOUT + in the unit circuit 2 and the unit circuit 3, respectively, and is used as an output terminal VOUT +, and the output terminal VOUT-in the unit circuit 1 is electrically connected to the output terminals VOUT-in the unit circuit 2 and the unit circuit 3, respectively, and is used as an output terminal VOUT-, and other electrical connection relationships are not changed.
The working principle of the invention will be analyzed in detail by combining with the specific embodiments, which are not described herein, and the beneficial effects are as follows:
1. the full-bridge rectifier circuit is removed, the number of diodes connected in series in the main circuit is reduced during working, the rectification loss of the circuit is reduced, and the conversion efficiency of the circuit is improved;
2. the characteristic of the voltage reduction power factor correction circuit is realized, the output voltage of the power factor correction circuit is reduced, and the design of a switching power supply rear-stage power converter is more convenient;
3. because the loop between the output capacitor C1 and the alternating current input is not conducted when the MOS tube Q1 and the MOS tube Q2 in the circuit are cut off, the power-on impact current of the switching power supply is eliminated.
Drawings
FIG. 1 is a schematic block diagram of a conventional power factor correction circuit;
FIG. 2 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a first embodiment of the present invention;
FIG. 3 is a simulated waveform diagram of a bridgeless buck power factor correction circuit in accordance with a first embodiment of the present invention;
FIG. 4 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a second embodiment of the present invention;
FIG. 5 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a third embodiment of the present invention;
fig. 6 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a fourth embodiment of the present invention.
Detailed Description
In order that those skilled in the art will more readily understand the present invention, reference will now be made to the specific embodiments.
First embodiment
Fig. 2 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a first embodiment of the present invention, where the circuit includes a MOS transistor Q1, a MOS transistor Q2, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, an inductor L1, an inductor L2, and a resistor R1, and the electrical connection relationship is: the alternating current POWER supply input AC POWER L is connected with the drain electrode of a MOS tube Q2 and the cathode of a diode D3, the source electrode of the MOS tube Q2 is connected with the cathode of a diode D4 and the dotted terminal of an inductor L2, the anode of a diode D4 is connected with one end of a capacitor C1, the anode of a diode D1, one end of a resistor R1 and the output end VOUT +, the alternating current POWER supply input AC POWER is connected with the cathode of a diode D2 and the source electrode of a MOS tube Q2, the anode of a diode D2 is connected with the dotted terminal of an inductor L2, the other end of a capacitor C1 and the other end of a resistor R1, the other end of the resistor R1 is connected with the output end VOUT +, the source electrode of the MOS tube Q1 is connected with the cathode of a diode D1 and the dotted terminal of the inductor L1, and the dotted terminal of the.
Compared with the existing power factor correction circuit shown in fig. 1, the full-bridge rectification circuit is omitted, when the MOS transistor Q1 is turned on, the diode D3 in the main circuit is connected in series with the MOS transistor Q1, or when the MOS transistor Q2 is turned on, the diode D2 in the main circuit is connected in series with the MOS transistor Q2, so that the number of diodes connected in series in the main circuit during operation is reduced, the rectification loss of the circuit is reduced, and the bridgeless and reduced power factor correction characteristics are realized.
Description of the working principle:
FIG. 3 is a diagram of simulated waveforms for a first embodiment of the present invention, analyzed as follows:
1. when alternating current is input by an alternating current POWER supply input AC POWER L and an alternating current POWER supply input AC POWER N, the MOS tube Q1 and the MOS tube Q2 work alternately in the positive half period and the negative half period of the alternating current, Q2 GATE and Q2 SOURCE are driving pulse signals of the MOS tube Q2, Q1 GATE and Q1 SOURCE are driving pulse signals of the MOS tube Q1, and the duration of high level is changed according to the sine rule of the positive half period or the negative half period of the alternating current.
2. When the alternating current is a positive half cycle, the phase of the AC1 is synchronized to be a high level, the phase between the Q2 GATE and the Q2 SOURCE is a high level, the MOS transistor Q2 is passively turned on, and the current is input from the alternating current POWER input AC POWER L end, and sequentially flows through the drain of the MOS transistor Q2, the SOURCE of the MOS transistor Q2, the dotted end of the inductor L2, the dotted end of the inductor L2, the anode of the diode D2, and the cathode of the diode D2 to the alternating current POWER input AC POWER N end, at this time, the inductor L2 stores energy, and at the same time, the diode D4, the diode D1, the diode D3, and the MOS transistor Q1 are in a cut-off state.
3. When the phase between the Q2 GATE and the Q2 SOURCE is in a low level, the MOS transistor Q2 is turned off, because the current at the two ends of the inductor L2 can not be suddenly changed, the current continuously flows through the output end VOUT +, the output end VOUT-, the capacitor C1 and the resistor R1 in parallel between the output end VOUT + and the output end VOUT-, the inductor L2 discharges the resistor R1 to charge the capacitor C1, the inductor L2 stores energy, the voltage between the output end VOUT + and the output end VOUT-is controlled by the duration of the high level between the Q2 GATE and the Q2 SOURCE, and the process is repeated until the phase between the AC POWER L and the AC POWER N input AC is in a negative half cycle, and the phase of the AC1 is synchronized to be in a low level.
4. When the alternating current is in a negative half cycle, the phase of the AC2 is synchronous to be high level, the voltage between the Q1 GATE and the Q1 SOURCE is high level, the MOS tube Q1 is passively conducted, current is input from the N end of the alternating current POWER input AC POWER, and sequentially flows through the drain electrode of the MOS tube Q1, the SOURCE electrode of the MOS tube Q1, the dotted end of the inductor L1, the dotted end of the inductor L1, the anode of the diode D3 and the cathode of the diode D3 to the L end of the alternating current POWER input AC POWER, at the moment, the inductor L1 stores energy, and meanwhile, the diode D1, the diode D2, the diode D4 and the MOS tube Q2 are in a cut-off state.
5. When the phase between the Q1 GATE and the Q1 SOURCE is in a low level, the MOS transistor Q1 is turned off, because the current at the two ends of the inductor L1 can not be suddenly changed, the current continuously flows through the output end VOUT +, the output end VOUT-, the capacitor C1 and the resistor R1 in parallel between the output end VOUT + and the output end VOUT-, the inductor L1 discharges the resistor R1 to charge the capacitor C1, the inductor L1 stores energy, the voltage between the output end VOUT + and the output end VOUT-is controlled by the duration of the high level between the Q1 GATE and the Q1 SOURCE, and the process is repeated until the phase between the AC POWER L and the AC POWER N input AC is in a positive half cycle, and the phase of the AC2 is synchronized to be in a low level.
Through the analysis of the working principle of the circuit, the bridgeless step-down power factor correction circuit controls the conduction time of the MOS tube Q2 and the MOS tube Q1 according to the sine rule change of the positive half cycle or the negative half cycle of the alternating current by the driving pulse signal between the Q2 GATE and the Q2 SOURCE or between the Q1 GATE and the Q1 SOURCE, so as to respectively correct the load power factor of the positive half cycle or the negative half cycle of the alternating current, and meanwhile, when the MOS tube Q1 is conducted, the diode D3 and the MOS tube Q1 in the main loop are connected in series, or when the MOS tube Q2 is conducted, the diode D2 and the MOS tube Q2 in the main loop are connected in series, so that the number of the diodes connected in series in the main loop during working is reduced, the rectification loss of the circuit is reduced, and the bridgeless and reduced power factor correction characteristics are realized.
Second embodiment
Fig. 4 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a second embodiment of the present invention, based on the first embodiment: the inductor L2 is replaced by a transformer TX2, the inductor L1 is replaced by a transformer TX1, and the electrical connection relation is as follows: the source of the MOS tube Q2 is connected with the homonymous terminal of the primary winding of the transformer TX2, the anode of the diode D2 is connected with the synonym terminal of the primary winding of the transformer TX2, the cathode of the diode D4 is connected with the homonymous terminal of the secondary winding of the transformer TX2, and the other end of the capacitor C1 is connected with the synonym terminal of the secondary winding of the transformer TX 2; the source of the MOS transistor Q1 is connected with the homonymous terminal of the primary winding of the transformer TX1, the anode of the diode D3 is connected with the synonym terminal of the primary winding of the transformer TX1, the cathode of the diode D1 is connected with the homonymous terminal of the secondary winding of the transformer TX1, the output terminal VOUT + is connected with the synonym terminal of the secondary winding of the transformer TX1, and other electrical connection relations are unchanged.
Description of the working principle: the first embodiment is similar and will not be described herein.
The difference from the first embodiment is that the second embodiment can achieve isolation of the input side and the output side of the bridgeless buck power factor correction circuit.
Third embodiment
Fig. 5 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a third embodiment of the present invention, which is based on the first embodiment, the bridgeless buck power factor correction circuit in the first embodiment is used as a unit circuit 1, a unit circuit 2, and a unit circuit 3, and is electrically connected to form a three-phase bridgeless buck power factor correction circuit by delta connection, where the electrical connection relationship is: the AC POWER input AC POWER N in the unit circuit 1 is connected to the AC POWER input AC POWER L in the unit circuit 2 as AC POWER input AC POWER A, the AC POWER input AC POWER N in the unit circuit 2 is connected to the AC POWER input AC POWER L in the unit circuit 3 as AC POWER input AC POWER B, the AC POWER input AC POWER N in the unit circuit 3 is connected to the AC POWER input AC POWER L in the unit circuit 1 as AC POWER input AC POWER C, the output terminal VOUT + in the unit circuit 1 is electrically connected to the output terminals VOUT + in the unit circuit 2 and the unit circuit 3, respectively, and as the output terminal VOUT +, the output terminal VOUT-in the unit circuit 1 is electrically connected with the output terminals VOUT-in the unit circuit 2 and the unit circuit 3, respectively, and as the output terminal VOUT-, other electrical connection relations are not changed.
Description of the working principle: the operation principle of each of the unit circuits 1, 2, and 3 is the same as that of the first embodiment, and is not described herein again.
The difference from the first embodiment is that the third embodiment can realize the bridgeless buck power factor correction of the three-phase delta connection.
Fourth embodiment
Fig. 6 is a schematic block diagram of a bridgeless buck power factor correction circuit according to a fourth embodiment of the present invention, which is based on the first embodiment, the bridgeless buck power factor correction circuit in the first embodiment is used as a unit circuit 1, a unit circuit 2, and a unit circuit 3, and is electrically connected in a star connection manner to form a three-phase bridgeless buck power factor correction circuit, where the electrical connection relationship is: the AC POWER input AC POWER N in the unit circuit 1 is electrically connected to the AC POWER input AC POWER N in the unit circuit 2 and the unit circuit 3, respectively, and is an AC POWER input AC POWER N in a three-phase star connection method, the AC POWER input AC POWER L in the unit circuit 1, the unit circuit 2, and the unit circuit 3 are sequentially and respectively used as an AC POWER input AC POWER a, an AC POWER input AC POWER B, and an AC POWER input AC POWER C, the output terminal VOUT + in the unit circuit 1 is electrically connected to the output terminals VOUT + in the unit circuit 2 and the unit circuit 3, respectively, and is used as an output terminal VOUT +, and the output terminal VOUT-in the unit circuit 1 is electrically connected to the output terminals VOUT-in the unit circuit 2 and the unit circuit 3, respectively, and is used as an output terminal VOUT-, and other electrical connection relationships are not changed.
Description of the working principle: the operation principle of each of the unit circuits 1, 2, and 3 is the same as that of the first embodiment, and is not described herein again.
The difference from the first embodiment is that the fourth embodiment can realize the bridgeless buck power factor correction of the three-phase star connection.
The above is only a preferred embodiment of the present invention, and it should be noted that the above preferred embodiment should not be considered as limiting the present invention, and as for MOS transistor Q1 and MOS transistor Q2: the switch tube can be understood as a switch tube, and the switch tube comprises an MOS tube, an IGBT and other electronic switch devices. For diodes D1, D2, D3, D4: it can also be understood as a synchronous rectifier composed of MOS transistors. For those skilled in the art, it is obvious that several equivalent changes, modifications and decorations can be made without departing from the spirit and scope of the present invention, and these equivalent changes, modifications and decorations should be regarded as the protection scope of the present invention, which is not described in detail herein without departing from the embodiment, and the protection scope of the present invention should be determined by the scope of the appended claims. All the relationships of "electrical connection", "connection" and "connection" in the patent do not mean that the components are directly connected, but mean that a more preferable connection structure can be formed by adding or reducing connection accessories according to the specific implementation, and the explicit use of "electrical connection" in the present invention is only for the purpose of emphasizing the meaning, but does not exclude the use of "connection" and "connection" as well. All technical characteristics in the invention can be interactively combined on the premise of not conflicting with each other.
Claims (5)
1. A bridgeless buck power factor correction circuit is characterized in that: the circuit comprises a MOS transistor Q1, a MOS transistor Q2, a diode D1, a diode D2, a diode D3, a diode D4, a capacitor C1, an inductor L1, an inductor L2 and a resistor R1, wherein the electrical connection relations are as follows: the alternating current POWER supply input AC POWER L is connected with the drain electrode of a MOS tube Q2 and the cathode of a diode D3, the source electrode of the MOS tube Q2 is connected with the cathode of a diode D4 and the dotted terminal of an inductor L2, the anode of a diode D4 is connected with one end of a capacitor C1, the anode of a diode D1, one end of a resistor R1 and the output end VOUT +, the alternating current POWER supply input AC POWER is connected with the cathode of a diode D2 and the source electrode of a MOS tube Q2, the anode of a diode D2 is connected with the dotted terminal of an inductor L2, the other end of a capacitor C1 and the other end of a resistor R1, the other end of the resistor R1 is connected with the output end VOUT +, the source electrode of the MOS tube Q1 is connected with the cathode of a diode D1 and the dotted terminal of the inductor L1, and the dotted terminal of the.
2. The bridgeless buck power factor correction circuit of claim 1, further characterized by: MOS transistor Q1 and MOS transistor Q2 work alternately in the positive half cycle and the negative half cycle of the alternating current.
3. The bridgeless buck power factor correction circuit of claim 1, wherein: the inductor L2 is replaced by a transformer TX2, the inductor L1 is replaced by a transformer TX1, and the electrical connection relation is as follows: the source of the MOS tube Q2 is connected with the homonymous terminal of the primary winding of the transformer TX2, the anode of the diode D2 is connected with the synonym terminal of the primary winding of the transformer TX2, the cathode of the diode D4 is connected with the homonymous terminal of the secondary winding of the transformer TX2, and the other end of the capacitor C1 is connected with the synonym terminal of the secondary winding of the transformer TX 2; the source of the MOS transistor Q1 is connected with the homonymous terminal of the primary winding of the transformer TX1, the anode of the diode D3 is connected with the synonym terminal of the primary winding of the transformer TX1, the cathode of the diode D1 is connected with the homonymous terminal of the secondary winding of the transformer TX1, the output terminal VOUT + is connected with the synonym terminal of the secondary winding of the transformer TX1, and other electrical connection relations are unchanged.
4. The bridgeless buck power factor correction circuit of claim 1, wherein: the bridgeless step-down power factor correction circuit is electrically connected into a three-phase bridgeless step-down power factor correction circuit by a delta connection method as a combination of a unit circuit 1, a unit circuit 2 and a unit circuit 3, and the electrical connection relationship is as follows: the AC POWER input AC POWER L in the unit circuit 1 is connected to the AC POWER input AC POWER L in the unit circuit 2 as an AC POWER input AC POWER, the AC POWER input AC POWER L in the unit circuit 2 is connected to the AC POWER input AC POWER L in the unit circuit 3 as an AC POWER input AC POWER B, the AC POWER input AC POWER in the unit circuit 3 is connected to the AC POWER input AC POWER L in the unit circuit 1 as an AC POWER input AC POWER C, the output terminal VOUT + in the unit circuit 1 is electrically connected to the output terminals VOUT + in the unit circuit 2 and the unit circuit 3, respectively, and as the output terminal VOUT +, the output terminal VOUT-in the unit circuit 1 is electrically connected with the output terminals VOUT-in the unit circuit 2 and the unit circuit 3, respectively, and as the output terminal VOUT-, other electrical connection relations are not changed.
5. The bridgeless buck power factor correction circuit of claim 1, wherein: the bridgeless step-down power factor correction circuit is combined and electrically connected as a unit circuit 1, a unit circuit 2 and a unit circuit 3 to form a three-phase bridgeless step-down power factor correction circuit by a star connection method, and the electrical connection relationship is as follows: the AC POWER input AC POWER N in the unit circuit 1 is electrically connected to the AC POWER input AC POWER N in the unit circuit 2 and the unit circuit 3, respectively, and is an AC POWER input AC POWER N in a three-phase star connection method, the AC POWER input AC POWER L in the unit circuit 1, the unit circuit 2, and the unit circuit 3 are sequentially and respectively used as an AC POWER input AC POWER, an AC POWER input AC POWER B, and an AC POWER input AC POWER C, the output terminal VOUT + in the unit circuit 1 is electrically connected to the output terminals VOUT + in the unit circuit 2 and the unit circuit 3, respectively, and is used as an output terminal VOUT +, and the output terminal VOUT-in the unit circuit 1 is electrically connected to the output terminals VOUT-in the unit circuit 2 and the unit circuit 3, respectively, and is used as an output terminal VOUT-, and other electrical connection relationships are not changed.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110218853.2A CN113037074A (en) | 2021-02-26 | 2021-02-26 | Bridgeless voltage reduction power factor correction circuit |
| PCT/CN2022/077685 WO2022179564A1 (en) | 2021-02-26 | 2022-02-24 | Bridgeless voltage-drop power factor correction circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202110218853.2A CN113037074A (en) | 2021-02-26 | 2021-02-26 | Bridgeless voltage reduction power factor correction circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN113037074A true CN113037074A (en) | 2021-06-25 |
Family
ID=76461874
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202110218853.2A Withdrawn CN113037074A (en) | 2021-02-26 | 2021-02-26 | Bridgeless voltage reduction power factor correction circuit |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN113037074A (en) |
| WO (1) | WO2022179564A1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179564A1 (en) * | 2021-02-26 | 2022-09-01 | 广州金升阳科技有限公司 | Bridgeless voltage-drop power factor correction circuit |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227564A (en) * | 2013-05-07 | 2013-07-31 | 杭州电子科技大学 | Bridgeless forward power factor correction device |
| WO2015106643A1 (en) * | 2014-01-16 | 2015-07-23 | 深圳市金宏威技术股份有限公司 | Bridgeless buck active power factor correction (apfc) circuit |
| US20180115256A1 (en) * | 2016-10-26 | 2018-04-26 | University Of Manitoba | Bi-Directional Bridgeless Buck-Boost Converter |
| CN108683343A (en) * | 2018-07-03 | 2018-10-19 | 华南理工大学 | Pseudo- continuous conduction mode Buck-Boost non-bridge PFC converters |
| CN111416532A (en) * | 2020-04-27 | 2020-07-14 | 亚瑞源科技（深圳）有限公司 | Bridgeless buck-boost type alternating current-direct current converter |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20160080922A (en) * | 2014-12-30 | 2016-07-08 | 삼성전자주식회사 | Power factor correction circuit, and the electronic product including the same |
| CN211296567U (en) * | 2019-12-31 | 2020-08-18 | 广州金升阳科技有限公司 | Multi-path output circuit |
| CN113037074A (en) * | 2021-02-26 | 2021-06-25 | 广州金升阳科技有限公司 | Bridgeless voltage reduction power factor correction circuit |
-
2021
- 2021-02-26 CN CN202110218853.2A patent/CN113037074A/en not_active Withdrawn
-
2022
- 2022-02-24 WO PCT/CN2022/077685 patent/WO2022179564A1/en active Application Filing
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103227564A (en) * | 2013-05-07 | 2013-07-31 | 杭州电子科技大学 | Bridgeless forward power factor correction device |
| WO2015106643A1 (en) * | 2014-01-16 | 2015-07-23 | 深圳市金宏威技术股份有限公司 | Bridgeless buck active power factor correction (apfc) circuit |
| US20180115256A1 (en) * | 2016-10-26 | 2018-04-26 | University Of Manitoba | Bi-Directional Bridgeless Buck-Boost Converter |
| CN108683343A (en) * | 2018-07-03 | 2018-10-19 | 华南理工大学 | Pseudo- continuous conduction mode Buck-Boost non-bridge PFC converters |
| CN111416532A (en) * | 2020-04-27 | 2020-07-14 | 亚瑞源科技（深圳）有限公司 | Bridgeless buck-boost type alternating current-direct current converter |
Non-Patent Citations (2)
| Title |
|---|
| VINAYAKA K.U.,等: ""Adaptable Speed Control of Bridgeless PFC Buck-Boost Converter VSI Fed BLDC Motor Drive"", 《2016 IEEE 1ST INTERNATIONAL CONFERENCE ON POWER ELECTRONICS,INTELLIGENT CONTROL AND ENERGY SYSTEMS（ICPEICES）》 * |
| 毛行奎: ""基于变压器等效电流模型的隔离型功率变换器教学"", 《电气电子教学学报》 * |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2022179564A1 (en) * | 2021-02-26 | 2022-09-01 | 广州金升阳科技有限公司 | Bridgeless voltage-drop power factor correction circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| WO2022179564A1 (en) | 2022-09-01 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Zhao et al. | A high-efficiency hybrid resonant converter with wide-input regulation for photovoltaic applications | |
| US20220294358A1 (en) | Asymmetrical half-bridge flyback converter and power supply system | |
| CN102263515A (en) | AC-DC (alternating current-direct current) power conversion chip and power conversion circuit | |
| CN103840670A (en) | Energy-saving type high-frequency switching power source | |
| TWI682617B (en) | Interleaved ultra-high boost converter | |
| CN103607108A (en) | Transformer primary side multi-stage passive clamp circuit of full-bridge single-stage power factor corrector | |
| CN105407583A (en) | Single-pole quasi-resonance LED driving device based on Buck-Boost circuit and Flyback circuit | |
| CN103296876A (en) | Control method of buck PFC (power factor correction) | |
| CN108365765A (en) | A kind of multiple-channel output single-end flyback switching power supply | |
| CN101355305B (en) | Multifunctional active clamping structure-changing type double tube positive and negative sharp DC convertor | |
| CN110445387B (en) | Topological structure and control method of formation and grading power supply | |
| CN202178715U (en) | AC-DC power conversion chip and power conversion circuit | |
| CN103762839B (en) | A kind of magnetic coupling type single-phase high-gain Bridgeless power factor circuit correcting circuit | |
| CN113037074A (en) | Bridgeless voltage reduction power factor correction circuit | |
| CN102810986B (en) | A kind of series topology LED switch power circuit | |
| US12119749B2 (en) | Flyback converter, constant-current control method, and lighting system | |
| CN219247707U (en) | Continuous mode control integrated PFC converter device | |
| CN208589926U (en) | A kind of synchronous rectification power supply circuit with absorption function | |
| CN110677063A (en) | Series-parallel DCM Boost PFC converter and working method thereof | |
| CN215344368U (en) | Novel power factor conversion circuit | |
| CN112467989B (en) | Quasi-single-stage high-power-factor alternating current-direct current converter | |
| CN206283411U (en) | A kind of single-stage isolated circuit of power factor correction | |
| EP2680418A2 (en) | A common-core power factor correction resonant converter | |
| CN103546026A (en) | Single-phase high-gain no-bridge power factor correction converter | |
| Wang et al. | A single-stage LED driver based on resonant converter with low-voltage stress |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| WW01 | Invention patent application withdrawn after publication | ||
| WW01 | Invention patent application withdrawn after publication |
Application publication date: 20210625 |