CN113035696B - Preparation method of semiconductor structure and semiconductor structure - Google Patents
Preparation method of semiconductor structure and semiconductor structure Download PDFInfo
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- CN113035696B CN113035696B CN202110213894.2A CN202110213894A CN113035696B CN 113035696 B CN113035696 B CN 113035696B CN 202110213894 A CN202110213894 A CN 202110213894A CN 113035696 B CN113035696 B CN 113035696B
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
- H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
- H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
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Abstract
The present disclosure provides a semiconductor structure and a method for manufacturing the same, the method comprising: forming a first pattern layer on the substrate, wherein the first pattern layer comprises a first pattern on the array region and a second pattern on the peripheral region; forming a mask material layer on the first pattern layer, wherein the mask material layer comprises a first mask material layer positioned on the peripheral region, a second mask material layer positioned on the edge region and a third mask material layer positioned on the central region, and the second mask material layer is larger than the first mask material layer in thickness; determining the position of the edge region and the thickness difference of the second mask material layer and the third mask material layer; correcting the thickness of the second mask material layer according to the position and the thickness difference of the edge area, wherein the corrected thickness difference of the second mask material layer and the third mask material layer is located in the range of the target thickness difference; and patterning the corrected mask material layer to form a mask layer, and patterning the first pattern layer according to the mask layer to form a second pattern layer.
Description
Technical Field
The disclosure relates to the technical field of semiconductors, and in particular relates to a semiconductor structure and a preparation method thereof.
Background
In the modern semiconductor mechanism manufacturing process, a series of relevant process links such as cleaning, film forming, etching, heat treatment and the like need to be carried out, various defects can be introduced into each process, and loss caused by device defects is extremely high.
Meanwhile, under the trend that semiconductor memory chips develop towards high density and large capacity, the memory structure based on planar manufacturing is more delicate in requirement, and the problem of inconsistent sizes of etched memory cells is caused due to the fact that repeated patterns are more and more dense.
It is to be noted that the information disclosed in the above background section is only for enhancement of understanding of the background of the present disclosure, and thus may include information that does not constitute prior art known to those of ordinary skill in the art.
Disclosure of Invention
The present disclosure provides a method for manufacturing a semiconductor structure and a semiconductor structure, which improve etching deviation of a pattern layer in an array region and an edge region, improve product yield, reduce production cost, and improve production efficiency.
According to an aspect of the present disclosure, there is provided a method of fabricating a semiconductor structure, the method comprising:
providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region, the array region comprising a central region and an edge region surrounding the central region;
forming a first pattern layer on the substrate, wherein the first pattern layer comprises a first pattern on the array region and a second pattern on the peripheral region, the first pattern comprises a plurality of first protruding structures distributed at intervals, the second pattern comprises a plurality of second protruding structures distributed at intervals, and the width of each second protruding structure is larger than that of each first protruding structure;
forming a mask material layer on the first pattern layer, wherein the mask material layer comprises a first mask material layer located on the peripheral region, a second mask material layer located on the edge region, and a third mask material layer located on the central region, and the thickness of the second mask material layer is greater than that of the third mask material layer;
determining a location of the edge region and a thickness difference of the second and third masking material layers;
correcting the thickness of the second mask material layer according to the position of the edge region and the thickness difference, so that the corrected thickness difference between the second mask material layer and the third mask material layer is located in the range of target thickness difference;
patterning the corrected mask material layer to form a mask layer, wherein the mask layer is provided with a first groove structure, the first groove structure and the first protrusion structure are arranged correspondingly, and the projection of the first groove structure on the substrate is positioned in the projection of the first protrusion structure on the substrate;
and patterning the first pattern layer according to the mask layer to form a second pattern layer.
In an exemplary embodiment of the present disclosure, the determining the location of the edge region and the difference in thickness of the second and third mask material layers includes:
determining the surface size of the mask material layer through an atomic force microscope;
and determining the position of the edge region and the thickness difference of the second mask material layer and the third mask material layer according to the surface size of the mask material layer.
In an exemplary embodiment of the present disclosure, the correcting the thickness of the second mask material layer according to the position of the edge region and the difference in thickness between the second mask material layer and the third mask material layer includes:
forming a first photoresist material layer on the mask material layer;
patterning the first photoresist material layer according to the determined position of the edge region to form a first photoresist layer, wherein the second mask material layer is exposed by the first photoresist layer;
and adjusting etching parameters of an etching process according to the thickness difference, taking the first photoresist layer as a mask, and etching part of the second mask material layer by using the etching process so as to enable the thickness difference between the etched second mask material layer and the third mask material layer to be within the range of target thickness difference.
In an exemplary embodiment of the present disclosure, the patterning the first photoresist material layer according to the determined position of the edge region, and the forming the first photoresist layer includes:
and designing a photomask exposing the edge area, taking the photomask as a mask, and removing the first photoresist material layer on the edge area by utilizing a photoetching process.
In an exemplary embodiment of the present disclosure, further comprising:
when the target edge region of the substrate deviates from the region exposed by the photomask, the adjustment can be performed by adjusting the illumination energy in the photoetching process.
In an exemplary embodiment of the present disclosure, adjusting an etching parameter of an etching process according to the thickness difference includes:
and comparing the thickness difference with the target thickness difference, and adjusting the etching time of the etching process according to the comparison result.
In an exemplary embodiment of the present disclosure, the patterning the corrected mask material layer to form a mask layer includes:
forming a second photoresist material layer on the corrected mask material layer;
patterning the second photoresist material layer to form a second photoresist layer, wherein the second photoresist layer is provided with a second groove structure; wherein a projection of the second trench structure on the substrate coincides with a projection of the first trench structure on the substrate;
etching the corrected mask material layer by taking the second photoresist layer as a mask;
and removing the second photoresist layer.
In an exemplary embodiment of the present disclosure, the first pattern has a third groove structure, and the third groove structure is located between adjacent first protrusion structures;
the second pattern is provided with fourth groove structures, and the fourth groove structures are positioned between the adjacent second protruding structures;
wherein the trench density of the first pattern is greater than the trench density of the second pattern.
In an exemplary embodiment of the present disclosure, includes:
the thickness of the first masking material layer is greater than the thickness of the second masking material layer.
In an exemplary embodiment of the present disclosure, includes:
the thickness difference between the second mask material layer and the third mask material layer is 10 nm-20 nm.
In an exemplary embodiment of the present disclosure, includes:
the target thickness difference is-5 nm.
In an exemplary embodiment of the present disclosure, includes:
the material forming the first pattern layer includes at least one of silicon oxide, polysilicon, and silicon nitride.
In an exemplary embodiment of the present disclosure, includes:
the material forming the masking material layer includes a carbon material.
In an exemplary embodiment of the present disclosure, the patterning the first pattern layer according to the mask layer, and the forming the second pattern layer further includes:
and removing the mask layer.
According to another exemplary embodiment of the present disclosure, a semiconductor structure is provided, which is formed by the above-mentioned manufacturing method.
In the preparation process of a DRAM product, due to the requirement of product performance, a pattern with high groove density is often formed in an array area, and a pattern with low groove density is formed in a peripheral area, so that when a mask layer is formed subsequently, the thickness of the mask layer above the edge area of the array area is larger than that of the mask layer above the central area of the array area, and the phenomenon of incomplete etching of the mask layer above the edge area is caused during subsequent etching, so that the yield of a semiconductor structure is influenced. In order to solve the above problems, the present disclosure provides a method for manufacturing a semiconductor structure, which corrects the thickness of a mask material layer on an edge region by determining the position of the edge region and the thickness difference between the mask material layer on the edge region and the mask material layer on a center region, so that the thickness difference between the mask material layer on the edge region and the mask material layer on the center region after correction is within a target thickness difference range, thereby avoiding the problem of inconsistent pattern gaps of a formed mask layer due to an excessive thickness difference between the mask material layer on the edge region and the mask material layer on the center region, further avoiding the problem of insufficient etching of the pattern layer on the edge region due to inconsistent pattern gaps of the mask layer, resulting in a narrower line width or even no etching, improving the reliability of the manufacturing method, and improving the yield of products using the manufacturing method, the production cost is reduced, and the production efficiency is improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present disclosure and together with the description, serve to explain the principles of the disclosure. It is to be understood that the drawings in the following description are merely exemplary of the disclosure, and that other drawings may be derived from those drawings by one of ordinary skill in the art without the exercise of inventive faculty.
Fig. 1 is a method for fabricating a semiconductor structure according to an embodiment of the present disclosure;
fig. 2 is a top view of a semiconductor structure provided in an embodiment of the present disclosure;
FIG. 3 is a schematic thickness diagram of a first, second, and third mask material layer measured according to one embodiment of the present disclosure;
fig. 4-13 are process flow diagrams of a method of fabricating a semiconductor structure according to an embodiment of the present disclosure.
Detailed Description
Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and thus their detailed description will be omitted.
Although relative terms, such as "upper" and "lower," may be used in this specification to describe one element of an icon relative to another, these terms are used in this specification for convenience only, e.g., in accordance with the orientation of the examples described in the figures. It will be understood that if the illustrated device is turned upside down, elements described as "upper" will be those that are "lower". When a structure is "on" another structure, it may mean that the structure is integrally formed with the other structure, or that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via another structure.
The terms "a," "an," "the," "said" are used to indicate the presence of one or more elements/components/etc.; the terms "comprising" and "having" are intended to be inclusive and mean that there may be additional elements/components/etc. other than the listed elements/components/etc.; the terms "first" and "second" are used merely as labels, and are not limiting on the number of their objects.
The embodiment of the present disclosure first provides a method for manufacturing a semiconductor structure, as shown in fig. 1, the method includes:
step S100, providing a substrate, wherein the substrate comprises an array area and a peripheral area surrounding the array area, and the array area comprises a central area and an edge area surrounding the central area;
step S200, forming a first pattern layer on the substrate, where the first pattern layer includes a first pattern located on the array region and a second pattern located on the peripheral region, the first pattern includes a plurality of first protruding structures distributed at intervals, the second pattern includes a plurality of second protruding structures distributed at intervals, and a width of each of the second protruding structures is greater than a width of each of the first protruding structures;
step S300 of forming a mask material layer on the first pattern layer, where the mask material layer includes a first mask material layer located on the peripheral region, a second mask material layer located on the edge region, and a third mask material layer located on the central region, and a thickness of the second mask material layer is greater than a thickness of the third mask material layer;
step S400, determining the position of the edge region and the thickness difference of the second mask material layer and the third mask material layer;
step S500, correcting the thickness of the second mask material layer according to the position of the edge area and the thickness difference, so that the corrected thickness difference between the second mask material layer and the third mask material layer is located in the range of target thickness difference;
step S600, patterning the corrected mask material layer to form a mask layer, wherein the mask layer is provided with a first groove structure, the first groove structure and the first protrusion structure are arranged correspondingly, and the projection of the first groove structure on the substrate is positioned in the projection of the first protrusion structure on the substrate;
step S700, patterning the first pattern layer according to the mask layer to form a second pattern layer.
In the preparation process of a DRAM product, due to the requirement of product performance, a pattern with high groove density is often formed in an array area, and a pattern with low groove density is formed in a peripheral area, so that when a mask layer is formed subsequently, the thickness of the mask layer above the edge area of the array area is larger than that of the mask layer above the central area of the array area, and the phenomenon of incomplete etching of the mask layer above the edge area is caused during subsequent etching, so that the yield of a semiconductor structure is influenced. In order to solve the above problems, the present disclosure provides a method for manufacturing a semiconductor structure, which corrects the thickness of a mask material layer on an edge region by determining the position of the edge region and the thickness difference between the mask material layer on the edge region and the mask material layer on a center region, so that the thickness difference between the mask material layer on the edge region and the mask material layer on the center region after correction is within a target thickness difference range, thereby avoiding the problem of inconsistent pattern gaps of a formed mask layer due to an excessive thickness difference between the mask material layer on the edge region and the mask material layer on the center region, further avoiding the problem of insufficient etching of the pattern layer on the edge region due to inconsistent pattern gaps of the mask layer, resulting in a narrower line width or even no etching, improving the reliability of the manufacturing method, and improving the yield of products using the manufacturing method, the production cost is reduced, and the production efficiency is improved.
Hereinafter, each step in the method for manufacturing a semiconductor structure provided by the present disclosure will be described in detail.
In step S100, a substrate is provided, the substrate including an array region and a peripheral region surrounding the array region, the array region including a central region and an edge region surrounding the central region.
Specifically, a substrate 10 is provided, and the substrate 10 may be, for example, a silicon substrate, where the silicon substrate is a substrate having silicon as a main component, such as a monocrystalline silicon substrate, a polycrystalline silicon substrate, and the like, and may be doped with certain ions, such as a p-type silicon substrate, an n-type silicon substrate, and the like.
As shown in fig. 2, the substrate 10 may include an array region including a central region B and an edge region C surrounding the central region B and a peripheral region D surrounding the array region.
In step S200, a first pattern layer is formed on the substrate, where the first pattern layer includes a first pattern on the array region and a second pattern on the peripheral region, the first pattern includes a plurality of first protruding structures distributed at intervals, the second pattern includes a plurality of second protruding structures distributed at intervals, and a width of the second protruding structure is greater than a width of the first protruding structure.
Specifically, the first pattern material layer may be formed on the substrate 10 by a Physical Vapor Deposition (PVD), a Chemical Vapor Deposition (CVD), a spin coating (spin coating), or a combination thereof. The first pattern material layer is patterned, for example, by masking, exposing, developing, and etching, to form a first pattern material layer including a first pattern on the array region and a second pattern on the peripheral region D. As shown in fig. 4, the first pattern includes a plurality of first protruding structures 210 distributed at intervals, and the second pattern includes a plurality of second protruding structures 220 distributed at intervals (only one second protruding structure 220 is shown on each of two sides in fig. 4, and the plurality of second protruding structures 220 may be arranged outside the second protruding structures 220); due to the requirement of DRAM products, the Peripheral pattern is close to the Peripheral circuit (Peripheral/core) or scribe line (scribe line), and the size of the Peripheral circuit and scribe line pattern is generally larger than the size of the array pattern, so the width of the second bump structure 220 is larger than the width of the first bump structure 210.
The material forming the first pattern layer 20 may be a semiconductor material or an insulating material, and the semiconductor material may be, for example, amorphous silicon, polycrystalline silicon, microcrystalline silicon, monocrystalline silicon, an oxide semiconductor material, an organic silicon material, an organic oxide semiconductor material, or a combination thereof; the insulating material may be, for example, silicon oxide, silicon oxynitride, silicon nitride, or other suitable insulating substances (e.g., organic polymers), or a combination thereof.
In step S300, a mask material layer is formed on the first pattern layer, where the mask material layer includes a first mask material layer located on the peripheral region, a second mask material layer located on the edge region, and a third mask material layer located on the central region, and a thickness of the second mask material layer is greater than a thickness of the third mask material layer.
Specifically, as shown in fig. 5, the masking material layer 30 may be formed on the first pattern layer 20 by a physical vapor deposition method, a chemical vapor deposition method, a spin coating method, an atomic layer deposition method, or a combination thereof, where the masking material layer 30 includes a first masking material layer 310 on the peripheral region D, a second masking material layer 320 on the edge region C, and a third masking material layer 330 on the central region B, and since the width of the second protrusion structure 220 is greater than the width of the first protrusion structure 210, when the masking material is deposited, the thickness of the first masking material layer 310 is greater than the thickness of the third masking material layer 330, and the second masking material layer 320 forms an excess layer between the first masking material layer 310 and the third masking material layer 330, so that the thickness of the second masking material layer 320 is also greater than the thickness of the third masking material layer 330.
The material forming the masking material layer 30 includes a carbon material.
In step S400, the position of the edge region and the thickness difference of the second and third mask material layers are determined.
Specifically, the surface size of the masking material layer 30 may be determined by an atomic force microscope, and the position of the edge region C and the thickness difference of the second masking material layer 320 and the third masking material layer 330 may be determined according to the surface size of the masking material layer 30. As shown in fig. 3, after the surface size of the mask material layer 30 is obtained, the position of the edge region C (Define the space CD) and the Thickness difference between the second mask material layer 320 and the third mask material layer 330 (Define the Hard mask Etch Thickness) can be determined.
The Atomic Force Microscope (AFM) mainly comprises a micro-cantilever with a needle point, a micro-cantilever motion detection device, a feedback loop for monitoring the motion of the micro-cantilever, a piezoelectric ceramic scanning device for scanning a sample, and a computer-controlled image acquisition, display and processing system. The movement of the micro cantilever can be detected by an electric method such as tunnel current detection or an optical method such as a beam deflection method and an interference method, when the needle tip and the sample are close enough to each other and a short-distance mutual repulsion force exists, a surface atomic resolution image can be obtained by detecting the repulsion force, and the resolution ratio is also at a nanometer level in general. AFM measurement has no special requirements on samples, and can measure solid surfaces, adsorption systems and the like.
Specifically, a micro-cantilever which is extremely sensitive to weak force is fixed at one end, a micro-needle point is arranged at the other end, the needle point is lightly contacted with the surface of a sample, and because extremely weak repulsive force exists between atoms at the tip end of the needle point and atoms on the surface of the sample, the micro-cantilever with the needle point moves up and down in a direction vertical to the surface of the sample corresponding to an equipotential surface of acting force between the needle point and the atoms on the surface of the sample by controlling the constancy of the force during scanning. The position change of the micro-cantilever corresponding to each scanning point can be measured by an optical detection method or a tunnel current detection method, so that the surface size information of the sample can be obtained.
Illustratively, a Laser-Atomic Force Microscope (Atomic Force Microscope) is used for example, a Laser Diode (Laser Diode) emits a Laser Beam, which is focused on the back surface of the micro-cantilever through an optical system and reflected from the back surface of the micro-cantilever to a spot position detector formed by a photodiode. When a sample is scanned, due to the interaction force between atoms on the surface of the sample and atoms at the probe tip of the micro-cantilever, the micro-cantilever bends and fluctuates along with the surface appearance of the sample, and a reflected light beam is shifted along with the micro-cantilever, so that the surface size information of the measured sample can be obtained by detecting the change of the position of a light spot through the photodiode.
Of course, the position of the edge region C and the thickness difference between the second masking material layer 320 and the third masking material layer 330 can be determined by other methods by those skilled in the art, which is not limited by the present disclosure.
In step S500, the thickness of the second mask material layer is corrected according to the position of the edge region and the thickness difference, so that the corrected thickness difference between the second mask material layer and the third mask material layer is within a target thickness difference range.
Specifically, as shown in fig. 6, a first photoresist material layer 40 is formed on the mask material layer 30. As shown in fig. 7, the first photoresist material layer 40 is patterned according to the determined location of the edge region C to form a first photoresist layer 41, and the first photoresist layer 41 exposes the second mask material layer 320.
As shown in fig. 8, the etching parameters of the etching process are adjusted according to the thickness difference, and the first photoresist layer 41 is used as a mask, and the etching process is used to etch part of the second masking material layer 320, so that the thickness difference between the etched second masking material layer 320 and the third masking material layer 330 is smaller than the target thickness difference. As shown in fig. 7, the surface of the second mask material layer 320 is a non-flat surface, and the average thickness of the second mask material layer 320 can be used as the thickness value.
The thickness difference between the second masking material layer 320 and the third masking material layer 330 before correction is 10nm to 20nm, such as 10nm, 12nm, 15nm, 17nm, 18nm, 20nm, etc., which is not listed herein in this disclosure. Of course, the thickness difference between the second masking material layer 320 and the third masking material layer 330 before correction may also be less than 10nm or greater than 20nm, which is not limited by the present disclosure.
The target thickness difference is in the range of-5 nm to 5nm, i.e., the target thickness difference between the corrected second masking material layer 320 and the third masking material layer 330 is in the range of-5 nm to 5nm, such as-5 nm, -3nm, -1nm, 0nm, 1nm, 3nm, 5nm, etc., which is not listed herein. Of course, the target thickness difference between the second masking material layer 320 and the third masking material layer 330 may also be less than-5 nm or greater than 5nm, which is not limited by the present disclosure.
The thickness of the first mask material layer 310 is greater than the thickness of the second mask material layer 320, that is, the modified second mask material layer 320 is less than or equal to the first mask material layer 310, so as to reduce the negative impact of the loading effect on the manufacturing process.
Wherein, according to the determined position of the edge region C, patterning the first photoresist material layer 40 to form a first photoresist layer 41 includes: and designing a photomask for exposing the edge region C, and removing the first photoresist material layer 40 on the edge region C by using the photomask as a mask by utilizing a photoetching process.
Further, when the target edge region C of the substrate 10 deviates from the reticle-exposed region, it can be adjusted by adjusting the light irradiation energy in the photolithography process. As shown in fig. 7, the mask exposure area can be changed by setting different illumination energies, thereby overcoming the problem of deviation of the target edge region C of the substrate 10 from the mask exposure area.
Wherein, adjusting the etching parameters of the etching process according to the thickness difference comprises: and comparing the thickness difference with the target thickness difference, and adjusting the etching time of the etching process according to the comparison result. Illustratively, the target thickness difference is 0nm, when the thickness difference between the actually measured two mask material layers 30 and the actually measured first mask material layer 310 is 1nm, the target thickness difference can be achieved by increasing the etching time, and when the thickness difference between the actually measured two mask material layers 30 and the actually measured first mask material layer 310 is-1 nm, the target thickness difference can be achieved by decreasing the etching time. For example, if the feedback thickness difference measured by the afm is 20nm, the etching rate is 1nm/s, the first etching time is 20s, and the final thickness difference is measured, and if the thickness difference of the edge region C — the thickness difference of the center region B is X nm, the etching time is optimized to 20+ coefficient X s by the fitting formula, and the coefficient may be, for example, 1.
In addition, due to the difference of each batch of wafers, the position and thickness difference of the edge region C of the semiconductor structure on each batch of wafers can be fed back through the measurement result of the atomic force microscope so as to adjust the illumination energy and the etching parameter, and finally, the CD (critical dimension) condition suitable for each wafer is found, so that the final etched morphology achieves the optimal uniformity.
In step S600, the corrected mask material layer is patterned to form a mask layer, where the mask layer has a first trench structure, the first trench structure is disposed corresponding to the first protrusion structure, and a projection of the first trench structure on the substrate is located in a projection of the first protrusion structure on the substrate.
Specifically, as shown in fig. 9, a second photoresist material layer is formed on the modified mask material layer 30, and the second photoresist material layer is patterned to form a second photoresist layer 50, where the second photoresist layer 50 has a second trench structure 510; as shown in fig. 10, the corrected mask material layer 30 is etched using the second photoresist layer 50 as a mask to form a mask layer 300.
As shown in fig. 10, a projection of the second trench structure 510 on the substrate 10 coincides with a projection of the first trench structure 340 on the substrate 10; the second photoresist layer 50 is then removed, as shown in fig. 11.
In step S700, the first pattern layer is patterned according to the mask layer to form a second pattern layer.
Specifically, as shown in fig. 11, the first pattern has third trench structures 230, the third trench structures 230 being located between adjacent first bump structures 210; the second pattern has fourth trench structures 240, and the fourth trench structures 240 are located between the second bump structures 220 and the first bump structures 210 and between adjacent second bump structures 220. As shown in fig. 12, the first pattern layer 20 is patterned according to the mask layer 300 to form a second pattern layer, the second pattern layer including fifth trench structures 250 formed on the first protrusion structures 210, the fifth trench structures 250 being located between the adjacent third trench structures 230.
The dimensions of the third trench structures 230 and the fifth trench structures 250 may be identical, and the third trench structures 230 and the fourth trench structures 240 may be alternately arranged in an array.
Wherein the trench density of the first pattern is greater than the trench density of the second pattern. As shown in fig. 13, the first pattern includes third trench structures 230 and fifth trench structures 250 arranged in an alternating array, the second pattern includes fourth trench structures 240, and the widths of the fourth trench structures 240 are greater than the widths of the third trench structures 230 and the fifth trench structures 250.
In addition, as shown in fig. 13, the step of forming the second pattern layer further includes removing the mask layer, and the method of removing the mask layer is, for example, dry etching, wet etching or a combination thereof.
It should be noted that although the various steps of the methods of the present disclosure are depicted in the drawings in a particular order, this does not require or imply that these steps must be performed in this particular order, or that all of the depicted steps must be performed, to achieve desirable results. Additionally or alternatively, certain steps may be omitted, multiple steps combined into one step execution, and/or one step broken down into multiple step executions, etc.
Embodiments of the present disclosure also provide a semiconductor structure formed by the above method for manufacturing a semiconductor structure. The semiconductor structure may be applied to a Memory, which may be a Dynamic Random Access Memory (DRAM) or a Read-Only Memory (ROM), and the type of the Memory is not particularly limited. The memory can be used for mobile phones, tablet computers or other terminal devices, and the beneficial effects of the memory can be referred to the beneficial effects of the manufacturing method, which are not described in detail herein.
Other embodiments of the disclosure will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the disclosure following, in general, the principles of the disclosure and including such departures from the present disclosure as come within known or customary practice within the art to which the disclosure pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the disclosure being indicated by the following claims.
It will be understood that the invention is not limited to the precise arrangements described above and shown in the drawings and that various modifications and changes may be made without departing from the scope thereof. The scope of the invention is limited only by the appended claims.
Claims (14)
1. A method for fabricating a semiconductor structure, comprising:
providing a substrate, the substrate comprising an array region and a peripheral region surrounding the array region, the array region comprising a central region and an edge region surrounding the central region;
forming a first pattern layer on the substrate, wherein the first pattern layer comprises a first pattern on the array region and a second pattern on the peripheral region, the first pattern comprises a plurality of first protruding structures distributed at intervals, the second pattern comprises a plurality of second protruding structures distributed at intervals, and the width of each second protruding structure is larger than that of each first protruding structure;
forming a mask material layer on the first pattern layer, wherein the mask material layer comprises a first mask material layer located on the peripheral region, a second mask material layer located on the edge region and a third mask material layer located on the central region, and the thickness of the second mask material layer is greater than that of the third mask material layer;
determining a location of the edge region and a thickness difference of the second and third masking material layers;
correcting the thickness of the second mask material layer according to the position of the edge region and the thickness difference, so that the corrected thickness difference between the second mask material layer and the third mask material layer is located in the range of target thickness difference; wherein the correcting the thickness of the second mask material layer according to the position of the edge region and the thickness difference comprises: forming a first photoresist material layer on the mask material layer; patterning the first photoresist material layer according to the determined position of the edge region to form a first photoresist layer, wherein the second mask material layer is exposed by the first photoresist layer; adjusting etching parameters of an etching process according to the thickness difference, taking the first photoresist layer as a mask, and etching part of the second mask material layer by using the etching process so as to enable the thickness difference between the etched second mask material layer and the third mask material layer to be within the range of target thickness difference;
patterning the corrected mask material layer to form a mask layer, wherein the mask layer is provided with a first groove structure, the first groove structure and the first protrusion structure are arranged correspondingly, and the projection of the first groove structure on the substrate is positioned in the projection of the first protrusion structure on the substrate;
and patterning the first pattern layer according to the mask layer to form a second pattern layer.
2. The method of claim 1, wherein determining the location of the edge region and the difference in thickness of the second and third masking material layers comprises:
determining the surface size of the mask material layer through an atomic force microscope;
and determining the position of the edge region and the thickness difference of the second mask material layer and the third mask material layer according to the surface size of the mask material layer.
3. The method of claim 1, wherein patterning the first photoresist material layer to form a first photoresist layer according to the determined location of the edge region comprises:
and designing a photomask exposing the edge area, taking the photomask as a mask, and removing the first photoresist material layer on the edge area by utilizing a photoetching process.
4. The method of claim 3, further comprising:
when the target edge region of the substrate deviates from the region exposed by the photomask, the adjustment can be performed by adjusting the illumination energy in the photoetching process.
5. The method of claim 3, wherein adjusting the etching parameters of the etching process according to the thickness difference comprises:
and comparing the thickness difference with the target thickness difference, and adjusting the etching time of the etching process according to the comparison result.
6. The method of claim 1, wherein the patterning the modified layer of masking material to form a masking layer comprises:
forming a second photoresist material layer on the corrected mask material layer;
patterning the second photoresist material layer to form a second photoresist layer, wherein the second photoresist layer is provided with a second groove structure; wherein a projection of the second trench structure on the substrate coincides with a projection of the first trench structure on the substrate;
etching the corrected mask material layer by taking the second photoresist layer as a mask;
and removing the second photoresist layer.
7. The method of claim 1, comprising:
the first pattern is provided with third groove structures, and the third groove structures are positioned between the adjacent first protruding structures;
the second pattern is provided with fourth groove structures, and the fourth groove structures are positioned between the adjacent second protruding structures;
wherein the trench density of the first pattern is greater than the trench density of the second pattern.
8. The method of claim 1, comprising:
the thickness of the first masking material layer is greater than the thickness of the second masking material layer.
9. The method of claim 1, comprising:
the thickness difference between the second mask material layer and the third mask material layer is 10 nm-20 nm.
10. The method of claim 1, comprising:
the target thickness difference is-5 nm to 5 nm.
11. The method of claim 1, comprising:
the material forming the first pattern layer includes at least one of silicon oxide, polysilicon, and silicon nitride.
12. The method of claim 1, comprising:
the material forming the masking material layer includes a carbon material.
13. The method of claim 1, wherein the step of patterning the first pattern layer according to the mask layer and forming a second pattern layer further comprises:
and removing the mask layer.
14. A semiconductor structure formed by the method of manufacturing a semiconductor structure of any one of claims 1-13.
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