CN113032722A - Method for reducing matrix decomposition in circuit simulation - Google Patents
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- CN113032722A CN113032722A CN202110334854.3A CN202110334854A CN113032722A CN 113032722 A CN113032722 A CN 113032722A CN 202110334854 A CN202110334854 A CN 202110334854A CN 113032722 A CN113032722 A CN 113032722A
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Abstract
A method for reducing matrix factorization in circuit simulation, comprising the steps of: establishing a Newton-Raphson iterative equation; carrying out Newton-Raphson iteration, and calculating a residual error and a device state corresponding to each iteration; and judging whether matrix decomposition is needed or not according to the residual error or the device state. The method for reducing the matrix decomposition in the circuit simulation can adaptively judge whether the current Newton-Raphson iteration needs to carry out the matrix decomposition in the circuit simulation process, thereby reducing the times of the matrix decomposition in the simulation process and greatly improving the calculation efficiency.
Description
Technical Field
The invention relates to the technical field of EDA circuit simulation, in particular to a method for reducing matrix decomposition in circuit simulation.
Background
The circuit simulation tool spice is a set of simulation tools which establish a set of differential equations based on kirchhoff current law according to the connection relation of electronic elements in the circuit and solve the differential equations. On the time scale, the original differential equation set is dispersed according to a numerical integration method, so that a nonlinear equation set which is satisfied by the circuit at each working point is obtained. And solving the nonlinear equation set through a Newton-Raphson (Newton-Raphson) iterative algorithm to obtain the voltage of each node in the circuit at the working point. The Newton-Raphson iterative algorithm is a very practical and classical iterative solution method. The most important calculation amount of the algorithm is that a large-scale sparse linear equation system is required to be solved in each iteration.
For the simulation of a large-scale circuit, a Newton-Raphson iterative algorithm is adopted to solve a large-scale sparse linear equation set in each iteration, the bottleneck of solving the linear equation set is LU decomposition of a matrix, the proportion exceeds 90%, and the simulation efficiency is greatly reduced.
Disclosure of Invention
In order to solve the defects in the prior art, the invention aims to provide a method for reducing matrix decomposition in circuit simulation, which effectively reduces the matrix decomposition times according to the state and the convergence state of a device in the circuit simulation and improves the simulation efficiency.
In order to achieve the above object, the method for reducing matrix decomposition in circuit simulation provided by the present invention comprises the following steps:
establishing a Newton-Raphson iterative equation;
carrying out Newton-Raphson iteration, and calculating a residual error and a device state corresponding to each iteration;
and judging whether matrix decomposition is needed or not according to the residual error or the device state.
Further, the step of calculating the residual error corresponding to each iteration further includes calculating an weighted infinite norm of the overall residual error according to the reference tolerance of each node to obtain a relatively worst residual error.
Further, the step of calculating the device state corresponding to each iteration further includes marking the operating state of each device according to the voltage change of each node and the operating area of the device.
Further, the step of judging whether matrix decomposition is required according to the residual error further comprises judging whether the residual error drop meets the requirement that the ratio of the current residual error value to the previous residual error value is less than 1e-1, wherein,
if the residual error reduction meets the requirement in the iteration process, the decomposition result of the previous iteration can be multiplexed at the moment, and the matrix decomposition is not carried out in the current iteration; if the residual error drop does not meet the requirement, matrix decomposition is required.
Further, if the matrix decomposition is not carried out in the previous iteration and the residual error reduction of the current iteration does not meet the requirement in the iteration process, carrying out the matrix decomposition on the current iteration; and if the previous iteration is subjected to matrix decomposition and the residual error is not reduced well, determining that the convergence at the current moment is not good, and terminating the iteration in advance.
Further, the step of determining whether matrix decomposition is required according to the device state further includes determining whether a state change of the device satisfies a requirement: the branch voltage in the device varies to satisfy | Δ vp，n|≤relTol*|vp，n|+absTol，
Wherein, Δ vp，nIs the variation of the branch voltage, vp，nThe branch voltage is determined as relTol, the relative error is determined as the default value of 1e-4, absTol is determined as the absolute error, the default value is 1e-5, if the requirement is met, the state change of the device is determined as meeting the requirement, the matrix decomposition result of the previous iteration can be multiplexed, and the matrix decomposition is not performed in the current iteration; otherwise, the state change of the device does not meet the requirement, and matrix decomposition is required.
In order to achieve the above object, the present invention further provides an apparatus for reducing matrix decomposition in circuit simulation, including a memory and a processor, where the memory stores a program running on the processor, and the processor executes the steps of the method for reducing matrix decomposition in circuit simulation.
To achieve the above object, the present invention further provides a computer readable storage medium having stored thereon computer instructions which, when executed, perform the steps of the method for reducing matrix decomposition in circuit simulation described above.
Compared with the prior art, the method for reducing matrix decomposition in circuit simulation has the following beneficial effects: whether matrix decomposition is needed in the current Newton-Raphson iteration can be judged in a self-adaptive mode in the circuit simulation process, so that the matrix decomposition times in the simulation process are reduced, and the calculation efficiency and the simulation efficiency are greatly improved.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.
Drawings
The accompanying drawings are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:
FIG. 1 is a flow chart of a method for reducing matrix decomposition in circuit simulation according to the present invention.
Detailed Description
The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.
Fig. 1 is a flowchart of a method for reducing matrix decomposition in circuit simulation according to the present invention, and the method for reducing matrix decomposition in circuit simulation according to the present invention will be described in detail with reference to fig. 1.
First, in step 11, a Newton-Raphson iterative equation is established.
In the embodiment of the invention, before establishing the Newton-Raphson iterative equation, the simulator needs to be initialized.
In step 12, Newton-Raphson iteration is performed, and the residual error and the device state corresponding to each iteration are calculated.
In the embodiment of the invention, the residual error corresponding to each iteration and the device state corresponding to each iteration are respectively calculated and recorded. In addition, the convergence status at each current time point needs to be recorded.
In the embodiment of the invention, the calculation of the residual error corresponding to each iteration comprises the steps of calculating the weighted infinite norm of the whole residual error according to the reference tolerance of each node to obtain the relative worst residual error.
In the embodiment of the invention, the calculation of the device state corresponding to each iteration comprises marking the working state of each device according to the voltage change of each node and the working area of the device.
In step 13, it is determined whether matrix decomposition is required based on the residual and the device state.
In the embodiment of the invention, whether the residual error reduction meets the requirement is judged firstly: if the residual error is reduced well in the iteration process, the current solution is closer to the true solution, so that the convergence is considered to be better, the decomposition result of the previous iteration can be multiplexed, and the matrix decomposition is not performed in the current iteration. In particular, the previous residual is labeled vi-1Marking the current residual as viIf v isi/vi-1If the value is less than 1e-1, the convergence is considered to meet the requirement; otherwise convergence is not satisfactory.
This criterion is made based on the fact that Newton's iterations have local quadratic convergence properties. If the residual drops by more than an order of magnitude, such as from 1e-5 to less than 1e-6, it is considered a better residual drop. Conversely, if the residual drops by less than an order of magnitude, it is considered a bad iteration, and the current iteration forces matrix decomposition.
In addition, in the iteration process, if the state change of the device is small, the matrix change can be considered to be small, so that the matrix decomposition result of the previous iteration can be multiplexed, and the matrix decomposition is not performed in the current iteration.
A smaller change in state of the device may include a smaller change in the branch voltage at the device port. This is because in the circuit simulation process, if the branch voltage of the device port changes relatively little, the spice simulator will perform linearization processing on the equation of the device at this time, and the element corresponding to the device in the Jacobi matrix at this time is unchanged. It is therefore possible to make a judgment that the device state change is small. In particular, the amount of the solvent to be used,judging whether the state change of the device meets the following requirements: the branch voltage in the device varies to satisfy | Δ vp，n|≤relTol*|vp，n|+absTol，
Wherein, Δ vp，nRefers to the variation of the branch voltage, vp，nThe branch voltage is referred, relTol is referred to as a relative error, the default value is 1e-4, absTol is referred to as an absolute error, the default value is 1e-5, if the requirements are met, the state change of the device is considered to meet the requirements, the matrix decomposition result of the previous iteration can be multiplexed, and the matrix decomposition is not performed in the current iteration; otherwise, the state change of the device does not meet the requirement, and matrix decomposition is required.
In addition, if the previous iteration does not perform matrix decomposition in the iteration process and the residual error of the current iteration is not good to be reduced, the current iteration is forced to perform matrix decomposition; and if the previous iteration is subjected to matrix decomposition and the residual error is not reduced well, determining that the convergence at the current moment is not good, and terminating the iteration in advance. It is determined not to converge.
The invention also provides a device for reducing matrix decomposition in circuit simulation, which comprises a memory and a processor, wherein the memory is stored with a program running on the processor, and the processor executes the steps of the method for reducing matrix decomposition in circuit simulation when running the program.
The present invention further provides a computer-readable storage medium, on which computer instructions are stored, and when the computer instructions are executed, the steps of the method for reducing matrix decomposition in circuit simulation are performed, and the method for reducing matrix decomposition in circuit simulation is described in the foregoing section, and will not be described again.
Those of ordinary skill in the art will understand that: although the present invention has been described in detail with reference to the foregoing embodiments, it will be apparent to those skilled in the art that changes may be made in the embodiments and/or equivalents thereof without departing from the spirit and scope of the invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A method for reducing matrix factorization in circuit simulation, comprising the steps of:
establishing a Newton-Raphson iterative equation;
carrying out Newton-Raphson iteration, and calculating a residual error and a device state corresponding to each iteration;
and judging whether matrix decomposition is needed or not according to the residual error or the device state.
2. The method of claim 1, wherein the step of calculating the residual error for each iteration further comprises calculating an weighted infinite norm of the overall residual error according to a reference tolerance of each node, thereby obtaining a relatively worst residual error.
3. The method of reducing matrix factorization in circuit simulation of claim 1, wherein said step of calculating a corresponding device state for each iteration further comprises marking an operating state of each device based on a voltage change at each node and an operating region of the device.
4. The method of claim 1, wherein the step of determining whether matrix decomposition is required according to the residual further comprises determining whether the residual falls to satisfy a requirement that a ratio of a current residual value to a previous residual value is less than 1e-1, wherein,
if the residual error reduction meets the requirement in the iteration process, the decomposition result of the previous iteration can be multiplexed at the moment, and the matrix decomposition is not carried out in the current iteration; if the residual error drop does not meet the requirement, matrix decomposition is required.
5. The method for reducing matrix decomposition in circuit simulation according to claim 4, further comprising, if in the iteration process, the previous iteration does not perform matrix decomposition and the residual error reduction of the current iteration does not meet the requirement, performing matrix decomposition on the current iteration; and if the previous iteration is subjected to matrix decomposition and the residual error is not reduced well, determining that the convergence at the current moment is not good, and terminating the iteration in advance.
6. The method of claim 1, wherein the step of determining whether matrix decomposition is required based on the device state further comprises determining whether a change in state of the device satisfies a requirement: branch voltage variation in the device, satisfy
，
Wherein the content of the first and second substances,
as the amount of change in the branch voltage,
is the voltage of the branch circuit and is,
for relative error, default values are 1e-4,
the default value is 1e-5 for absolute error, if the requirement is met, the state change of the device is considered to meet the requirement, the matrix decomposition result of the previous iteration can be multiplexed, and the matrix decomposition is not carried out in the current iteration; otherwise, the state change of the device does not meet the requirement, and matrix decomposition is required.
7. An apparatus for reducing matrix factorization in circuit simulation, comprising a memory and a processor, wherein the memory stores a program running on the processor, and the processor executes the program to perform the steps of the method for reducing matrix factorization in circuit simulation as claimed in any one of claims 1-6.
8. A computer readable storage medium having stored thereon computer instructions, wherein said computer instructions when executed perform the steps of the method for reducing matrix factorization in circuit simulation of any of claims 1-6.
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