CN113031486A

CN113031486A - FPGA-based I3C logic controller implementation method, I3C read-write test device and system

Info

Publication number: CN113031486A
Application number: CN202110288739.7A
Authority: CN
Inventors: 聂忠强; 李万泉
Original assignee: Shenzhen Dothinkey Technology Co ltd
Current assignee: Shenzhen Dothinkey Technology Co ltd
Priority date: 2021-03-18
Filing date: 2021-03-18
Publication date: 2021-06-25
Anticipated expiration: 2041-03-18
Also published as: CN113031486B

Abstract

The application discloses an FPGA-based I3C logic controller implementation method, an I3C read-write test device and a system, wherein the method comprises the following steps: receiving a control instruction output by the upper computer based on the packaged I3C protocol; distributing a dynamic address for a slave device with an I3C read/write function according to the control instruction, and setting a maximum length value of once readable/writable data; sending an I3C read/write control command to the slave equipment based on a control instruction of the upper computer to realize I3C read/write operation on the slave equipment; and sending a read slave device data or write operation completion signal to the upper computer to complete the I3C read/write control command. The method is used for solving the problem that the processor does not support the read-write function of I3C in the prior art, and realizing the I3C data read-write and test of the camera module with the I3C bus interface.

Description

FPGA-based I3C logic controller implementation method, I3C read-write test device and system

Technical Field

The invention relates to the technical field of camera module testing, in particular to an FPGA-based I3C logic controller implementation method, an I3C read-write testing device and a system.

Background

Along with the requirement of cell-phone camera module to communication speed is higher and higher, original I2C communication bus speed generally is 100Kbps and 400Kbps, and a small amount of I2C device supports 3.4Mbps, can't satisfy the demand of the high-end camera module of part, and SPI communication bus can satisfy nevertheless bus pin quantity in the speed is many, to cell-phone camera module, undoubtedly can increase the volume. According to the requirements, the MIPI alliance provides an I3C communication bus aiming at the mobile phone camera module, and the MIPI alliance has the advantages that the communication bus is compatible with an I2C device downwards, the communication speed is high, the SDR mode can support 12.5Mbps at most, the number of pins is the same as that of I2C, and a plurality of pins are not needed to be used as the communication bus.

With the fact that the I3C communication bus is more and more widely applied to the mobile phone camera module, new requirements are provided for the camera module test, and the mobile phone camera module test equipment needs to support the controller of the I3C bus to be capable of testing the communication of the mobile phone camera module of the I3C bus. In order to solve the test problem, it is necessary to develop an I3C controller based on an FPGA to implement a cell phone camera module of test I3C.

Disclosure of Invention

The application provides an implementation method of an I3C logic controller based on an FPGA (field programmable gate array), an I3C read-write testing device and an I3C read-write testing system, which are used for overcoming the technical defect that the existing processor cannot test a camera module with an I3C bus interface, and provides an I3C logic controller based on an FPGA and an implementation method thereof, so that the camera module with an I3C bus interface is tested.

In order to achieve the above object, the present application provides an FPGA-based I3C logic controller implementation method, including:

receiving a control instruction output by the upper computer based on the packaged I3C protocol;

distributing a dynamic address for a slave device with an I3C read/write function according to the control instruction, and setting a maximum length value of once readable/writable data;

sending an I3C read/write control command to the slave equipment based on a control instruction of the upper computer to realize I3C read/write operation on the slave equipment; and sending the read data of the slave equipment or a write operation completion signal to the upper computer to complete the I3C read/write control command.

By adopting the technical scheme, the problem that the conventional processor does not support the I3C read-write function, so that the I3C slave device cannot be subjected to read/write communication is solved. Compared with a customized special I3C integrated circuit, the method has the advantages of greatly reducing the research and development cost, shortening the research and development period and improving the design flexibility.

Preferably, the step of allocating a dynamic address to a slave device with an I3C read/write function according to the control instruction and setting a maximum length value of once readable/writable data includes:

distributing dynamic addresses to slave equipment with an I3C read/write function through an I3C bus based on a control instruction of an upper computer; initializing the I3C bus into I3C SDR mode;

and setting a maximum length value of once readable/writable data for the slave equipment based on the control instruction of the upper computer.

By adopting the technical scheme, the communication speed can realize the technical effect of 12.5 Mbps.

Preferably, in the step of receiving a control command output by the upper computer based on the encapsulated I3C protocol:

the control instruction comprises control information and data, wherein the control information comprises a start signal, an end signal, a master device waiting slave device response mark signal, a data writing mark signal, a data reading mark signal and a data reading suspension reading operation mark signal; the data includes slave static address and dynamic address to be allocated, I3C broadcast address, I3C common command code, I3C slave internal register address, write slave valid data.

By adopting the technical scheme, the technical effect of flexible reading and writing operation of I3C data can be realized.

Preferably, the step of allocating a dynamic address to a slave device having an I3C read/write function according to the control instruction includes:

sending a start signal over an I3C bus, sending an I3C dynamic address assignment command to an I3C broadcast address, the assignment command assigning a dynamic address to a slave device using a static address of the slave device;

sending a resume signal over the I3C bus, writing the slave device static address;

writing a dynamic address to be allocated to the slave equipment when receiving a slave equipment response signal ACK;

and sending an end signal to finish dynamic address allocation.

By adopting the technical scheme, the technical effect of distributing the dynamic address to the slave equipment based on the static address can be realized.

Preferably, the control instruction based on the upper computer sends an I3C read/write control command to the slave device to realize I3C read/write operation on the slave device; sending a read slave data or write operation completion signal to an upper computer, wherein the step of completing the I3C read/write control command comprises the following steps:

the control instruction based on the upper computer sends an I3C write control command to the slave equipment to realize I3C write operation on the slave equipment; sending the written data to the slave device; until the I3C write control instruction is completed; sending a write operation completion signal to an upper computer;

the control instruction based on the upper computer sends an I3C read control command to the slave equipment to realize I3C read operation of the slave equipment; until the I3C read control instruction is completed; and sending the read data of the slave equipment to an upper computer.

By adopting the technical scheme, the technical effect of reading/writing I3C from/to the I3C slave by the I3C read control command and the I3C write control command can be realized.

Preferably, the control instruction based on the upper computer sends an I3C write control command to the slave device to realize I3C write operation on the slave device; sending the written data to the slave device; until the I3C write control instruction is completed; the step of sending a write operation completion signal to the upper computer comprises:

transmitting a start signal to the slave device;

writing the distributed dynamic address to the slave equipment, and writing the address of an internal register of the slave equipment and writing valid data after receiving a response signal ACK of the slave equipment;

when the SCL is at high level, the bus I3C jumps from low level to high level based on the ending signal sent by the master device, and ends the current I3C write control command operation;

generating a write operation completion signal and sending the write operation completion signal to an upper computer; completing the current I3C write control command operation;

when the I3C bus is in an idle state, receiving an I3C write control command sent by an upper computer, and performing the next round of I3C write control command operation on the slave equipment until all I3C write control command operations are completed;

the control instruction based on the upper computer sends an I3C read control command to the slave equipment to realize I3C read operation of the slave equipment; until the I3C read control command is completed; the step of sending the read data of the slave device to the upper computer comprises the following steps:

transmitting a start signal to the slave device;

writing the distributed dynamic address to the slave equipment, and writing the address of an internal register of the slave equipment after receiving a response signal ACK of the slave equipment;

sending a restart signal through an I3C bus, writing the allocated dynamic address to the slave device, and starting to read the data of the slave device after receiving a slave device response signal ACK;

when the SCL is at high level, the bus I3C jumps from low level to high level based on the ending signal sent by the master device, and ends the current I3C read control command operation;

sending the read slave device data to an upper computer; completing the current I3C read control command operation;

when the I3C bus is in an idle state, an I3C read control command sent by the upper computer is received, and the next round of I3C read control command operation is carried out on the slave device until all I3C read control command operations are completed.

By adopting the technical scheme, the technical effect of efficiently implementing the I3C read/write control command operation can be realized.

Preferably, when the control instruction based on the upper computer sends an I3C read/write control command to the slave device, the SDA data line switches between the open-drain and push-pull modes, including:

when an address head of an I3C read/write control command is sent to an I3C bus, an SDA data line is set to be in an open-drain mode;

when the I3C read/write control command address head content is sent to the I3C bus, the SDA data line is switched to a push-pull mode, and the data transmission rate is accelerated;

after the current I3C read/write control command is finished, the SDA data lines switch back to the open drain mode, and the I3C bus enters an idle state.

By adopting the technical scheme, a small amount of address head contents are transmitted in an open-drain mode, and non-address head contents are transmitted in a push-pull mode, so that the technical effect of high-efficiency data transmission can be realized.

Preferably, the step of the I3C bus ending the current I3C read control command operation is further followed by the steps of the SDA jumping from low to high when SCL is high based on an end signal issued by the master device:

storing the read slave device data into an output cache;

and the read I3C slave equipment data or I3C write operation completion signals are transmitted to a USB3.0 chip through an SPI controller realized by FPGA internal logic, and are transmitted to an upper computer through a USB bus.

By adopting the technical scheme, the transmission efficiency of the test data is improved.

In order to achieve the purpose, the application also provides an I3C read-write testing device, which comprises a plug-in Flash chip and a logic circuit, wherein the plug-in Flash chip stores a file compiled by computer codes and realized by an I3C logic controller based on FPGA; logic circuits are generated when the files are loaded and the steps of the above method are performed.

By adopting the technical scheme, the method is presented in a computer readable code form and then compiled into a program file for being loaded by the FPGA, the program file is stored in the plug-in Flash chip, after the FPGA loads the program, the internal logic of the FPGA realizes the internal logic circuits of the I3C logic controller, the SPI controller and the like, and the steps of the method are executed to obtain the technical effect.

To achieve the above object, the present application further provides an I3C test system, comprising:

the upper computer issues an I3C read/write control instruction and receives and transmits read/write data based on the operation of a user; has a USB interface;

the USB chip is connected with a USB interface of the upper computer and the I3C read-write testing device;

the I3C read-write testing device is the I3C read-write testing device in the scheme, and comprises an I3C logic controller realized based on FPGA internal logic and an SPI controller realized based on FPGA internal logic, wherein an interface of the SPI controller is physically connected with a USB chip;

and the slave equipment comprises a camera module with an I3C read-write function, and the camera module is connected with the I3C logic controller through an I3C bus.

By adopting the technical scheme, an I3C read/write control command can be issued at the PC software end to control the read/write of the I3C master device FPGA to the I3C slave device, and the read/write result is transmitted to the PC end upper computer control software, so that the complexity of the I3C read/write test is reduced, and a simple and friendly use operation method is provided for users.

Preferably, the I3C logic controller includes an SDA port and an SCL port, the SDA port is connected to the camera module via an SDA data line, and the SCL port is connected to the camera module via an SCL clock line;

and pull-up resistors are connected to the SDA port and the SCL port.

By adopting the technical scheme, the cost can be reduced, and the compatibility can be improved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the structures shown in the drawings without creative efforts.

Fig. 1 is a schematic structural diagram of an I3C read-write test system according to an embodiment of the present application;

fig. 2 is a flowchart of an FPGA implementing an I3C logic controller according to another embodiment of the present application.

The implementation, functional features and advantages of the objects of the present invention will be further explained with reference to the accompanying drawings.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

It should be noted that all the directional indicators (such as up, down, left, right, front, and rear … …) in the embodiment of the present invention are only used to explain the relative position relationship between the components, the movement situation, etc. in a specific posture (as shown in the drawing), and if the specific posture is changed, the directional indicator is changed accordingly.

In addition, the descriptions related to "first", "second", etc. in the present invention are only for descriptive purposes and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one such feature. In the description of the present invention, "a plurality" means at least two, e.g., two, three, etc., unless specifically limited otherwise.

In the present invention, unless otherwise expressly stated or limited, the terms "connected," "secured," and the like are to be construed broadly, and for example, "secured" may be a fixed connection, a removable connection, or an integral part; the connection can be mechanical connection, electrical connection, physical connection or wireless communication connection; they may be directly connected or indirectly connected through intervening media, or they may be connected internally or in any other suitable relationship, unless expressly stated otherwise. The specific meanings of the above terms in the present invention can be understood by those skilled in the art according to specific situations.

In addition, the technical solutions in the embodiments of the present invention may be combined with each other, but it must be based on the realization of those skilled in the art, and when the technical solutions are contradictory or cannot be realized, such a combination of technical solutions should not be considered to exist, and is not within the protection scope of the present invention.

Example one

As shown in fig. 1, the present application provides an I3C read-write test system, which includes a PC upper computer 10, a USB chip 20, an FPGA30, and an I3C slave device (here, a camera module) 40; the USB module 20 is connected with the upper computer 10 through a USB line and is used for the upper computer 10 and the USB chip 20 to transmit data; the USB chip 20 is connected with the FPGA30 through an SPI bus and used for transmitting data between the USB chip 20 (adopting a USB3.0 chip in the scheme) and the FPGA30, and the SPI controller 310 in the FPGA30 is realized by internal logic of the FPGA. The USB chip 20 is connected to the PC upper computer 10 via a USB bus.

The SPI controller 310 receives a control command sent by the PC upper computer 10 and writes the control command into the input cache 320; the control information comprises a start signal, an end signal, a mark signal for the master device to wait for the slave device to respond, a mark signal for writing data, a mark signal for reading data suspension and reading operation, and the like; the data includes static address and dynamic address to be allocated of the slave, I3C broadcast address (7' h 7E), I3C common command code, I3C slave internal register address, write slave data, etc.;

the upper computer 10 encapsulates the I3C read/write control command, encapsulates information related to the I3C control command or data to be written into the I3C slave device into a command packet, and issues the command packet to a buffer of the FPGA (in this scheme, an input buffer), where the FPGA serves as a host of the I3C, takes out the command packet input to the buffer, and determines whether the command is to be operated by the I3C slave device or the I3C slave device by judging whether a write data flag signal or a read data flag signal in the command packet is valid, so as to execute a write I3C slave device function or a read I3C slave device function.

The I3C Common Command Codes (CCC, Common Command Codes) are some I3C Common commands sent by the I3C host to the slave devices, and here refer to commands valid for all I3C slave devices, such as a Command for the I3C master to allocate a Dynamic Address to a slave device using the I3C slave device Static Address (SETDASA, Set Dynamic Address from Static, Command code 0x 87). The public command code is also packaged in a command packet issued by the upper computer and issued to the FPGA input cache. The FPGA executes I3C related commands to the slave device when the cache data is fetched. Also taking the example of allocating dynamic addresses, in the description of allocating dynamic addresses later, refer to the corresponding description details of allocating dynamic address common command codes.

The I3C master controller 340 is implemented by internal logic of the FPGA, takes out control instructions in the input buffer 320, and encapsulates the control instructions into an I3C command frame to implement I3C read-write access to the camera module (I3C slave device) 40; the I3C master device FPGA30 is connected with the I3C slave device 40 through an I3C bus, the I3C bus comprises a data line SDA and a clock line SCL, a pull-up resistor is connected to each of the SDA port and the SCL port, and the I3C bus is compatible with the I2C bus;

the I3C controller 340 writes the completion signal of writing I3C slave device 40 or the data of reading I3C slave device 40 into the output buffer 130, and the SPI controller 310 is controlled by the PC host computer 10 and transmits the data in the output buffer to the PC software side through the USB bus.

Example two

On the basis of the first embodiment, the present embodiment provides an implementation method of an I3C logic controller based on an FPGA, including:

s100, receiving a control instruction output by an upper computer based on a packaged I3C protocol;

the upper computer sends a control command to the FPGA30 of the I3C master device according to a packaged I3C protocol based on an operation command of a user, and writes the I3C read/write control command and data into an internal input buffer of the FPGA through a USB3.0 interface and an SPI interface of a USB chip.

S200, distributing a dynamic address for the slave equipment with the I3C read/write function according to the control instruction, and setting a maximum length value of once readable/writable data;

distributing a Dynamic Address (Dynamic Address) to the slave equipment with the I3C read-write function through an FPGA (field programmable gate array) of the I3C main equipment based on an I3C control instruction of the upper computer; the I3C bus comprises a Data line SDA (serial Data) and a clock line SCL (serial clock), and is compatible with the I2C bus, the FPGA of the master device on the bus allocates dynamic addresses for the I3C slave device, namely, the FPGA of the master device on the bus initializes the I3C bus to enter an I3C SDR (Single Data Rate) mode, and the master device on the bus can perform read/write access of I3C on the slave device;

setting a maximum length value of once readable/writable data for the I3C slave equipment through an I3C master equipment FPGA based on a control instruction of an upper computer; after the operation is completed, the upper computer sends a read/write related control instruction to the slave device through the I3C master device FPGA to send a read/write command to the slave device, so that the I3C read/write operation on the slave device is realized.

S300, sending an I3C read/write control command to the slave equipment based on a control instruction of the upper computer to realize I3C read/write operation on the slave equipment; and sending the read data of the slave equipment or a write operation completion signal to the upper computer to complete the I3C read/write control command.

The I3C host device FPGA transmits the read data to the PC upper computer end through a USB interface;

after the current I3C read/write operation is completed, a read/write command is sent when the bus is idle, the next round of I3C read/write of the slave device is realized until the I3C read/write command is finished, and the read I3C slave device data or the write I3C operation completion signal is transmitted to the upper computer.

The step of sending a write command to the slave device based on the control instruction of the upper computer to realize the I3C write operation to the slave device comprises the following steps:

firstly, the FPGA of the master device sends a starting signal and writes a dynamic address of the slave device; after receiving the slave equipment response signal ACK, the FPGA writes the address of the internal register of the slave equipment and writes the effective data; after the valid data is written, the FPGA sends an end signal to end the current I3C write operation;

the step of sending a read command to the slave device based on the control instruction of the upper computer to realize the I3C read operation of the slave device comprises the following steps:

firstly, the FPGA of the master device sends a starting signal and writes a dynamic address of the slave device; writing the address of the internal register of the slave equipment after the FPGA receives the response signal ACK of the slave equipment; then, the FPGA sends a restart signal, sends a dynamic address to the slave device and carries out reading operation; when the FPGA receives a slave equipment response signal ACK, the effective data of the slave equipment is read; after the effective data is read, the FPGA sends an end signal to end the current I3C reading operation;

after the current I3C read/write operation is completed, a read/write command is sent when the bus is idle, and the steps of realizing the next I3C read/write operation of the slave equipment until the control instruction of the upper computer is completed comprise:

after the current I3C read/write operation is completed, repeating the sending of the read/write command when the bus is idle to realize the next round of I3C read/write of the slave until the I3C slave data read by the lower computer in a feedback way to the upper computer or an I3C write operation completion signal is completed.

The step S100 of receiving the control instruction output by the upper computer based on the packaged I3C protocol includes:

an SPI controller which is realized by FPGA logic receives a control instruction sent by an upper computer, wherein the control instruction comprises control information and data, and the control information and the data are transmitted to an I3C logic controller after being cached in the FPGA; the control information comprises a start signal, an end signal, a mark signal for the master device to wait for the slave device to respond, a mark signal for writing data, a mark signal for reading data suspension and reading operation, and the like; the data includes slave Static Address (Static Address) and dynamic Address to be allocated, I3C Broadcast Address (Broadcast Address, 7' h 7E), I3C Common Command code (CCC, Common Command Codes), I3C slave internal register Address, write slave valid data, etc.

Wherein, the step S200 of allocating a dynamic address to a slave device with I3C read/write function and setting a maximum length value of once readable/writable data according to the control instruction includes:

s201, distributing dynamic addresses to slave equipment with an I3C read/write function through an I3C bus based on a control instruction of an upper computer; initializing the I3C bus into I3C SDR mode;

the step of distributing dynamic addresses to the slave devices based on the I3C control instructions of the upper computer comprises the following steps:

firstly, a master device FPGA on a bus sends a start signal, and sends an I3C Dynamic Address allocation instruction (SETDASA, Set Dynamic Address from Static, command code is 0x 87) to an I3C broadcast Address, wherein the instruction is to allocate a Dynamic Address for a slave device by using a Static Address of the I3C slave device; the FPGA then sends a resume START signal, writing the slave static address; writing a dynamic address to be allocated into the slave equipment after the FPGA receives the response signal ACK of the slave equipment; and finally, the FPGA sends an end signal, and the process of allocating the dynamic address is completed.

The step of initializing the I3C bus to enter I3C mode includes:

the I3C master device FPGA allocates dynamic addresses for the slave devices, an unallocated dynamic address bus is in an I2C mode, and the bus enters an I3C mode after dynamic address allocation is completed.

S202, setting a maximum length value of once readable/writable data for the slave equipment based on a control instruction of the upper computer.

Wherein the step S210 of allocating a dynamic address to a slave device having an I3C read/write function according to the control instruction includes:

s211, sending a start signal through an I3C bus, sending an I3C dynamic address allocation command to an I3C broadcast address, wherein the allocation command allocates a dynamic address for a slave device by using a static address of the slave device;

s212, sending a restarting signal through an I3C bus, and writing a static address of the slave device;

s213, writing the dynamic address to be distributed into the internal register of the slave equipment when receiving the response signal ACK of the slave equipment;

and S214, sending an end signal to complete dynamic address allocation.

Preferably, the control instruction based on the upper computer sends an I3C read/write control command to the slave device to realize I3C read/write operation on the slave device; sending the read data of the slave equipment to an upper computer or sending the written data to the slave equipment; until the I3C read/write control instruction is completed; the step S300 of sending the operation completion signal to the upper computer includes:

s301, sending an I3C write control command to the slave equipment by the control instruction based on the upper computer to realize I3C write operation on the slave equipment; sending the written data to the slave device; until the I3C write control instruction is completed; sending a write operation completion signal to an upper computer;

s302, sending an I3C read control command to the slave equipment by the control instruction based on the upper computer to realize I3C read operation of the slave equipment; until the I3C read control instruction is completed; and sending the read data of the slave equipment to an upper computer. S301 and S302 are two steps arranged in parallel with each other, and the order can be changed.

Step S301 includes:

s311, the FPGA of the master device sends a starting signal to the slave device, namely when the SCL is at a high level, the SDA jumps from the high level to a low level; it may be understood that the current I3C write control command operation is initiated;

s312, writing the distributed dynamic address to the slave equipment, and writing the address of the internal register of the slave equipment and writing effective data after receiving the response signal ACK of the slave equipment;

s313, when the bus of the I3C is at the high level based on the ending signal sent by the master device, the SDA jumps from the low level to the high level, and the current I3C write control command operation is ended;

s314, the master device generates a write operation completion signal and sends the write operation completion signal to the upper computer; completing the current I3C write control command operation;

s315, when the I3C bus is in an idle state, receiving an I3C write control command sent by the upper computer, and performing the next round of I3C write control command operation on the slave equipment until all I3C write control command operations are completed;

step S302 includes:

s321, the master device FPGA sends a start signal to the slave device, namely when SCL is at high level, SDA jumps from high level to low level; may be understood to begin the current I3C read control command operation;

s322, writing the distributed dynamic address to the slave equipment, and writing the address of the internal register of the slave equipment after receiving the response signal ACK of the slave equipment;

s323, sending a restart signal through an I3C bus, writing the allocated dynamic address to the slave device, and starting to read the data of the slave device after receiving a slave device response signal ACK;

s324, when the bus I3C is based on the ending signal sent by the master device, when the SCL is at the high level, the SDA jumps from the low level to the high level, and the current I3C read control command operation is ended;

s325, sending the read slave device data to an upper computer; completing the current I3C read control command operation;

and S326, when the I3C bus is in an idle state, receiving an I3C read control command starting signal sent by the upper computer, and performing the next round of I3C read control command operation on the slave equipment until all I3C read control command operations are completed.

When the control instruction based on the upper computer sends an I3C read/write control command to the slave equipment, the SDA data line is switched between the open-drain mode and the push-pull mode, and the method comprises the following steps:

when an address head of an I3C read/write control command is sent to an I3C bus, an SDA data line is set to be in an open-drain mode; a start signal, a write I3C broadcast address or a slave device dynamic address, and a slave device reply acknowledge signal ACK, which are called address headers of I3C read-write commands;

Wherein, the I3C bus is based on that when SCL is at high level, SDA jumps from low level to high level when the end signal issued by the master device, and after step S314 or S325 of ending the current I3C read control command operation, the method further comprises:

storing the read slave device data into an output cache;

As shown in fig. 2, a specific embodiment of an FPGA-based I3C logic controller implementation method is provided below, including the following steps:

step S3410: the FPGA receives a host computer control command and allocates a dynamic address for the I3C slave equipment, the I3C bus enters an I3C SDR mode, and the FPGA can carry out I3C read/write operation on the slave equipment;

firstly, a main device FPGA on a bus sends a start signal, and sends an I3C dynamic address allocation instruction (SETDASA, command code 0x 87) to an I3C broadcast address (7' h 7E), wherein the instruction allocates a dynamic address for the auxiliary device by using a static address of the I3C auxiliary device; after writing a broadcast address (7 ' h 7E) to the slave equipment, the FPGA needs to wait for an ACK response of the slave equipment, and then sends a 0x87 dynamic address allocation command code, a T code of one bit needs to be written after the command code, and the T code is an exclusive OR value of the first 8bit data and ' 1 ', namely XOR (0 x87, 1);

then the FPGA sends a restart signal to write the static address of the slave device;

writing a dynamic address to be allocated to the slave equipment after the FPGA receives the slave equipment response signal ACK, wherein a one-bit T code needs to be written after the dynamic address, namely an exclusive OR value of the first 8-bit dynamic address and '1';

and finally, the FPGA sends an end signal, and the process of allocating the dynamic address is completed.

Step S3420: the FPGA receives a control instruction of an upper computer, sets a maximum length reading and writing value for the I3C slave equipment, namely the maximum data byte number which can be read or written by an I3C control instruction at one time;

step S3430: the FPGA receives a control instruction of an upper computer, sends a read/write data command to the I3C slave equipment, and carries out read-write operation on the I3C slave equipment;

the step of sending a write command to the slave device based on the control instruction of the upper computer to realize the I3C write operation on the slave device comprises the following steps:

firstly, the FPGA of the master device sends a starting signal and writes a dynamic address of the slave device;

after receiving the slave equipment response signal ACK, the FPGA writes the address of the internal register of the slave equipment and writes the effective data; when the address of the internal register of the slave equipment or the effective data of one byte is written, a bit T code (the exclusive or value of the first 8 bits of data and '1') needs to be written;

after the valid data is written, the FPGA sends an end signal to end the current I3C write operation;

writing an internal register address of the slave equipment after the FPGA receives the response signal ACK of the slave equipment, wherein a one-bit T code needs to be written after the register address;

then, the FPGA sends a restart signal to write a dynamic address to the slave device, and the read operation is carried out;

when the FPGA receives a slave equipment response signal ACK, the effective data of the slave equipment is read;

when receiving one byte of data, the master device FPGA sends a bit signal to determine whether the data read by the current read command reaches the maximum number of read data bytes set in step S3420; the value is '1', which indicates that the number of bytes of read data does not reach the maximum number of bytes of read data, the master device can continue to read the data of the slave device, and can also actively terminate the transmission of the read data, and the current reading operation process is ended. The value is '0', which indicates that the number of read data bytes reaches the maximum number of read data bytes, the main device needs to terminate the read data transmission, and the current read operation is finished; when the I3C master device reads the slave device data, the slave device feeds back a signal every time 8 bits of data are read, so that the master device knows whether the data can be continuously read or not, the flexibility of the I3C read operation is increased, and the write data can be terminated when the maximum number of bytes is not written.

After the effective data is read, the FPGA sends an end signal to end the current I3C reading operation;

step S3440: when the current I3C read/write command is finished, transmitting an I3C write completion signal or read slave equipment data to an upper computer; the next round of I3C read and write commands may be initiated when the bus is idle.

The set read and write maximum length value performing step in step S3420 is similar to the data writing process in step S3430.

It should be noted that, during the above-mentioned sending of I3C read/write command to the slave device based on the control command from the host computer, the SDA data line needs to be switched between the open-drain and push-pull modes, and the switching details are as follows:

the method comprises the following steps that a main device FPGA on a bus sends a start signal, writes an I3C broadcast address or a slave device dynamic address, and replies an acknowledgement signal ACK from the slave device, wherein the part is called an address head of an I3C read-write command, and an SDA data line needs to be set to an open-drain mode; I3C reads and writes the content behind the command address head, the SDA data line is switched to a push-pull mode, and the data transmission rate is accelerated; after the current I3C read-write command is finished, the SDA data line is switched back to the open-drain mode, and the bus enters an idle state.

The above description is only a preferred embodiment of the present invention, and is not intended to limit the scope of the present invention, and all modifications and equivalents of the present invention, which are made by the contents of the present specification and the accompanying drawings, or directly/indirectly applied to other related technical fields, are included in the scope of the present invention.

Claims

1. An FPGA-based I3C logic controller implementation method is characterized by comprising the following steps:

2. The FPGA-based I3C logic controller implementation method of claim 1, wherein the step of assigning a dynamic address to a slave device with I3C read/write function and setting a maximum length value of one-time readable/writable data according to the control instruction comprises:

3. The FPGA-based I3C logic controller implementation method of claim 2, wherein in the step of receiving the control instruction output by the upper computer based on the packaged I3C protocol:

4. The FPGA-based I3C logic controller implementation method of claim 3, wherein the step of assigning a dynamic address to a slave device with I3C read/write capability according to the control instruction comprises:

and sending an end signal to finish dynamic address allocation.

5. The FPGA-based I3C logic controller implementation method of claim 4, wherein the upper computer-based control instruction sends an I3C read/write control command to the slave device to implement I3C read/write operations on the slave device; sending a read slave data or write operation completion signal to an upper computer, wherein the step of completing the I3C read/write control command comprises the following steps:

6. The FPGA-based I3C logic controller implementation method of claim 5, wherein the upper computer-based control instruction sends an I3C write control command to the slave device to implement an I3C write operation to the slave device; sending the written data to the slave device; until the I3C write control instruction is completed; the step of sending a write operation completion signal to the upper computer comprises:

transmitting a start signal to the slave device;

7. The FPGA-based I3C logic controller implementation method of claim 6, wherein when the host-based control instruction is an I3C read/write control command sent by a slave device, the SDA data lines are switched between a drain-open mode and a push-pull mode, and the method comprises:

8. The FPGA-based I3C logic controller implementation method of claim 6, wherein the step of the I3C bus ending the current I3C read control command operation is further followed by the steps of SDA jumping from low to high based on an ending signal issued by a master device when SCL is high:

storing the read slave device data into an output cache;

9. An I3C read-write test device, comprising:

the plug-in Flash chip stores a file compiled by computer codes realized by an I3C logic controller based on the FPGA;

logic circuitry generated when said file is loaded and arranged to perform the steps of the method of any of claims 1 to 8.

10. An I3C read-write test system, comprising:

the I3C read-write test device is the I3C read-write test device of claim 9, and comprises an I3C logic controller realized based on FPGA internal logic and an SPI controller realized based on FPGA internal logic, wherein an interface of the SPI controller is physically connected with a USB chip;