CN113014227A - Terminal resistance calibration method, circuit, chip and high-definition multimedia interface device - Google Patents
Terminal resistance calibration method, circuit, chip and high-definition multimedia interface device Download PDFInfo
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- CN113014227A CN113014227A CN202110226059.2A CN202110226059A CN113014227A CN 113014227 A CN113014227 A CN 113014227A CN 202110226059 A CN202110226059 A CN 202110226059A CN 113014227 A CN113014227 A CN 113014227A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03H—IMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
- H03H11/00—Networks using active elements
- H03H11/02—Multiple-port networks
- H03H11/28—Impedance matching networks
- H03H11/30—Automatic matching of source impedance to load impedance
Abstract
The present disclosure provides a circuit for calibrating a plurality of termination resistances using a single off-chip resistance, comprising: the device comprises a plurality of adjustable terminal resistors, reference resistors and comparators which are arranged corresponding to the terminal resistors, an off-chip reference current generating circuit and an on-chip reference current generating circuit corresponding to the reference resistors; the off-chip reference current generating circuit is provided with a plurality of interfaces, and each interface is connected with each terminal resistor; the off-chip reference current generating circuit comprises an off-chip resistor; the off-chip reference current generating circuit is used for converting reference voltage into off-chip reference current based on off-chip resistance, and the on-chip reference current generating circuit is used for converting the reference voltage into on-chip reference current; the voltage on each terminal resistor and the voltage on each reference resistor are respectively sent to the inverting input end and the non-inverting input end of the corresponding comparator. The disclosure also provides a terminal resistance calibration method, a chip and high-definition multimedia interface equipment.
Description
Technical Field
The disclosure relates to the field of integrated circuits, and in particular, to a circuit for calibrating a plurality of terminal resistors by using a single off-chip resistor, a terminal resistor calibration method, a chip, and high-definition multimedia interface equipment.
Background
At present, aiming at the condition that a plurality of modules are integrated on a single chip, different output signals are obtained by switching and combining input signals of the modules, terminal resistors corresponding to input ports of the modules receive the input signals, and at the moment, the terminal resistors are naturally required to be calibrated. The modules may be distributed at different positions of the chip, the termination resistance of each module needs to be calibrated separately, and separate circuits for providing reference current need to be configured outside the modules.
Disclosure of Invention
The present disclosure is directed to at least solve one of the technical problems in the prior art, and provides a circuit for calibrating a plurality of terminal resistors by using a single off-chip resistor, a terminal resistor calibration method, a chip and a high definition multimedia interface device.
To achieve the above object, in a first aspect, the embodiments of the present disclosure provide a circuit for calibrating a plurality of termination resistances with a single off-chip resistance, the circuit including: the circuit comprises a plurality of adjustable terminal resistors, a reference resistor and a comparator which are arranged corresponding to each terminal resistor, an off-chip reference current generating circuit and an on-chip reference current generating circuit corresponding to each reference resistor;
the off-chip reference current generating circuit is provided with a plurality of interfaces, and each interface is connected with each terminal resistor; the off-chip reference current generating circuit comprises an off-chip resistor;
the off-chip reference current generation circuit is used for converting reference voltage into off-chip reference current based on the off-chip resistor, and the on-chip reference current generation circuit is used for converting the reference voltage into on-chip reference current;
the voltage on each terminal resistor is obtained based on the off-chip reference current, and the voltage on each reference resistor is obtained based on the on-chip reference current generated by the on-chip reference current generating circuit corresponding to the voltage on each reference resistor;
the voltage on each terminal resistor and the voltage on each reference resistor are respectively sent to a positive phase input end and an inverted phase input end of a comparator corresponding to the terminal resistor and the reference resistor;
and the resistance value of each terminal resistor is linearly adjusted, and the corresponding resistance value is the calibrated target value when the output level of the corresponding comparator is inverted.
In some embodiments, each of the on-chip reference current generation circuits includes an on-chip resistor, and a resistance value of each of the reference resistors matches a resistance value of its corresponding on-chip resistor.
In some embodiments, the off-chip reference current generating circuit further comprises a first voltage to current converter; the input end of the first voltage-current converter is connected with the output end of the band-gap reference generating circuit, and the first voltage-current converter is used for converting the reference voltage generated by the band-gap reference generating circuit into a plurality of paths of off-chip reference currents and sending the off-chip reference currents to the terminal resistors;
the first voltage-to-current converter is grounded through the off-chip resistor.
In some embodiments, the on-chip reference current generation circuit comprises: a second voltage to current converter and the on-chip resistor; the input end of the second voltage-current converter is connected with the output end of the band-gap reference generating circuit, and the second voltage-current converter is used for converting the reference voltage generated by the band-gap reference generating circuit into the on-chip reference current and sending the on-chip reference current to the corresponding reference resistor; the second voltage-current converter is grounded through the on-chip resistor.
In some embodiments, the voltage trace corresponding to the reference voltage is provided with a shielding line.
In some embodiments, each of the terminal resistors is connected to its corresponding high definition multimedia interface receiving module, and each of the terminal resistors is configured to receive a signal sent by the corresponding high definition multimedia interface sending module; each on-chip reference current generating circuit is arranged inside each corresponding high-definition multimedia interface receiving module.
In a second aspect, an embodiment of the present disclosure further provides a terminal resistance calibration method, applied to a circuit as described in any of the above embodiments, including:
and linearly adjusting the resistance value of each terminal resistor until the output level of the comparator corresponding to each terminal resistor is inverted.
In some embodiments, each of the termination resistances is adjusted from a reference resistance value, the reference resistance value being 50 Ω.
In a third aspect, an embodiment of the present disclosure further provides a chip, including:
the system comprises a plurality of high-definition multimedia interface receiving modules and a plurality of high-definition multimedia interface sending modules;
a circuit as claimed in any one of the above embodiments.
In a fourth aspect, an embodiment of the present disclosure further provides a high definition multimedia interface device, including:
the system comprises a plurality of high-definition multimedia interface receiving modules and a plurality of high-definition multimedia interface sending modules;
a circuit as claimed in any one of the above embodiments.
The present disclosure has the following beneficial effects:
the embodiment of the disclosure provides a circuit for calibrating a plurality of terminal resistors by adopting a single off-chip resistor, a terminal resistor calibration method, a chip and high-definition multimedia interface equipment, wherein the circuit comprises: the off-chip reference current generating circuit comprises an off-chip reference current generating circuit and an off-chip reference current generating circuit, wherein the off-chip reference current generating circuit is provided with a plurality of interfaces, each interface is connected with each terminal resistor, the off-chip reference current generating circuit comprises an off-chip resistor, and the calibration of the plurality of terminal resistors based on a single off-chip resistor can be realized based on the circuit.
Drawings
Fig. 1 is a schematic structural diagram of a terminal resistance calibration branch according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an off-chip reference current generating circuit according to an embodiment of the disclosure;
fig. 3 is a schematic structural diagram of an on-chip reference current generating circuit according to an embodiment of the disclosure;
fig. 4 is a schematic diagram of a circuit for calibrating a plurality of termination resistors with a single off-chip resistor according to an embodiment of the present disclosure.
Detailed Description
In order to make those skilled in the art better understand the technical solution of the present disclosure, a circuit, a method for calibrating a terminal resistor, a chip and a high definition multimedia interface device provided by the present disclosure, which use a single off-chip resistor to calibrate a plurality of terminal resistors, are described in detail below with reference to the accompanying drawings.
Example embodiments will be described more fully hereinafter with reference to the accompanying drawings, but which may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof.
It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element, component, or module discussed below could be termed a second element, component, or module without departing from the teachings of the present disclosure.
Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure, and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.
The present disclosure provides a circuit for calibrating a plurality of termination resistances using a single off-chip resistance, comprising: the off-chip reference current generating circuit comprises an off-chip reference current generating circuit and an off-chip reference current generating circuit, wherein the off-chip reference current generating circuit is provided with a plurality of interfaces, each interface is connected with each terminal resistor, the off-chip reference current generating circuit comprises an off-chip resistor, and the calibration of the plurality of terminal resistors based on a single off-chip resistor can be realized based on the off-chip resistor
In a first aspect, embodiments of the present disclosure provide a circuit for calibrating a plurality of termination resistances using a single off-chip resistance, including: the circuit comprises a plurality of adjustable terminal resistors (Term), reference resistors and comparators which are arranged corresponding to the terminal resistors, an off-chip reference current generating circuit and an on-chip reference current generating circuit corresponding to the reference resistors.
The off-chip reference current generating circuit is provided with a plurality of interfaces, and each interface is connected with each terminal resistor; the off-chip reference current generating circuit comprises an off-chip resistor; the off-chip reference current generating circuit is used for converting reference voltage into off-chip reference current based on off-chip resistance, and the on-chip reference current generating circuit is used for converting the reference voltage into on-chip reference current; the voltage on each terminal resistor is obtained based on the off-chip reference current, and the voltage on each reference resistor is obtained based on the on-chip reference current generated by the on-chip reference current generating circuit corresponding to the reference resistor; the voltage on each terminal resistor and the voltage on each reference resistor are respectively sent to the inverting input end and the non-inverting input end of the corresponding comparator.
And the resistance value of each terminal resistor is linearly adjusted, and the corresponding resistance value is the calibrated target value when the output level of the corresponding comparator is inverted.
Fig. 1 is a schematic structural diagram of a termination resistance calibration branch according to an embodiment of the present disclosure. As shown in FIG. 1, the termination resistance calibration branch illustrates the calibration of multiple termination resistances with a single off-chip resistance provided by embodiments of the present disclosureIn the circuit of (3) a single terminating resistor RTERMThe circuit connection condition of (1). For the terminal resistance RTERMThe off-chip reference current I1 generated by the off-chip reference current generating circuit is sent to the terminal resistor RTERMThe generated voltage is input to the inverting input end of the corresponding comparator; for the terminal resistance RTERMCorresponding reference resistance RREFThe on-chip reference current I2 generated by the corresponding on-chip reference current generation circuit is sent to the reference resistor RREFThe generated voltage is input to the non-inverting input terminal of the corresponding comparator.
In some embodiments, each on-chip reference current generation circuit comprises an on-chip resistor, and the resistance value of each reference resistor is matched with the resistance value of the corresponding on-chip resistor.
Fig. 2 is a schematic structural diagram of an off-chip reference current generating circuit according to an embodiment of the disclosure. As shown in fig. 2, the off-chip reference current generating circuit has a plurality of interfaces, each interface connecting to a respective terminal resistor (three outputs are schematically shown in the figure); the off-chip reference current generating circuit includes: a first voltage-to-current converter V2I and an off-chip resistor REXT。
The input end of the first voltage-current converter V2I is connected with the output end of the bandgap reference generating circuit BG, and the first voltage-current converter is used for converting a reference voltage V generated by the bandgap reference generating circuit BG into a plurality of off-chip reference currents I1 by V2I and sending the off-chip reference currents I1 to each terminal resistor; the first voltage-to-current converter V2I passes through an off-chip resistor REXTAnd (4) grounding.
Thus, individual calibration of each of the plurality of termination resistors may be achieved based on the single off-chip reference current generating circuit and the off-chip resistor.
Fig. 3 is a schematic structural diagram of an on-chip reference current generating circuit according to an embodiment of the disclosure. As shown in fig. 3, the on-chip reference current generating circuit includes: second voltage-to-current converter V2I' and on-chip resistor RINT(ii) a Wherein, the input end of the second voltage-current converter V2I 'is connected with the output end of the bandgap reference generating circuit, and the second voltage-current converter V2I' is used for generating the bandgap reference generating circuitConverting the reference voltage V into an on-chip reference current I2, and sending the on-chip reference current I2 to a corresponding reference resistor; the second voltage-current converter V2I' passes through the on-chip resistor RINTAnd (4) grounding.
In some embodiments, the voltage trace corresponding to the reference voltage is provided with a shielding line. Therefore, the voltage wiring is prevented from being interfered by other signals.
In some embodiments, each terminal resistor is connected to its corresponding High Definition Multimedia Interface (HDMI) receiving module (RX), and each terminal resistor is configured to receive a signal sent by the corresponding High Definition Multimedia Interface sending module (TX). Each on-chip reference current generating circuit is arranged inside each corresponding high-definition multimedia interface receiving module, wherein the description of 'on-chip' corresponds to the inside of the module; in some embodiments, each termination resistor is disposed inside a corresponding high definition multimedia interface receiving module.
Fig. 4 is a schematic diagram of a circuit for calibrating a plurality of termination resistors with a single off-chip resistor according to an embodiment of the present disclosure. Specifically, taking calibration of three terminal resistors as an example, the off-chip reference current generation circuit comprises a voltage-to-current converter V2I and an off-chip resistor REXTThe input end of the voltage-current converter V2I is connected to the output end of the bandgap reference generating circuit BG to convert the reference voltage V into a plurality of off-chip reference currents having a plurality of outputs, the off-chip reference currents output by the reference current generating circuit BG being supplied to the respective terminal resistors, wherein the off-chip reference currents I _ rext _1 are supplied to the terminal resistor R of the HDMIRX _1TERM1The generated off-chip reference current I _ rext _2 is sent to the terminal resistor R of the HDMIRX _2TERM2The generated off-chip reference current I _ rext _3 is sent to the terminal resistor R of the HDMIRX _1TERM3(ii) a In each high-definition multimedia interface receiving module, an on-chip reference current generating circuit in each high-definition multimedia interface receiving module respectively generates an on-chip reference current which is sent to a reference resistor corresponding to a terminal resistor of each high-definition multimedia interface receiving module, wherein in the high-definition multimedia interface receiving module HDMIRX _1, the on-chip reference current generating circuit is based on an on-chip resistor RINT1The generated off-chip reference current I _ rint _1 is sent to the reference resistor RREF1Correspondingly, in other modules, based on the on-chip resistance RINT2The generated off-chip reference current I _ rint _2 is sent to the reference resistor RREF2Based on the on-chip resistance RINT3The generated off-chip reference current I _ rint _3 is sent to the reference resistor RREF3(ii) a The voltage generated on each terminal resistor based on the corresponding off-chip reference current is respectively input to the inverting input end of the corresponding comparator; the voltages generated on the reference resistors based on the on-chip reference current generated by the corresponding on-chip reference current generating circuit are respectively input to the positive phase input ends of the corresponding comparators.
The embodiment of the disclosure provides a circuit for calibrating a plurality of terminal resistors by using a single off-chip resistor, and particularly, the circuit comprises a plurality of terminal resistors, reference resistors and comparators, the reference resistors are arranged corresponding to the terminal resistors, an off-chip reference current generating circuit and an on-chip reference current generating circuit corresponding to the reference resistors, the off-chip reference current generating circuit comprises an off-chip resistor, and calibration of the terminal resistors based on the single off-chip resistor can be realized based on the circuit.
In a second aspect, embodiments of the present disclosure further provide a termination resistance calibration method, applied to a circuit that calibrates a plurality of termination resistances with a single off-chip resistance according to any one of the first aspect, including:
and linearly adjusting the resistance value of each terminal resistor until the output level of the comparator corresponding to each terminal resistor is inverted.
Wherein, as the resistance value of each terminal resistor gradually increases, when the resistance value reaches the calibration value, the output level of the corresponding comparator is reversed; because the chip manufacturing process can not improve the resistance value accuracy of the on-chip resistor to the condition of no need of reality, the reference current provided based on the off-chip resistor is required to be used as the reference to calibrate the terminal resistor, and when the chip manufacturing process meets the corresponding resistance value accuracy requirement, the terminal resistor can be directly calibrated according to the identification value of the on-chip resistor.
Based on the terminal resistance calibration branch shown in fig. 1, the following formula is adopted:
to perform termination of resistor RTERMCalibration (Calibration). Wherein the reference numerals used for the devices in the formula refer to the resistance values thereof, including the terminating resistor RTERMResistance value of, corresponding off-chip resistance REXTResistance value of (1), on-chip resistance RINTResistance value and reference resistance RREFThe resistance value of (1); m is a fixed value and represents a preset proportional relation; although the absolute value deviation of the on-chip resistance is large, the proportional relation can achieve high precision. Thus, the terminal resistance RTERMIs only equal to the off-chip resistance REXTIs correlated with the resistance value of (a).
In some embodiments, each termination resistance is adjusted starting from a reference resistance value, wherein the reference resistance value is 50 Ω, in particular, the typical resistance value of the termination resistance is 50 Ω in general.
In a third aspect, an embodiment of the present disclosure further provides a chip, including:
the system comprises a plurality of high-definition multimedia interface receiving modules and a plurality of high-definition multimedia interface sending modules; a circuit for calibrating a plurality of termination resistances using a single off-chip resistance as in any of the first aspects.
In a fourth aspect, an embodiment of the present disclosure further provides a high definition multimedia interface device, including:
the system comprises a plurality of high-definition multimedia interface receiving modules and a plurality of high-definition multimedia interface sending modules; a circuit for calibrating a plurality of termination resistances using a single off-chip resistance as in any of the first aspects.
It is to be understood that the above embodiments are merely exemplary embodiments that are employed to illustrate the principles of the present disclosure, and that the present disclosure is not limited thereto. It will be apparent to those skilled in the art that various changes and modifications can be made therein without departing from the spirit and scope of the disclosure, and these are to be considered as the scope of the disclosure.
Claims (10)
1. A circuit for calibrating a plurality of termination resistances with a single off-chip resistance, the circuit comprising: the circuit comprises a plurality of adjustable terminal resistors, a reference resistor and a comparator which are arranged corresponding to each terminal resistor, an off-chip reference current generating circuit and an on-chip reference current generating circuit corresponding to each reference resistor;
the off-chip reference current generating circuit is provided with a plurality of interfaces, and each interface is connected with each terminal resistor; the off-chip reference current generating circuit comprises an off-chip resistor;
the off-chip reference current generation circuit is used for converting reference voltage into off-chip reference current based on the off-chip resistor, and the on-chip reference current generation circuit is used for converting the reference voltage into on-chip reference current;
the voltage on each terminal resistor is obtained based on the off-chip reference current, and the voltage on each reference resistor is obtained based on the on-chip reference current generated by the on-chip reference current generating circuit corresponding to the voltage on each reference resistor;
the voltage on each terminal resistor and the voltage on each reference resistor are respectively sent to the inverting input end and the non-inverting input end of the corresponding comparator;
and the resistance value of each terminal resistor is linearly adjusted, and the corresponding resistance value is the calibrated target value when the output level of the corresponding comparator is inverted.
2. The circuit of claim 1, wherein,
each on-chip reference current generating circuit comprises an on-chip resistor, and the resistance value of each reference resistor is matched with the resistance value of the corresponding on-chip resistor.
3. The circuit of claim 1, wherein the off-chip reference current generating circuit further comprises a first voltage-to-current converter;
the input end of the first voltage-current converter is connected with the output end of the band-gap reference generating circuit, and the first voltage-current converter is used for converting the reference voltage generated by the band-gap reference generating circuit into a plurality of paths of off-chip reference currents and sending the off-chip reference currents to the terminal resistors;
the first voltage-to-current converter is grounded through the off-chip resistor.
4. The circuit of claim 3, wherein the on-chip reference current generation circuit comprises: a second voltage to current converter and the on-chip resistor;
the input end of the second voltage-current converter is connected with the output end of the band-gap reference generating circuit, and the second voltage-current converter is used for converting the reference voltage generated by the band-gap reference generating circuit into the on-chip reference current and sending the on-chip reference current to the corresponding reference resistor; the second voltage-current converter is grounded through the on-chip resistor.
5. The circuit of claim 4, wherein the voltage trace corresponding to the reference voltage is provided with a shielding line.
6. The circuit of claim 1, wherein each terminal resistor is connected to its corresponding high definition multimedia interface receiving module, and each terminal resistor is configured to receive a signal sent by the corresponding high definition multimedia interface sending module; each on-chip reference current generating circuit is arranged inside each corresponding high-definition multimedia interface receiving module.
7. A termination resistance calibration method applied to a circuit as claimed in any one of claims 1 to 6, comprising:
and linearly adjusting the resistance value of each terminal resistor until the output level of the comparator corresponding to each terminal resistor is inverted.
8. The termination resistance calibration method according to claim 1, wherein each of the termination resistances is adjusted from a reference resistance value, the reference resistance value being 50 Ω.
9. A chip, comprising:
the system comprises a plurality of high-definition multimedia interface receiving modules and a plurality of high-definition multimedia interface sending modules;
a circuit as claimed in any one of claims 1 to 6.
10. A high definition multimedia interface device comprising:
the system comprises a plurality of high-definition multimedia interface receiving modules and a plurality of high-definition multimedia interface sending modules;
a circuit as claimed in any one of claims 1 to 6.
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| CN202110226059.2A CN113014227A (en) | 2021-03-01 | 2021-03-01 | Terminal resistance calibration method, circuit, chip and high-definition multimedia interface device |
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