CN113013605A - 基于扇出封装的多馈封装天线 - Google Patents
基于扇出封装的多馈封装天线 Download PDFInfo
- Publication number
- CN113013605A CN113013605A CN202110125247.6A CN202110125247A CN113013605A CN 113013605 A CN113013605 A CN 113013605A CN 202110125247 A CN202110125247 A CN 202110125247A CN 113013605 A CN113013605 A CN 113013605A
- Authority
- CN
- China
- Prior art keywords
- antenna
- layer
- feed
- packaged
- chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/12—Supports; Mounting means
- H01Q1/22—Supports; Mounting means by structural association with other equipment or articles
- H01Q1/2283—Supports; Mounting means by structural association with other equipment or articles mounted in or on the surface of a semiconductor substrate as a chip-type antenna or integrated with other components into an IC package
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/36—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith
- H01Q1/38—Structural form of radiating elements, e.g. cone, spiral, umbrella; Particular materials used therewith formed by a conductive layer on an insulating support
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/64—Impedance arrangements
- H01L23/66—High-frequency adaptations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/20—Structure, shape, material or disposition of high density interconnect preforms
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L24/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/73—Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/40—Radiating elements coated with or embedded in protective material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q1/00—Details of, or arrangements associated with, antennas
- H01Q1/50—Structural association of antennas with earthing switches, lead-in devices or lightning protectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01Q—ANTENNAS, i.e. RADIO AERIALS
- H01Q9/00—Electrically-short antennas having dimensions not more than twice the operating wavelength and consisting of conductive active radiating elements
- H01Q9/04—Resonant antennas
- H01Q9/0407—Substantially flat resonant element parallel to ground plane, e.g. patch antenna
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6605—High-frequency electrical connections
- H01L2223/6627—Waveguides, e.g. microstrip line, strip line, coplanar line
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
- H01L2223/58—Structural electrical arrangements for semiconductor devices not otherwise provided for
- H01L2223/64—Impedance arrangements
- H01L2223/66—High-frequency adaptations
- H01L2223/6661—High-frequency adaptations for passive devices
- H01L2223/6677—High-frequency adaptations for passive devices for antenna, e.g. antenna included within housing of semiconductor device
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/04105—Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/12105—Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24153—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate
- H01L2224/24195—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being arranged next to each other, e.g. on a common substrate the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
- H01L2224/241—Disposition
- H01L2224/24151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/24221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/24265—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
- H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
- H01L2224/25—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of a plurality of high density interconnect connectors
- H01L2224/251—Disposition
- H01L2224/2512—Layout
- H01L2224/25171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73209—Bump and HDI connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Waveguide Aerials (AREA)
Abstract
本发明提供了一种基于扇出封装的多馈封装天线,涉及封装天线技术领域。本发明在所述封装层下方设置第一钝化层,并在第一钝化层设置第一重布线层和第二重布线层来完成多馈封装天线结构。将芯片多个通道的连接端连接到封装天线的天线馈电结构,该天线馈电结构所在的金属层用封装中的第一重布线层来完成,而第二重布线层主要用于实现封装天线。由于采用同轴馈电方式,即用两层重布线层,可在天线上实现多端口功率合成功能,实现宽波束性能,同时可以消除有耗功率合成器所带来的损耗和工作带宽小的特点,其工作带宽和波束带宽将与单个天线几乎一样宽,从而可以有效地减小系统体积和成本,提高了系统的等效全向辐射功率。
Description
技术领域
本发明涉及封装天线技术领域,具体涉及一种基于扇出封装的多馈封装天线。
背景技术
在毫米波甚至太赫兹频段,由于工作波长达到毫米或亚毫米级别,从而为封装天线和毫米波芯片集成提供了可能。封装天线(Antenna-in-Package,AIP)是基于封装工艺和材料,将毫米波芯片和天线集成在封装结构内,其可以较好的兼顾天线体积、性能和成本,从而更好地实现微系统级无线传输的功能。
扇出型晶圆级封装(Fan-Out Wafer Level Packaging,FOWLP),在晶圆的制程中,从半导体裸晶的端点上,拉出所需的电路到重布线层(Redistribution Layer),进而形成封装,成本相对便宜。现有基于扇出型封装实现多端口功率合成功能的多馈天线,主要是在印制板上实现多路功率合成,或是在硅基片上实现天线功率合成。
在传统的扇出型封装实现在天线上进行功率合成时,馈线会对封装天线的辐射性能产生影响,使得辐射方向图偏移,不再指向0度方向,且随着馈线数量的增加,封装天线的辐射性能将持续恶化。
发明内容
(一)解决的技术问题
针对现有技术的不足,本发明提供了一种基于扇出封装的多馈封装天线,解决了如何在封装天线上实现芯片多端口功率合成功能的问题。
(二)技术方案
为实现以上目的,本发明通过以下技术方案予以实现:
一种基于扇出封装的多馈封装天线,包括封装层和芯片,
所述芯片嵌入所述封装层,且在芯片连接端所在的一侧设置有第一钝化层;
所述第一钝化层包括第一重布线层和第二重布线层;
所述第一重布线层中设置有天线馈电结构;
所述第二重布线层中设置有所述封装天线;
所述芯片的多个连接端通过所述第一重布线层内的天线馈电结构与第二重布线层内的封装天线连接。
进一步的,所述天线馈电结构包括对应芯片连接端的多条馈线,所述多条馈线中的各条馈线的第一端通过过孔与所述芯片的连接端连接,且第二端通过过孔与所述封装天线连接。
进一步的,所述封装天线为双馈贴片天线,且连接第二端的两个过孔关于封装天线的中线对称分布。
进一步的,所述封装天线为三馈贴片天线,且连接第二端的三个过孔中的其中一个位于封装天线的中线上,其余两个关于封装天线的中线对称分布。
进一步的,每条馈线的长度相同。
进一步的,所述封装层采用玻璃制成。
进一步的,所述封装层和所述芯片的上端面覆盖有第二钝化层。
进一步的,所述第一钝化层的下端面设置有等间距排布的焊球阵列,所述焊球阵列围绕着芯片和封装天线的四周和非辐射方向排布。
进一步的,所述焊球阵列与外部的印制板上的金属走线连接。
(三)有益效果
本发明提供了一种基于扇出封装的多馈封装天线。与现有技术相比,具备以下有益效果:
本发明在所述封装层下方设置第一钝化层,并在第一钝化层设置第一重布线层和第二重布线层来完成多馈封装天线结构。将芯片多个通道的连接端连接到封装天线的天线馈电结构,该天线馈电结构所在的金属层用封装中的第一重布线层来完成,而第二重布线层主要用于实现封装天线。由于采用同轴馈电方式,即用两层重布线层,一层用于实现天线,一层用于馈线,根据天线电场分布,这样可在天线上实现多端口功率合成功能;且本发明的辐射方向图与单个天线的方向图一样,实现宽波束性能,同时可以消除有耗功率合成器所带来的损耗和工作带宽小的缺点,提高了系统的等效全向辐射功率,同时可以有效地减小系统体积和成本。
附图说明
为了更清楚地说明本发明实施例或现有技术中的技术方案,下面将对实施例或现有技术描述中所需要使用的附图作简单地介绍,显而易见地,下面描述中的附图仅仅是本发明的一些实施例,对于本领域普通技术人员来讲,在不付出创造性劳动的前提下,还可以根据这些附图获得其他的附图。
图1为本发明实施例1的基于扇出封装的双馈封装天线的三维示意图;
图2为本发明实施例1的基于扇出封装的双馈封装天线的仰视图;
图3为本发明实施例2的基于扇出封装的三馈封装天线的三维示意图;
图4为本发明实施例2的基于扇出封装的三馈封装天线的仰视图;
图5为本发明基于扇出封装的多馈封装天线与印制板的连接示意图;
图6为本发明实施例1的基于扇出封装的双馈封装天线的有源发射系数示意图;
图7为本发明实施例1的基于扇出封装的双馈封装天线的辐射方向图;
图8为本发明实施例2的基于扇出封装的三馈封装天线的有源发射系数示意图;
图9为本发明实施例2的基于扇出封装的三馈封装天线的辐射方向图。
具体实施方式
为使本发明实施例的目的、技术方案和优点更加清楚,对本发明实施例中的技术方案进行清楚、完整地描述,显然,所描述的实施例是本发明一部分实施例,而不是全部的实施例。基于本发明中的实施例,本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例,都属于本发明保护的范围。
本申请实施例通过提供一种基于扇出封装的多馈封装天线,解决了如何在封装天线上实现芯片多端口功率合成功能的问题。
本申请实施例中的技术方案为解决上述技术问题,总体思路如下:在所述封装层下方设置第一钝化层,并在第一钝化层设置第一重布线层和第二重布线层来完成多馈封装天线结构。将芯片多个通道的连接端连接到封装天线的天线馈电结构,该天线馈电结构所在的金属层用封装中的第一重布线层来完成,而第二重布线层主要用于实现封装天线。由于采用同轴馈电方式,即用两层重布线层,一层用于实现天线,一层用于馈线,这样根据天线电场分布,可在天线上实现多端口功率合成功能,一方面本发明的辐射方向图与单个天线的方向图一样,实现宽波束性能,同时可以消除有耗功率合成器所带来的损耗和工作带宽小的特点;另一方面,由于芯片连接端直接连接到单个天线上,从而其工作带宽和波束带宽将与单个天线几乎一样宽,从而可以有效地减小系统体积和成本,提高了系统的等效全向辐射功率。
为了更好的理解上述技术方案,下面将结合说明书附图以及具体的实施方式对上述技术方案进行详细的说明。
本发明提供了一种基于扇出封装的多馈封装天线,采用多馈技术在封装天线上实现了多端口功率合成的功能,包括封装层和芯片,
所述芯片嵌入所述封装层,且在芯片连接端所在的一侧设置有第一钝化层;
所述第一钝化层包括第一重布线层和第二重布线层;
所述第一重布线层中设置有天线馈电结构;
所述第二重布线层中设置有所述封装天线;
所述芯片的多个连接端通过所述第一重布线层内的天线馈电结构与第二重布线层内的封装天线连接。
本实施例的有益效果为:
本发明在所述封装层下方设置第一钝化层,并在第一钝化层设置第一重布线层和第二重布线层来完成多馈封装天线结构。将芯片多个通道的连接端连接到封装天线的天线馈电结构,该天线馈电结构所在的金属层用封装中的第一重布线层来完成,而第二重布线层主要用于实现封装天线。由于采用同轴馈电方式,即用两层重布线层,一层用于实现天线,一层用于馈线,这样根据天线电场分布,可在天线上实现多端口功率合成功能,一方面本发明的辐射方向图与单个天线的方向图一样,实现宽波束性能,同时可以消除有耗功率合成器所带来的损耗和工作带宽小的特点;另一方面,由于芯片连接端直接连接到单个天线上,从而其工作带宽和波束带宽将与单个天线几乎一样宽,从而可以有效地减小系统体积和成本,提高了系统的等效全向辐射功率。
实施例1:
如图1所示,以双馈封装天线为例,对本实施例的实现过程进行详细说明:
基于扇出封装的双馈封装天线,包括封装层、芯片以及封装天线;
芯片采用毫米波芯片,所述芯片嵌入封装层,所述芯片嵌入所述封装层,使芯片连接端所在一侧露出即可,例如,使芯片的下端面与封装层的下端面位于同一平面。
考虑到传统扇出封装工艺中,所述封装层采用塑封,通过采用较厚的封装材料加在芯片上方以提高芯片的物理性能。但扇出封装所用的塑封材料加工成本高、损耗较大,并且相比于玻璃具有较高的曲率,且在毫米波频段,塑封材料会对AIP的辐射性能造成一定的影响,由于损耗角正切相比于玻璃的较大,从而将会造成天线增益的减小。因此,封装层采用玻璃制成。由于所用的玻璃材料相比于塑封材料具有较低的损耗、加工成本和曲率,故而可以大大地提高封装天线性能和降低微系统的成本。
且在芯片连接端所在的一侧设置有第一钝化层,使第一钝化层覆盖封装层和芯片的一侧。
具体的,还可使芯片的上端面与封装层的上端面位于同一平面,并设置第二钝化层,使其覆盖所述封装层和芯片的上端面。
所述第一钝化层包括第一重布线层和第二重布线层;
所述第一重布线层中设置天线馈电结构;所述封装天线设置在第二重布线层;所述芯片的多个连接端通过所述第一重布线层内的天线馈电结构与第二重布线层内的封装天线连接。
芯片焊盘通过低高度的过孔直接连接到第一层重布线层上,而若天线放置在顶层,由于芯片高度较大,从芯片焊盘连接到顶层天线需要较高的过孔连接,因而带来较大的过渡损耗,采用扇出封装可以有效规避此过渡损耗。
具体的,如图2所示,所述天线馈电结构包括两条长度相等的馈线,所述馈线的第一端与芯片的两个连接端的第一端通过过孔与所述芯片的连接端连接,且第二端通过过孔与所述封装天线连接。而连接封装天线与馈线的过孔是在第一钝化层实现,且连接第二端的两个过孔关于封装天线的中线对称分布。通过在封装天线上中选择合适的位置,实现将芯片连接端多端口的功率合成在一个天线上,从而代替了无源功率合成器的功能。
如图2所示,所述第一钝化层的下端面设置有等间距排布的焊球阵列,所述焊球阵列围绕着芯片和封装天线的四周和非辐射方向排布。对于封装天线而言,该焊球阵列一方面用于抑制在介质层传播的表面波,另一方面用于将封装天线的共面波导馈电结构的接地端接到印制板上面的地上。对于芯片而言,焊球阵列主要将芯片的数字和模拟管脚连接到印制板上,以保证信号完整性,同时将芯片产生的热量通过焊球快速地散播出去。
具体的,如图5所示,所述焊球阵列与外部的印制板上的金属走线连接。
具体的,为了增加工作带宽,在贴片天线左右两边各加了一个寄生贴片(图中未示出),其对天线辐射性能几乎无影响。
如图6所示的双馈封装天线的有源反射系数响应图,从图中可以发现,此双馈天线阻抗带宽约为6GHz,其中阻抗带宽指天线的S11随着频率变化的曲线,通常定义带宽为|S11|<-10,可以看出此双馈天线有效覆盖了75-81GHz。
如图7所示的双馈封装天线的归一化辐射方向图,此为两个馈电端口同时激励时得到的辐射方向图,从图中可以看出最大辐射方向为接近0度,表明此双馈天线完成了功率合成功能。
实施例2:
如图3所示,以三馈封装天线为例,对本实施例的实现过程进行详细说明:
基于扇出封装的双馈封装天线,包括封装层、芯片以及封装天线;
基于扇出封装的双馈封装天线,包括封装层、芯片以及封装天线;
芯片采用毫米波芯片,所述芯片嵌入封装层,所述芯片嵌入所述封装层,使芯片连接端所在一侧露出即可,例如,使芯片的下端面与封装层的下端面位于同一平面。
考虑到传统扇出封装工艺中,所述封装层采用塑封,通过采用较厚的封装材料加在芯片上方以提高芯片的物理性能。但扇出封装所用的塑封材料加工成本高、损耗较大,并且相比于玻璃具有较高的曲率,且在毫米波频段,塑封材料会对AIP的辐射性能造成一定的影响,由于损耗角正切相比于玻璃的较大,从而将会造成天线增益的减小。因此,封装层采用玻璃制成。由于所用的玻璃材料相比于塑封材料具有较低的损耗、加工成本和曲率,故而可以大大地提高封装天线性能和降低微系统的成本。
且在芯片连接端所在的一侧设置有第一钝化层,使第一钝化层覆盖封装层和芯片的一侧。
具体的,还可使芯片的上端面与封装层的上端面位于同一平面,并设置第二钝化层,使其覆盖所述封装层和芯片的上端面。
所述第一钝化层包括第一重布线层和第二重布线层;
所述第一重布线层中设置天线馈电结构;所述封装天线设置在第二重布线层;所述芯片的多个连接端通过所述第一重布线层内的天线馈电结构与第二重布线层内的封装天线连接。
芯片焊盘通过低高度的过孔直接连接到第一层重布线层上,而若天线放置在顶层,由于芯片高度较大,从芯片焊盘连接到顶层天线需要较高的过孔连接,因而带来较大的过渡损耗,采用扇出封装可以有效规避此过渡损耗。
具体的,如图4所示,所述天线馈电结构包括三条长度相等的馈线,所述馈线的一端与芯片的三个连接端通过过孔连接,且三条所述馈线的另一端通过过孔与同一个三馈封装天线连接。而连接封装天线与馈线的过孔是在第一钝化层实现,且连接封装天线与馈线的所述过孔关于封装天线的中线对称分布。通过在封装天线上中选择合适的位置,实现将芯片连接端多端口的功率合成在一个天线上,从而代替了无源功率合成器的功能。
如图4所示,所述第一钝化层的下端面设置有等间距排布的焊球阵列,所述焊球阵列围绕着芯片和封装天线的四周和非辐射方向排布。对于封装天线而言,该焊球阵列一方面用于抑制在介质层传播的表面波,另一方面用于将封装天线的共面波导馈电结构的接地端接到印制板上面的地上。对于芯片而言,焊球阵列主要将芯片的数字和模拟管脚连接到印制板上,以保证信号完整性,同时将芯片产生的热量通过焊球快速地散播出去。
具体的,如图5所示,所述焊球阵列与外部的印制板上的金属走线连接。
具体的,为了增加工作带宽,在贴片天线左右两边各加了一个寄生贴片(图中未示出),其对天线辐射性能几乎无影响。
如图8所示的三馈封装天线的有源反射系数响应图,从图中可以发现,此三馈天线阻抗带宽约为6GHz,其中阻抗带宽指天线的S11随着频率变化的曲线,通常定义带宽为|S11|<-10,可以看出此三馈天线有效覆盖了75-81GHz。
如图9所示的三馈封装天线的归一化辐射方向图,此为两个馈电端口同时激励时得到的辐射方向图,从图中可以看出最大辐射方向为接近0度,表明此三馈天线完成了功率合成功能。
综上所述,与现有技术相比,本发明具备以下有益效果:
1)本发明在所述封装层下方设置第一钝化层,并在第一钝化层设置第一重布线层和第二重布线层来完成多馈封装天线结构。将芯片多个通道的连接端连接到封装天线的天线馈电结构,该天线馈电结构所在的金属层用封装中的第一重布线层来完成,而第二重布线层主要用于实现封装天线。由于采用同轴馈电方式,即用两层重布线层,一层用于实现天线,一层用于馈线,这样根据天线电场分布,可在天线上实现多端口功率合成功能,一方面本发明的辐射方向图与单个天线的方向图一样,实现宽波束性能,同时可以消除有耗功率合成器所带来的损耗和工作带宽小的特点;另一方面,由于芯片连接端直接连接到单个天线上,从而其工作带宽和波束带宽将与单个天线几乎一样宽,从而可以有效地减小系统体积和成本,提高了系统的等效全向辐射功率。
2)本实施例可将传统扇出封装中的塑封用玻璃材料代替,将芯片嵌入到玻璃材料中,并在玻璃封装层上下设置第一钝化层和第二钝化层,进一步增加芯片的隔离层厚度。由于所用的玻璃材料相比于塑封材料具有较低的损耗、加工成本和曲率,故而可以大大地提高封装天线性能和降低微系统的成本。
3)在芯片和封装天线四周围绕焊球阵列,且沿着天线封装天线非辐射方向等间距排列。对于封装天线而言,该焊球阵列一方面用于抑制在介质层传播的表面波,另一方面用于将封装天线的共面波导馈电结构的接地端接到印制板上面的地上。对于芯片而言,焊球阵列主要将芯片的数字和模拟管脚连接到印制板上,以保证信号完整性,同时将芯片产生的热量通过焊球快速地散播出去。
需要说明的是,通过以上的实施方式的描述,本领域的技术人员可以清楚地了解到各实施方式可借助软件加必需的通用硬件平台的方式来实现。基于这样的理解,上述技术方案本质上或者说对现有技术做出贡献的部分可以以软件产品的形式体现出来,该计算机软件产品可以存储在计算机可读存储介质中,如ROM/RAM、磁碟、光盘等,包括若干指令用以使得一台计算机设备(可以是个人计算机,服务器,或者网络设备等)执行各个实施例或者实施例的某些部分所述的方法。在本文中,诸如第一和第二等之类的关系术语仅仅用来将一个实体或者操作与另一个实体或操作区分开来,而不一定要求或者暗示这些实体或操作之间存在任何这种实际的关系或者顺序。而且,术语“包括”、“包含”或者其任何其他变体意在涵盖非排他性的包含,从而使得包括一系列要素的过程、方法、物品或者设备不仅包括那些要素,而且还包括没有明确列出的其他要素,或者是还包括为这种过程、方法、物品或者设备所固有的要素。在没有更多限制的情况下,由语句“包括一个……”限定的要素,并不排除在包括所述要素的过程、方法、物品或者设备中还存在另外的相同要素。
以上实施例仅用以说明本发明的技术方案,而非对其限制;尽管参照前述实施例对本发明进行了详细的说明,本领域的普通技术人员应当理解:其依然可以对前述各实施例所记载的技术方案进行修改,或者对其中部分技术特征进行等同替换;而这些修改或者替换,并不使相应技术方案的本质脱离本发明各实施例技术方案的精神和范围。
Claims (9)
1.一种基于扇出封装的多馈封装天线,其特征在于,包括封装层和芯片,
所述芯片嵌入所述封装层,且在芯片连接端所在的一侧设置有第一钝化层;
所述第一钝化层包括第一重布线层和第二重布线层;
所述第一重布线层中设置有天线馈电结构;
所述第二重布线层中设置有所述封装天线;
所述芯片的多个连接端通过所述第一重布线层内的天线馈电结构与第二重布线层内的封装天线连接。
2.如权利要求1所述的多馈封装天线,其特征在于,所述天线馈电结构包括对应芯片连接端的多条馈线,所述多条馈线中的各条馈线的第一端通过过孔与所述芯片的连接端连接,且第二端通过过孔与所述封装天线连接。
3.如权利要求2所述的多馈封装天线,其特征在于,所述封装天线为双馈贴片天线,且连接第二端的两个过孔关于封装天线的中线对称分布。
4.如权利要求2所述的多馈封装天线,其特征在于,所述封装天线为三馈贴片天线,且连接第二端的三个过孔中的其中一个位于封装天线的中线上,其余两个关于封装天线的中线对称分布。
5.如权利要求2-4任一所述的多馈封装天线,其特征在于,每条馈线的长度相同。
6.如权利要求1所述的多馈封装天线,其特征在于,所述封装层采用玻璃制成。
7.如权利要求1所述的多馈封装天线,其特征在于,所述封装层和所述芯片的上端面覆盖有第二钝化层。
8.如权利要求1所述的多馈封装天线,其特征在于,所述第一钝化层的下端面设置有等间距排布的焊球阵列,所述焊球阵列围绕着芯片和封装天线的四周和非辐射方向排布。
9.如权利要求8所述的多馈封装天线,其特征在于,所述焊球阵列与外部的印制板上的金属走线连接。
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110125247.6A CN113013605B (zh) | 2021-01-29 | 2021-01-29 | 基于扇出封装的多馈封装天线 |
US17/206,479 US11569191B2 (en) | 2021-01-29 | 2021-03-19 | Multi-feed packaged antenna based on fan-out package |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN202110125247.6A CN113013605B (zh) | 2021-01-29 | 2021-01-29 | 基于扇出封装的多馈封装天线 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN113013605A true CN113013605A (zh) | 2021-06-22 |
CN113013605B CN113013605B (zh) | 2021-12-10 |
Family
ID=76385113
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN202110125247.6A Active CN113013605B (zh) | 2021-01-29 | 2021-01-29 | 基于扇出封装的多馈封装天线 |
Country Status (2)
Country | Link |
---|---|
US (1) | US11569191B2 (zh) |
CN (1) | CN113013605B (zh) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113394199A (zh) * | 2021-06-10 | 2021-09-14 | 邓天伟 | 一种半导体布置 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US11380979B2 (en) * | 2018-03-29 | 2022-07-05 | Intel Corporation | Antenna modules and communication devices |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107068659A (zh) * | 2017-04-19 | 2017-08-18 | 华进半导体封装先导技术研发中心有限公司 | 一种扇出型芯片集成天线封装结构及方法 |
CN107452720A (zh) * | 2017-08-03 | 2017-12-08 | 华天科技(昆山)电子有限公司 | 芯片扇出封装结构、多芯片集成模块及晶圆级封装方法 |
CN109244641A (zh) * | 2018-08-07 | 2019-01-18 | 清华大学 | 封装天线及其制造方法 |
CN109326584A (zh) * | 2018-08-07 | 2019-02-12 | 清华大学 | 封装天线及其制造方法 |
CN110211888A (zh) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | 一种嵌入式扇出封装结构及其制造方法 |
CN110993588A (zh) * | 2019-12-13 | 2020-04-10 | 青岛歌尔智能传感器有限公司 | 芯片模组及其制作方法和电子设备 |
Family Cites Families (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8278749B2 (en) * | 2009-01-30 | 2012-10-02 | Infineon Technologies Ag | Integrated antennas in wafer level package |
EP3381053A4 (en) * | 2015-11-24 | 2019-12-18 | Georgia Tech Research Corporation | BIDIRECTIONAL RADIO BASED ON OSCILLATORS WITH INTEGRATED ANTENNA |
US10700024B2 (en) | 2017-08-18 | 2020-06-30 | Samsung Electro-Mechanics Co., Ltd. | Fan-out semiconductor package |
-
2021
- 2021-01-29 CN CN202110125247.6A patent/CN113013605B/zh active Active
- 2021-03-19 US US17/206,479 patent/US11569191B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN107068659A (zh) * | 2017-04-19 | 2017-08-18 | 华进半导体封装先导技术研发中心有限公司 | 一种扇出型芯片集成天线封装结构及方法 |
CN107452720A (zh) * | 2017-08-03 | 2017-12-08 | 华天科技(昆山)电子有限公司 | 芯片扇出封装结构、多芯片集成模块及晶圆级封装方法 |
CN109244641A (zh) * | 2018-08-07 | 2019-01-18 | 清华大学 | 封装天线及其制造方法 |
CN109326584A (zh) * | 2018-08-07 | 2019-02-12 | 清华大学 | 封装天线及其制造方法 |
CN110211888A (zh) * | 2019-06-14 | 2019-09-06 | 上海先方半导体有限公司 | 一种嵌入式扇出封装结构及其制造方法 |
CN110993588A (zh) * | 2019-12-13 | 2020-04-10 | 青岛歌尔智能传感器有限公司 | 芯片模组及其制作方法和电子设备 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN113394199A (zh) * | 2021-06-10 | 2021-09-14 | 邓天伟 | 一种半导体布置 |
Also Published As
Publication number | Publication date |
---|---|
US20220246571A1 (en) | 2022-08-04 |
CN113013605B (zh) | 2021-12-10 |
US11569191B2 (en) | 2023-01-31 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
TWI716838B (zh) | 天線結構以及封裝天線 | |
US7675466B2 (en) | Antenna array feed line structures for millimeter wave applications | |
CA2637038C (en) | Apparatus and methods for packaging integrated cirguit chips with antennas formed from package lead wires | |
US7444734B2 (en) | Apparatus and methods for constructing antennas using vias as radiating elements formed in a substrate | |
US8179333B2 (en) | Antennas using chip-package interconnections for millimeter-wave wireless communication | |
US8164167B2 (en) | Integrated circuit structure and a method of forming the same | |
TW201728002A (zh) | 貼片天線單元及天線 | |
US20060276157A1 (en) | Apparatus and methods for packaging antennas with integrated circuit chips for millimeter wave applications | |
CN113013605B (zh) | 基于扇出封装的多馈封装天线 | |
WO2009111839A1 (en) | Integration of microstrip antenna with cmos transceiver | |
US11350522B2 (en) | Microwave antenna apparatus | |
CN111446535B (zh) | 电子封装件及其制法 | |
CN111128971A (zh) | 集成天线封装结构 | |
CN115425394B (zh) | 一种基于层叠式结构的带状线以及基于异质基材三维堆叠的层叠式阵面天线单元 | |
TWI762197B (zh) | 電子封裝件及其製法 | |
US11874515B2 (en) | Electronic device | |
CN210926005U (zh) | 集成天线封装结构 | |
CN113193333B (zh) | 一种应用于cmos工艺的分形结构片上天线 | |
CN117673721A (zh) | 一种宽带天线封装结构 | |
CN114122674A (zh) | 一种基于扇出封装工艺的毫米波封装天线 | |
CN116417785A (zh) | 电子封装件及其制法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
GR01 | Patent grant | ||
GR01 | Patent grant |