CN113013169B - NOR FLASH forming method - Google Patents

NOR FLASH forming method Download PDF

Info

Publication number
CN113013169B
CN113013169B CN202110209862.5A CN202110209862A CN113013169B CN 113013169 B CN113013169 B CN 113013169B CN 202110209862 A CN202110209862 A CN 202110209862A CN 113013169 B CN113013169 B CN 113013169B
Authority
CN
China
Prior art keywords
layer
flash memory
floating gate
region
trench isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN202110209862.5A
Other languages
Chinese (zh)
Other versions
CN113013169A (en
Inventor
田志
梁启超
邵华
陈昊瑜
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shanghai Huali Microelectronics Corp
Original Assignee
Shanghai Huali Microelectronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shanghai Huali Microelectronics Corp filed Critical Shanghai Huali Microelectronics Corp
Priority to CN202110209862.5A priority Critical patent/CN113013169B/en
Publication of CN113013169A publication Critical patent/CN113013169A/en
Application granted granted Critical
Publication of CN113013169B publication Critical patent/CN113013169B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

The invention provides a method for forming NOR FLASH, which comprises the following steps: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent; a flash memory oxide layer, a floating gate layer and a nitride layer are sequentially formed on the surface of the substrate, and the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area; sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide; removing the nitride layer of the flash memory region, and carrying out ion implantation and annealing on the floating gate layers of the flash memory region and the logic region, wherein part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory region; and removing the interlayer dielectric layer and the floating gate layer of the logic region to form a gate structure of the flash memory region. The invention can reduce the area of the flash memory unit and can ensure even erasure.

Description

NOR FLASH forming method
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for forming NOR FLASH.
Background
Flash memory has been widely used as the best choice for non-volatile memory applications due to its high density, low cost, electrically programmable and erasable advantages. At present, the flash memory unit is mainly performed at a 65 nanometer technology node, and with the requirement of a large-capacity flash memory, the number of chips on each silicon wafer is reduced by utilizing the prior technology node. Meanwhile, with the increasing maturity of new technology nodes, flash memory units are also urged to be produced by high-node technology. Meaning that the size of the flash memory cell needs to be reduced, however, reducing the active area width and the channel length of the flash memory cell both have an impact on the performance of the flash memory cell.
The current lateral scaling from 65nm to 55nm NOR FLASH, and thus to 50nm NOR FLASH, is mainly achieved by scaling the active area of the FLASH memory cell, and by scaling the distance between the active area and the active area. The existing floating gate mainly adopts a Fowerll-Norhei tunneling mode of a channel mode, and depends on the effective areas of a floating gate and a flash memory unit. Due to the reduced area, the number of silicon dioxide energy valleys generated by the doped phosphorus contained at the silicon dioxide interface between the floating gate and the flash oxide layer in each flash memory cell is reduced, resulting in reduced erase uniformity.
Disclosure of Invention
The invention aims to provide a method for forming NOR FLASH, which can reduce the area of a FLASH memory unit and can still ensure that erasure is kept uniform.
In order to achieve the above object, the present invention provides a method for forming a NOR FLASH, comprising:
providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent;
a flash memory oxide layer, a floating gate layer and a nitride layer are sequentially formed on the surface of the substrate, and the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area;
sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide;
removing the nitride layer of the flash memory region, and carrying out ion implantation and annealing on the floating gate layers of the flash memory region and the logic region, wherein part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure;
forming an interlayer dielectric layer on the floating gate layer of the flash memory region;
and removing the interlayer dielectric layer and the floating gate layer of the logic region to form a gate structure of the flash memory region.
Optionally, in the method for forming the NOR FLASH, before forming the FLASH oxide layer, the floating gate layer and the nitride layer on the surface of the substrate in sequence, the method further includes: forming an HVNW region and a CELL VT region within the substrate, and an HVPW region separating the HVNW region and the CELL VT region.
Optionally, in the method for forming NOR FLASH, a surface of the shallow trench isolation structure is lower than a surface of the nitride layer.
Optionally, in the method for forming a NOR FLASH, after removing the remaining nitride layer, the method further includes: the surface of the floating gate layer is flush with the surface of the shallow trench isolation structure.
Optionally, in the method for forming NOR FLASH, the material of the FLASH oxide layer is silicon dioxide.
Optionally, in the method for forming NOR FLASH, the oxide material is silicon dioxide.
Optionally, in the method for forming a NOR FLASH, the material of the nitride layer is silicon nitride.
Optionally, in the method for forming NOR FLASH, the doped ions include phosphorus ions.
Optionally, in the method for forming the NOR FLASH, the interlayer dielectric layer includes an ONO layer.
Optionally, in the method for forming a NOR FLASH, after removing the nitride layer above the FLASH memory region and performing ion implantation and annealing on the floating gate layer, the method further includes: and etching the shallow trench isolation structure of the flash memory region so that the surface of the shallow trench isolation structure is lower than the surface of the floating gate layer.
The method for forming the NOR FLASH provided by the invention comprises the following steps: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent; a flash memory oxide layer, a floating gate layer and a nitride layer are sequentially formed on the surface of the substrate, and the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area; sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide; removing the nitride layer of the flash memory region, and carrying out ion implantation and annealing on the floating gate layers of the flash memory region and the logic region, wherein ions enter the floating gate layer through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory region; and removing the interlayer dielectric layer and the floating gate layer of the logic region to form a gate structure of the flash memory region. And part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure, and the oxide carried by the part of ions prevents polysilicon at the bottom of the floating gate layer from crystallizing rapidly, so that the doping of polysilicon in contact with silicon dioxide is reduced, the corresponding grain size is also reduced, the grain boundary is more and the erasing is more uniform as the size occupied by the grains is reduced.
Drawings
Fig. 1 is a flow chart of a method of forming NOR FLASH according to an embodiment of the present invention;
FIGS. 2-6 are schematic diagrams of a method of forming NOR FLASH according to an embodiment of the present invention;
in the figure: 110-substrate, 110A-flash memory region, 110B-logic region, 111-HVNW region, 112-HVPW region, 113-CELL VT region, 120-flash oxide layer, 130-floating gate layer, 140-nitride layer, 150-shallow trench isolation structure, 160-interlayer dielectric layer.
Detailed Description
Specific embodiments of the present invention will be described in more detail below with reference to the drawings. The advantages and features of the present invention will become more apparent from the following description. It should be noted that the drawings are in a very simplified form and are all to a non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.
In the following, the terms "first," "second," and the like are used to distinguish between similar elements and are not necessarily used to describe a particular order or chronological order. It is to be understood that such terms so used are interchangeable under appropriate circumstances. Similarly, if a method described herein comprises a series of steps, and the order of the steps presented herein is not necessarily the only order in which the steps may be performed, and some of the described steps may be omitted and/or some other steps not described herein may be added to the method.
The inventor researches and discovers that one method for forming the NOR FLASH in the prior art is to form a FLASH memory oxide layer and a floating gate layer on a substrate respectively, then anneal the FLASH memory oxide layer and the floating gate layer, then form a shallow trench isolation structure, and etch the floating gate layer after the shallow trench isolation structure is formed to form a gate structure. Further research by the inventor finds that the grain size is increased due to the fact that the grains of the polycrystalline silicon in the floating gate layer are annealed after being doped with phosphorus ions, and then the grains are further increased in the formation of a later gate structure, so that the number of self-reduced silicon energy valleys is further reduced. Also, as the capacity of flash memory cells increases, the area of the flash memory cells is reduced more severely, resulting in less and more uniform erasure.
Referring to fig. 1, the present invention provides a method for forming a NOR FLASH, which includes:
s11: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent;
s12: a flash memory oxide layer, a floating gate layer and a nitride layer are sequentially formed on the surface of the substrate, and the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area;
s13: sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide;
s14: removing the nitride layer of the flash memory region, and carrying out ion implantation and annealing on the floating gate layers of the flash memory region and the logic region, wherein part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure;
s15: forming an interlayer dielectric layer on the floating gate layer of the flash memory region;
s16: and removing the interlayer dielectric layer and the floating gate layer of the logic region to form a gate structure of the flash memory region.
Specifically, referring to fig. 2, first, a substrate 110 is provided, and the substrate 100 includes a flash memory region 110A and a logic region 110B. The substrate 110 may be a silicon substrate or a germanium substrate, and in the embodiment of the present invention, a silicon substrate, for example, a wafer, is used. HVNW region 111, HVPW region 112, and CELL VT region 113 are formed within the substrate 110, respectively, with HVPW region 112 separating HVNW region 111 and CELL VT region 113. HVNW region 111 is the N-type well of the high voltage 5V device, HVPW region 112 is the P-type well of the high voltage 5V device, and CELL VT region 113 is the well of the tuning storage region. The forming method of the HVNW region 111, the HVPW region 112 and the CELL VT region 113 is a prior art, and will not be described herein.
Next, referring to fig. 3, a flash oxide layer 120 is formed on the surface of the substrate 110, the material of the flash oxide layer 120 may be oxide, specifically silicon dioxide, a floating gate layer 130 is formed on the flash oxide layer 120, the material of the floating gate layer 130 may be polysilicon, and a nitride layer 140 is formed on the floating gate layer 130, and the material of the nitride layer 140 may be silicon nitride. The flash oxide layer 120, the floating gate layer 130, and the nitride layer 140 are formed on the flash memory region 110A and the logic region 110B.
Next, referring to fig. 4, the nitride layer 140, the floating gate layer 130 and the flash oxide layer 120 of the flash memory region 110A and the logic region 110B are etched to form shallow trenches, and the shallow trenches are filled with an oxide such as silicon dioxide to form shallow trench isolation structures 150, that is, the shallow trench isolation structures 150 are filled with an oxide such as silicon dioxide, and the surface of the shallow trench isolation structures 150 is lower than the surface of the remaining nitride layer 140.
Next, referring to fig. 5, the remaining nitride layer 140 above the flash memory region 120A is removed, and the floating gate layer 130 of the flash memory region 110A and the logic region 110B is ion-implanted to dope the floating gate layer 130, and then annealed, wherein the implanted ions may be phosphorus ions, the energy of the implanted phosphorus ions is 10KeV to 25KeV, and the concentration of the implanted phosphorus ions is 2E15 atoms/cm 2 to 7E15 atoms/cm 2. When ions are injected into the floating gate layer 130, part of the ions are injected into the shallow trench isolation structure 150, part of the phosphorus ions are doped in the silicon dioxide during annealing, the part of the phosphorus ions can bring oxide (silicon dioxide) into the junction between the side wall of the shallow trench isolation structure 150 and the floating gate layer 130 and the junction between the bottom wall of the shallow trench isolation structure 150 and the floating gate layer 130, the growth of grains of the floating gate layer 130 at the junction is limited by the oxide (silicon dioxide), when the phosphorus ions in other areas outside the junction of the floating gate layer 130 enter the bottom of the floating gate layer 130, the grains at the bottom are in competition with the grains at the junction, the grains are slower than the original grains to be grown, the grain size is reduced, the size occupied by the grains is reduced, and the more the grains are erased, the more uniform the grains are. That is, the silicon dioxide enters the floating gate layer 130 through the sidewall of the shallow trench isolation structure 150, so that the polysilicon at the bottom of the floating gate layer 130 is prevented from crystallizing rapidly, the doping of the polysilicon contacting with the silicon dioxide is reduced, the corresponding grain size is also reduced, the size occupied by the grains is reduced, and the more grain boundaries, the more uniform the erasure. In the prior art, a FLASH memory oxide layer and a floating gate layer are respectively formed on a substrate, then annealing is carried out, then a shallow trench isolation structure is formed, and the floating gate layer is etched after the shallow trench isolation structure is formed to form a gate structure. Further research by the inventor finds that the grain size is increased due to the fact that the grains of the polycrystalline silicon in the floating gate layer are annealed after being doped with phosphorus ions, and then the grains are further increased in the formation of a later gate structure, so that the number of self-reduced silicon energy valleys is further reduced. Also, as the capacity of flash memory cells increases, the area of the flash memory cells is reduced more severely, resulting in less and more uniform erasure. The embodiment of the invention changes the sequence of the ion implantation and annealing steps in the formation method of the NOR FLASH, and can overcome the problem.
Next, referring to fig. 6, the shallow trench isolation structure 150 of the flash memory region 110A is etched so that the surface thereof is lower than the surface of the floating gate layer 130, and an interlayer dielectric layer 160 is formed on the remaining floating gate layer 130 of the flash memory region 110A, wherein the interlayer dielectric layer 160 is located on the ONO layer;
next, the interlayer dielectric layer 160 and the floating gate layer 130 of the logic region 110B are removed to form a gate structure of the flash memory region 110A.
In summary, the method for forming the NOR FLASH provided by the embodiment of the invention includes: providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent; a flash memory oxide layer, a floating gate layer and a nitride layer are sequentially formed on the surface of the substrate, and the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area; sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide; removing the nitride layer of the flash memory region, and carrying out ion implantation and annealing on the floating gate layers of the flash memory region and the logic region, wherein ions enter the floating gate layer through the side wall of the shallow trench isolation structure; forming an interlayer dielectric layer on the floating gate layer of the flash memory region; and removing the interlayer dielectric layer and the floating gate layer of the logic region to form a gate structure of the flash memory region. And part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure, and the oxide carried by the part of ions prevents polysilicon at the bottom of the floating gate layer from crystallizing rapidly, so that the doping of polysilicon in contact with silicon dioxide is reduced, the corresponding grain size is also reduced, the grain boundary is more and the erasing is more uniform as the size occupied by the grains is reduced.
The foregoing is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Any person skilled in the art will make any equivalent substitution or modification to the technical solution and technical content disclosed in the invention without departing from the scope of the technical solution of the invention, and the technical solution of the invention is not departing from the scope of the invention.

Claims (10)

1. A method for forming NOR FLASH, comprising:
providing a substrate, wherein the substrate comprises a flash memory area and a logic area which are adjacent;
a flash memory oxide layer, a floating gate layer and a nitride layer are sequentially formed on the surface of the substrate, and the flash memory oxide layer, the floating gate layer and the nitride layer are formed on the flash memory area and the logic area;
sequentially etching the nitride layer, the floating gate layer and the flash memory oxide layer to form a shallow trench isolation structure, wherein the filler of the shallow trench isolation structure is oxide;
removing the nitride layer of the flash memory region, and carrying out ion implantation and annealing on the floating gate layers of the flash memory region and the logic region, wherein part of ions enter the floating gate layer through the side wall of the shallow trench isolation structure;
forming an interlayer dielectric layer on the floating gate layer of the flash memory region;
and removing the interlayer dielectric layer and the floating gate layer of the logic region to form a gate structure of the flash memory region.
2. The method for forming the NOR FLASH as claimed in claim 1, wherein before the FLASH oxide layer, the floating gate layer and the nitride layer are sequentially formed on the surface of the substrate, the method further comprises: forming an HVNW region and a CELL VT region within the substrate, and an HVPW region separating the HVNW region and the CELL VT region.
3. The method of claim 1, wherein a surface of the shallow trench isolation structure is lower than a surface of the nitride layer.
4. The method of claim 1, further comprising, after removing the remaining nitride layer: the surface of the floating gate layer is flush with the surface of the shallow trench isolation structure.
5. The method of claim 1, wherein the FLASH memory oxide layer is silicon dioxide.
6. The method of claim 1, wherein the oxide material is silicon dioxide.
7. The method of claim 1, wherein the nitride layer is silicon nitride.
8. The method of forming NOR FLASH as claimed in claim 1, wherein the implanted ions comprise phosphorus ions.
9. The method of claim 1, wherein said interlayer dielectric layer comprises an ONO layer.
10. The method of claim 1, wherein after removing the nitride layer above the FLASH memory region and ion implanting and annealing the floating gate layer, further comprising: and etching the shallow trench isolation structure of the flash memory region so that the surface of the shallow trench isolation structure is lower than the surface of the floating gate layer.
CN202110209862.5A 2021-02-24 2021-02-24 NOR FLASH forming method Active CN113013169B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN202110209862.5A CN113013169B (en) 2021-02-24 2021-02-24 NOR FLASH forming method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN202110209862.5A CN113013169B (en) 2021-02-24 2021-02-24 NOR FLASH forming method

Publications (2)

Publication Number Publication Date
CN113013169A CN113013169A (en) 2021-06-22
CN113013169B true CN113013169B (en) 2023-06-16

Family

ID=76385968

Family Applications (1)

Application Number Title Priority Date Filing Date
CN202110209862.5A Active CN113013169B (en) 2021-02-24 2021-02-24 NOR FLASH forming method

Country Status (1)

Country Link
CN (1) CN113013169B (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114256256A (en) * 2021-12-09 2022-03-29 华虹半导体(无锡)有限公司 Method for manufacturing NOR flash memory device based on SAP (super oxide polymer) process
CN114695122B (en) * 2022-02-24 2026-02-03 上海华力集成电路制造有限公司 Method for manufacturing ultrathin metal gate

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6207504B1 (en) * 1998-07-29 2001-03-27 United Semiconductor Corp. Method of fabricating flash erasable programmable read only memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5013050B2 (en) * 2006-06-14 2012-08-29 富士通セミコンダクター株式会社 Manufacturing method of semiconductor device
CN102263110B (en) * 2011-08-12 2013-05-08 上海先进半导体制造股份有限公司 Electrically erasable programmable read-only memory (EEPROM) core structure formed by process embedded into monolithic integration process of manufacturing bipolar transistor, complementary metal oxide semiconductor (CMOS) device and double-diffusion metal oxide semiconductor (DMOS) device on identical chip (BCD) and forming method
CN108091658B (en) * 2017-11-16 2021-04-13 上海华力微电子有限公司 Process integration structure and method of flash memory
CN108039350B (en) * 2017-11-30 2020-09-01 上海华力微电子有限公司 Process integration method for improving reliability of grid oxide layer of high-voltage device in flash memory

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6207504B1 (en) * 1998-07-29 2001-03-27 United Semiconductor Corp. Method of fabricating flash erasable programmable read only memory

Also Published As

Publication number Publication date
CN113013169A (en) 2021-06-22

Similar Documents

Publication Publication Date Title
KR101878006B1 (en) Vertical memory device and method for making thereof
US6734063B2 (en) Non-volatile memory cell and fabrication method
US11610909B2 (en) Processes for forming 3-dimensional horizontal NOR memory arrays
US6885590B1 (en) Memory device having A P+ gate and thin bottom oxide and method of erasing same
JP5576400B2 (en) Flash memory device and manufacturing method thereof
US7928503B2 (en) Memory cells
US6400610B1 (en) Memory device including isolated storage elements that utilize hole conduction and method therefor
WO2000074139A1 (en) A single polysilicon flash eeprom and method for making same
US10714479B2 (en) One-transistor dram cell device based on polycrystalline silicon with FinFET structure and fabrication method thereof
US7265409B2 (en) Non-volatile semiconductor memory
US20090250746A1 (en) NOR-Type Flash Memory Cell Array and Method for Manufacturing the Same
CN113013169B (en) NOR FLASH forming method
US9299856B2 (en) Selective gate oxide properties adjustment using fluorine
US6894932B1 (en) Dual cell memory device having a top dielectric stack
KR100585097B1 (en) Ypyrom element and its manufacturing method
CN112397518B (en) Semiconductor structure and preparation method thereof
CN100466293C (en) Flash memory device and manufacturing method thereof
US10164073B2 (en) Apparatus and method for memory device
US20050173766A1 (en) Semiconductor memory and manufacturing method thereof
US8809147B2 (en) Dual conducting floating spacer metal oxide semiconductor field effect transistor (DCFS MOSFET) and method to fabricate the same
US6773990B1 (en) Method for reducing short channel effects in memory cells and related structure
CN117596878B (en) U-shaped floating gate type split gate embedded non-volatile memory and manufacturing method thereof
KR101033224B1 (en) Flash memory device and manufacturing method thereof
KR100209338B1 (en) Method for manufacturing non-voltile semiconductor memory device
CN1691336A (en) Buried bit line nonvolatile floating gate memory cell, its array and its manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant