CN113013037A - 3D semiconductor device and forming method thereof - Google Patents
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66484—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with multiple gate, at least one gate being an insulated gate
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42356—Disposition, e.g. buried gate electrode
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7831—Field effect transistors with field effect produced by an insulated gate with multiple gate structure
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Abstract
The invention provides a 3D semiconductor device and a forming method thereof, which are applied to the technical field of semiconductors. In the 3D semiconductor device forming method provided by the invention, two adjacent MOS devices share the grid, the grid and the drain/source of the MOS device are arranged on the surface of the semiconductor substrate, and the grid and the drain/source are horizontally connected, so that the channel length of the MOS device can be increased in a mode of increasing the grid width of the MOS device in the vertical direction, and the wafer area can be saved under the condition of reducing the short channel effect of the MOS device.
Description
Technical Field
The invention relates to the technical field of semiconductors, in particular to a 3D semiconductor device and a forming method thereof.
Background
Scaling of features in integrated circuits has been a driving force behind the continuing growth of the semiconductor industry over the past few decades. Scaling to smaller and smaller features enables increased density of functional units to be implemented on a limited chip area of a semiconductor chip. For example, shrinking transistor size allows for the incorporation of an increased number of memory or logic devices on a chip, thereby producing products with increased capacity. However, driving larger and larger capacities is not without problems. The necessity to optimize the performance of each device becomes increasingly important.
Currently, in the fabrication of integrated circuit devices, the size of MOS devices continues to shrink in order to pursue high performance of the devices and to save the chip area occupied by each device. However, as MOS devices continue to shrink, there is a concomitant decrease in the channel length of MOS devices and a thinner tunnel oxide thickness. However, short channel effects are induced when the size of the MOS device is reduced to a certain extent. Short channel effects will cause a reduction in the control capability of the gate of the MOS device, causing a shift in the threshold voltage and a drain induced barrier lowering effect, resulting in an increase in the static power consumption of the MOS device. Meanwhile, the reduced size of the device leads to the increase of the electric field inside the device, the generation of hot carriers is increased, and the reliability of the device is reduced.
Disclosure of Invention
The invention aims to provide a 3D semiconductor device and a forming method thereof, which aim to increase the channel length of an MOS device and finally realize the aim of inhibiting the short-channel effect of the device while saving the area of a chip occupied by the MOS device.
In a first aspect, to solve the above technical problem, the present invention provides a method for forming a semiconductor device, including:
providing a semiconductor substrate, wherein a plurality of discrete gate structures and a groove positioned between the adjacent gate structures are formed on the semiconductor substrate, and each gate structure comprises a first oxide layer, a gate material layer and a second oxide layer which are sequentially stacked along the direction far away from the semiconductor substrate;
forming a gate oxide layer exposing the semiconductor substrate on the bottom surface of the groove on the side wall of the groove, and covering a first semiconductor material layer on the side wall of the gate oxide layer and the bottom surface of the groove;
filling a third oxide layer in the trench, wherein the top surface of the third oxide layer is lower than the top surface of the first semiconductor material layer, so as to form an opening at the top end of the trench;
filling a second semiconductor material layer in the opening, wherein the second semiconductor material layer at least buries the third oxide layer and is connected with the first semiconductor material layer in the groove;
etching the gate structure, the second semiconductor material layer and the first semiconductor material layer to form a device isolation trench on the semiconductor substrate, wherein the device isolation trench defines a corresponding device region and enables at least two adjacent device regions to share the same gate structure;
and performing source-drain ion implantation on the second semiconductor material layer exposed on the side wall of the device isolation trench and the first semiconductor material layer to form a source region, a drain region and a channel region between the source region and the drain region, wherein the source region, the drain region and the channel region are respectively vertical to the gate structure.
Optionally, the materials of the first semiconductor material layer and the second semiconductor material layer may respectively include at least one of doped polysilicon, doped monocrystalline silicon, and doped germanium.
Optionally, the first semiconductor material layer may be covered on the sidewall of the gate oxide layer and the bottom surface of the trench by a method of depositing and then implanting N-type or P-type ions, or the first semiconductor material layer may be covered on the sidewall of the gate oxide layer and the bottom surface of the trench by a method of in-situ doping N-type or P-type ions.
Optionally, the second semiconductor material layer is filled in the opening by depositing and then injecting N-type or P-type ions, or the second semiconductor material layer is filled in the opening by in-situ doping N-type or P-type ions; the conductivity type of the ions doped in the second semiconductor material layer is opposite to the conductivity type of the ions doped in the first semiconductor material layer.
Optionally, the step of filling the trench with a third oxide layer may include:
depositing a third oxide layer, wherein the deposited third oxide layer at least fills the groove;
flattening the third oxide layer until the top surface of the third oxide layer is flush with the top surface of the second oxide layer;
and etching back the third oxide layer until the top surface of the third oxide layer is lowered to the required height.
Optionally, the step of forming the gate structure on the semiconductor substrate may include:
forming a first oxidation layer, a grid material layer, a second oxidation layer and a patterned photoresist layer on the semiconductor substrate from bottom to top in sequence;
and etching the first oxide layer, the gate material layer and the second oxide layer to the semiconductor substrate by taking the patterned photoresist layer as a mask so as to form a plurality of discrete gate structures, wherein the grooves are arranged between the adjacent gate structures.
Optionally, after the device isolation trench is formed and before source-drain ion implantation is performed on the second semiconductor material layer and the first semiconductor material layer exposed on the sidewall of the device isolation trench, a patterned photoresist layer is formed, where the patterned photoresist layer covers the top surface of the second semiconductor material layer in the device region and exposes the sidewall and the bottom surface of the device isolation trench; when source-drain ion implantation is carried out on the second semiconductor material layer exposed on the side wall of the device isolation ditch and the first semiconductor material layer, the patterned photoresist is used as a mask, and source-drain ion implantation is carried out on the second semiconductor material layer exposed on the side wall of the device isolation ditch and the first semiconductor material layer in an inclined ion implantation mode.
Optionally, after the device isolation trench is formed and before or after source-drain ion implantation is performed on the second semiconductor material layer and the first semiconductor material layer exposed on the sidewall of the device isolation trench, an insulating dielectric material may be filled in the device isolation trench to form a device isolation structure.
Optionally, after forming the source region, the drain region and the channel region, the forming method may further include:
forming an interlayer dielectric layer, wherein the interlayer dielectric layer buries the grid structure, the source region, the drain region and the channel region;
etching the interlayer dielectric layer to form a corresponding contact hole, wherein the bottom of the contact hole exposes a part of the top surface of at least one of the source region, the drain region, the channel region and the gate material layer in the gate structure;
and forming a conductive plug filled in the contact hole.
In a second aspect, based on the method for forming a semiconductor device as described above, the present invention also provides a 3D semiconductor device, including:
the semiconductor structure comprises a semiconductor substrate, wherein a plurality of discrete gate structures and a groove positioned between every two adjacent gate structures are formed on the semiconductor substrate, and each gate structure comprises a first oxide layer, a gate material layer and a second oxide layer which are sequentially stacked along the direction far away from the semiconductor substrate;
the gate oxide layer covers the side wall of the groove and exposes the semiconductor substrate on the bottom surface of the groove;
the first semiconductor material layer covers the side wall of the gate oxide layer and the bottom surface of the groove;
the third oxide layer is filled in the groove, and the top surface of the third oxide layer is lower than that of the first semiconductor material layer so as to form an opening at the top end of the groove;
the second semiconductor material layer is filled in the opening, at least the third oxide layer is buried in the second semiconductor material layer, and the second semiconductor material layer is connected with the first semiconductor material layer in the groove;
the device isolation structure is positioned on the semiconductor substrate, defines a corresponding device region and enables at least two adjacent device regions to share the same grid structure;
and source and drain regions, wherein source and drain ion implantation is performed on the second semiconductor material layer and the first semiconductor material layer exposed from the side wall of the device isolation trench corresponding to the device isolation structure to form a source region, a drain region and a channel region between the source region and the drain region, which are required by the device region, and the source region, the drain region and the channel region are all perpendicular to the gate structure.
Compared with the prior art, the technical scheme provided by the invention has at least one of the following beneficial effects:
in the 3D semiconductor device forming method provided by the invention, two adjacent MOS devices share the grid, the grid and the drain/source of the MOS device are arranged on the surface of the semiconductor substrate, and the grid and the drain/source are horizontally connected, so that the channel length of the MOS device can be increased in a mode of increasing the grid width of the MOS device in the vertical direction, and the wafer area can be saved under the condition of reducing the short channel effect of the MOS device.
Drawings
Fig. 1 is a flow chart illustrating a method for forming a semiconductor device according to an embodiment of the invention.
Fig. 2a to 2e are schematic structural diagrams of a method for forming a semiconductor device in a manufacturing process according to an embodiment of the invention.
Fig. 3 is a schematic top view of a 3D semiconductor device according to an embodiment of the invention.
Fig. 4 is a schematic three-dimensional structure diagram of a 3D semiconductor device according to an embodiment of the present invention.
Wherein the reference numbers are as follows:
100-a semiconductor substrate; 110-a first oxide layer;
120-a layer of gate material; 130-a second oxide layer;
140-a gate oxide layer; 150-a first layer of semiconductor material;
160-a third oxide layer; 170-a second semiconductor material layer;
101-a trench; 102-an opening;
251-a gate structure; 261-a device isolation structure;
A/B-N type ion or P type ion.
Detailed Description
As described in the background, in the fabrication of integrated circuit devices, the size of MOS devices is continuously reduced in order to achieve high performance of the devices and to save the chip area occupied by each device. However, as MOS devices continue to shrink, there is a concomitant decrease in the channel length of MOS devices and a thinner tunnel oxide thickness. However, short channel effects are induced when the size of the MOS device is reduced to a certain extent. Short channel effects will cause a reduction in the control capability of the gate of the MOS device, causing a shift in the threshold voltage and a drain induced barrier lowering effect, resulting in an increase in the static power consumption of the MOS device. Meanwhile, the reduced size of the device leads to the increase of the electric field inside the device, the generation of hot carriers is increased, and the reliability of the device is reduced.
Therefore, the invention provides a method for forming a semiconductor device, which aims to save the area of a chip occupied by an MOS device, increase the channel length of the MOS device and finally achieve the purpose of inhibiting the short-channel effect of the device.
Referring to fig. 1, fig. 1 is a schematic flow chart of a method for forming a semiconductor device according to an embodiment of the present invention, the method including the steps of:
step S100, providing a semiconductor substrate, wherein a plurality of discrete gate structures and a groove located between the adjacent gate structures are formed on the semiconductor substrate, and each gate structure comprises a first oxide layer, a gate material layer and a second oxide layer which are sequentially stacked along a direction far away from the semiconductor substrate.
And S200, forming a gate oxide layer exposing the semiconductor substrate on the bottom surface of the groove on the side wall of the groove, and covering a first semiconductor material layer on the side wall of the gate oxide layer and the bottom surface of the groove.
Step S300, filling a third oxide layer in the trench, where a top surface of the third oxide layer is lower than a top surface of the first semiconductor material layer, so as to form an opening at a top end of the trench.
Step S400, filling a second semiconductor material layer in the opening, wherein the second semiconductor material layer at least buries the third oxide layer therein and is connected to the first semiconductor material layer in the trench.
Step S500, etching the gate structure, the second semiconductor material layer, and the first semiconductor material layer to form a device isolation trench on the semiconductor substrate, where the device isolation trench defines a corresponding device region and enables at least two adjacent device regions to share the same gate structure.
Step S600, performing source-drain ion implantation on the second semiconductor material layer and the first semiconductor material layer exposed on the sidewall of the device isolation trench to form a source region, a drain region and a channel region between the source region and the drain region, which are required by the device region, and the source region, the drain region and the channel region are all perpendicular to the gate structure.
That is, in the forming method of the 3D semiconductor device provided by the present invention, the gate is shared by two adjacent MOS devices, and the gate and the drain/source of the MOS device are both disposed on the surface of the semiconductor substrate, and the gate and the drain/source are horizontally connected, so that the channel length of the MOS device can be increased by increasing the gate width of the MOS device in the vertical direction, and the wafer area can be saved while reducing the short channel effect of the MOS device.
The 3D semiconductor device and the method for forming the same according to the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description. It is to be noted that the drawings are in a very simplified form and are not to precise scale, which is merely for the purpose of facilitating and distinctly claiming the embodiments of the present invention.
Fig. 2a to 2e are schematic structural diagrams of a method for forming a semiconductor device in a manufacturing process according to an embodiment of the invention.
In step S100, specifically referring to fig. 2a, a semiconductor substrate 100 is provided, a plurality of discrete gate structures 251 and trenches 101 located between adjacent gate structures 251 are formed on the semiconductor substrate 100, and the gate structures 251 include a first oxide layer 110, a gate material layer 120 and a second oxide layer 130 sequentially stacked and disposed along a direction away from the semiconductor substrate 100. The semiconductor substrate 100 is used to provide an operating platform for the subsequent process to form a MOS device or a CMOS device. The material of the semiconductor substrate 100 is selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the semiconductor substrate 100 may also be selected from compounds such as silicon, germanium, gallium arsenide, or silicon germanium; the semiconductor substrate 100 may also be other semiconductor materials. Illustratively, in the embodiment of the present invention, the semiconductor substrate 100 is a silicon substrate.
In this embodiment, the first oxide layer 110 and the second oxide layer 130 may be silicon dioxide, or may be a layer of insulating material such as silicon nitride, which functions as a gate for isolating the device located between the two, which is trenched by the gate material layer 120. The gate material layer 120 may be a polysilicon layer or a metal gate layer.
Optionally, a specific manner of forming the gate structure on the semiconductor substrate 100 is provided in the embodiment of the present invention, which may include the following steps:
first, a first oxide layer 110, a gate material layer 120, a second oxide layer 130 and a patterned photoresist layer (not shown) are sequentially formed on the semiconductor substrate 100 from bottom to top;
next, the patterned photoresist layer is used as a mask to etch the first oxide layer 110, the gate material layer 120, and the second oxide layer 130 to the semiconductor substrate 100, so as to form a plurality of discrete gate structures 251, wherein the trenches 101 are formed between adjacent gate structures 251.
In step S200, with continued reference to fig. 2a, a gate oxide layer 140 exposing the semiconductor substrate 100 on the bottom surface of the trench 101 is formed on the sidewall of the trench 101, and a first semiconductor material layer 150 is covered on the sidewall of the gate oxide layer 140 and the bottom surface of the trench 101.
In this embodiment, an atomic deposition process may be used to form a gate oxide layer 140 with a certain thickness on the sidewall of the trench 101, the bottom of the trench 101, and the top surface of the gate structure 251, and then a dry etching process is used to remove the gate oxide layer 140 on the top surface of the gate structure 251, so as to serve as a tunneling oxide layer of the vertically-distributed 3D semiconductor device provided in the present invention. Then, a first semiconductor material layer 150 having a U-shaped structure is formed in the trench 101 formed with the gate oxide layer 140, so as to form a source region, a drain region and a channel region of the 3D semiconductor device proposed by the present invention in the trench 101 through subsequent steps.
Wherein, the material of the first semiconductor material layer 150 may be selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the first semiconductor material layer 150 may also be selected from compounds such as silicon, germanium, gallium arsenide, or silicon germanium; the first semiconductor material layer 150 may also be other semiconductor materials. Illustratively, the material of the first semiconductor material layer 150 in the embodiment of the present invention may further include at least one of doped polysilicon, doped monocrystalline silicon, and doped germanium.
Alternatively, referring to fig. 2b specifically and in conjunction with fig. 2a, the step S200 of forming the gate oxide layer 140 on the sidewall of the trench 101 to expose the semiconductor substrate 100 on the bottom surface of the trench 101, and covering the first semiconductor material layer 150 on the sidewall of the gate oxide layer 140 and the bottom surface of the trench 101 may specifically be:
the first semiconductor material layer 150 is covered on the side wall of the gate oxide layer 140 and the bottom surface of the trench 101 by means of depositing and then injecting N-type or P-type ions, or the first semiconductor material layer 150 is covered on the side wall of the gate oxide layer 140 and the bottom surface of the trench 101 by means of in-situ doping of N-type or P-type ions.
In this embodiment, in order to improve the conductivity of the first semiconductor material layer 150, it is necessary to perform ion implantation into the first semiconductor material layer 150. Instead, the first semiconductor material layer 150 is first deposited in the trench 101, and then ion implantation is performed thereon; or directly covering the doped first semiconductor material layer 150 on the sidewall of the gate oxide layer 140 and the bottom surface of the trench 101 by in-situ doping with N-type or P-type ions, which is not limited in this invention. Specifically, whether the first semiconductor material layer 150 is subjected to N-type ion implantation or P-type ion implantation needs to be defined according to the type of the 3D semiconductor device to be formed. Illustratively, if the 3D semiconductor device to be formed is a PMOS transistor, N-type ion implantation is performed on the first semiconductor material layer 150, as shown in a of fig. 2 b.
Wherein the N-type ions may include at least one of phosphorus, arsenic and antimony, and the P-type ions may include at least one of boron, boron fluoride, indium and gallium.
In step S300, referring to fig. 2c specifically, a third oxide layer 160 is filled in the trench 101, and a top surface of the third oxide layer 160 is lower than a top surface of the first semiconductor material layer 150, so as to form an opening 102 at a top end of the trench 101.
The third oxide layer 160 may be an insulating material layer such as silicon dioxide and silicon nitride, and is used as an isolation dielectric layer of a source region and a drain region between adjacent devices.
In this embodiment, a third oxide layer 160 may be deposited in the trench 101, and the deposited third oxide layer 160 at least fills the trench 101; then, a planarization process is used to planarize the third oxide layer 160 until the top surface of the third oxide layer 160 is flush with the top surface of the second oxide layer 120; then, the third oxide layer 160 is etched back until the top surface of the third oxide layer 160 is lowered to a desired height, so as to form an opening 102 at the top of the trench 101.
In step S400, referring to fig. 2d, a second semiconductor material layer 170 is filled in the opening 102, and the second semiconductor material layer 170 at least buries the third oxide layer 160 therein and is connected to the first semiconductor material layer 150 in the trench 101.
Wherein, the material of the second semiconductor material layer 170 may be selected from monocrystalline silicon, polycrystalline silicon or amorphous silicon; the second semiconductor material layer 170 may also be selected from compounds such as silicon, germanium, gallium arsenide, or silicon germanium; the second semiconductor material layer 170 may also be other semiconductor materials. Illustratively, the material of the second semiconductor material layer 170 in the embodiment of the present invention may further include at least one of doped polysilicon, doped monocrystalline silicon, and doped germanium.
In this embodiment, the opening 102 formed in the step S300 may be filled with the second semiconductor material layer 170, so that the trench 101 between two adjacent gate structures 251 forms a base for forming a source region, a drain region and a channel region of the 3D semiconductor device proposed by the present invention, so that the gate structure, the source region, the drain region and the channel region of the formed 3D semiconductor device are all formed on the semiconductor substrate 100, and the gate structure of the 3D semiconductor device is horizontally connected to the base forming the source region, the drain region and the channel region thereof.
Optionally, in the embodiment of the present invention, the second semiconductor material layer 170 may be filled in the opening 102 by depositing and then implanting N-type or P-type ions, or the second semiconductor material layer 107 may be filled in the opening 102 by in-situ doping N-type or P-type ions; the conductivity type of the ions doped in the second semiconductor material layer 170 is opposite to the conductivity type of the ions doped in the first semiconductor material layer 150.
In this embodiment, the second semiconductor material layer 170 is formed in the same manner as the first semiconductor material layer 150, and the description of the present invention is omitted.
In step S500, referring to fig. 2d in particular, and referring to fig. 3, the gate structure 251, the second semiconductor material layer 170, and the first semiconductor material layer 150 are etched to form a device isolation trench (not shown) on the semiconductor substrate 100, where the device isolation trench (not shown) defines a corresponding device region and enables at least two adjacent device regions to share the same gate structure 251.
In this embodiment, after the second semiconductor material layer 170 formed in the trench 101 is connected to the first semiconductor material layer 150 formed in the trench 101 in step S400 to form a base for forming a source region, a drain region and a channel region of a semiconductor device, the gate structure 251 and the base, which are formed on the semiconductor substrate 100 and horizontally connected, may be etched by using a photolithography and etching process to form the device isolation trench for an adjacent semiconductor device.
In step S600, referring to fig. 2e specifically, source/drain ion implantation is performed on the second semiconductor material layer 170 and the first semiconductor material layer 150 exposed on the sidewall of the device isolation trench to form a source region S and a drain region D required by the corresponding device region and a channel region located between the source region and the drain region, where the source region S, the drain region D and the channel region are all perpendicular to the gate structure 251.
In this embodiment, after the device isolation trench is formed and before the source/drain ion implantation is performed on the second semiconductor material layer 170 and the first semiconductor material layer 150 exposed on the sidewall of the device isolation trench, a patterned photoresist layer (not shown) may be formed, where the patterned photoresist layer covers the top surface of the second semiconductor material layer 170 in the device region and exposes the sidewall and the bottom surface of the device isolation trench; when source and drain ion implantation is performed on the second semiconductor material layer 170 exposed on the side wall of the device isolation trench and the first semiconductor material layer 150, the patterned photoresist is used as a mask, and source and drain ion implantation is performed on the second semiconductor material layer 170 exposed on the side wall of the device isolation trench and the first semiconductor material layer 150 in an inclined ion implantation mode.
Specifically, after the device isolation trench is formed and before or after source-drain ion implantation is performed on the second semiconductor material layer 170 and the first semiconductor material layer 150 exposed on the sidewall of the device isolation trench, an insulating dielectric material is filled in the device isolation trench to form a device isolation structure 261.
In this embodiment, when performing source-drain ion implantation in an inclined ion implantation manner on the second semiconductor material layer 170 and the first semiconductor material layer 150 exposed on the sidewall of the device isolation trench, the inclination angle may be adaptively adjusted according to the width of the device isolation structure 261, so as to perform uniform ion implantation on the second semiconductor material layer 170 and the first semiconductor material layer 150. For example, assuming that the width of the device isolation structure 261 is 1.6nm, the range of the inclination angle of the source and drain during ion implantation may be 10-15 °.
Optionally, after forming the source region S, the drain region D, and the channel region, the forming method further includes:
forming an interlayer dielectric layer (not shown) that buries all of the gate structure 251, the source region S, the drain region D, and the channel region;
etching the interlayer dielectric layer to form a corresponding contact hole (not shown), wherein the bottom of the contact hole exposes a part of the top surface of at least one of the source region S, the drain region D, the channel region and the gate material layer 120 in the gate structure 251;
conductive plugs (not shown) filled in the contact holes are formed.
Therefore, in the forming method of the 3D semiconductor device provided by the invention, the grid is shared by two adjacent MOS devices, the grid and the drain/source of the MOS device are arranged on the surface of the semiconductor substrate, and the grid and the drain/source are horizontally connected, so that the channel length of the MOS device can be increased in a mode of increasing the grid width of the MOS device in the vertical direction, and the wafer area can be saved under the condition of reducing the short channel effect of the MOS device.
In addition, based on the above method for forming a semiconductor device, the present embodiment further provides a 3D semiconductor device, including:
the semiconductor structure comprises a semiconductor substrate 100, wherein a plurality of discrete gate structures 251 and trenches 101 located between the adjacent gate structures 251 are formed on the semiconductor substrate 100, and the gate structures 251 comprise a first oxide layer 110, a gate material layer 120 and a second oxide layer 130 which are sequentially stacked and arranged along a direction far away from the semiconductor substrate 100;
a gate oxide layer 140 covering the sidewall of the trench 101 and exposing the semiconductor substrate 100 on the bottom surface of the trench 101;
a first semiconductor material layer 150 covering the side wall of the gate oxide layer 140 and the bottom surface of the trench 101;
a third oxide layer 160, wherein the third oxide layer 160 is filled in the trench 101, and a top surface of the third oxide layer 160 is lower than a top surface of the first semiconductor material layer 150, so as to form an opening 102 at a top end of the trench 101;
a second semiconductor material layer 170, wherein the second semiconductor material layer 170 is filled in the opening 102, and the second semiconductor material layer 170 at least buries the third oxide layer 160 therein and is connected to the first semiconductor material layer 150 in the trench 101;
a device isolation structure 261 located on the semiconductor substrate 100, wherein the device isolation structure 261 defines a corresponding device region and enables at least two adjacent device regions to share the same gate structure 251;
and a source region S and a drain region D, performing source-drain ion implantation on the second semiconductor material layer 170 and the first semiconductor material layer 160 exposed on the sidewall of the device isolation trench corresponding to the device isolation structure to form the source region S and the drain region D required by the corresponding device region and a channel region located between the source region S and the drain region D, wherein the source region, the drain region and the channel region are all perpendicular to the gate structure 251.
For example, for ease of understanding, the three-dimensional structure of the semiconductor device formed by the embodiments of the present invention may include a row array and a column array, as shown in fig. 4. Wherein the content of the first and second substances,
a row array including a plurality of mutually independent row units, each row unit including a plurality of devices such as MOS devices forming a common gate 130 on a semiconductor substrate (not shown), the MOS devices including the gate structure and having a three-dimensional solid structure including a source S and a drain D;
the array comprises a plurality of mutually independent array units, each array unit comprises a plurality of mutually independent grid structures, each grid structure comprises a first oxide layer 110, a grid material layer 130 and a second oxide layer which are sequentially stacked along the direction far away from the semiconductor substrate (not shown), and the side walls of the two sides of each grid structure are covered with grid oxide layers;
and a device isolation structure 261 between adjacent row cells and adjacent column cells.
Further, the three-dimensional stereo structure including the source S and the drain D is disposed between two adjacent shared gates 130 in each row of the cells, so that the adjacent shared gates 130 are horizontally connected along a horizontal direction by the three-dimensional stereo structure to form two devices sharing the three-dimensional stereo structure including the source S and the drain D.
In summary, in the forming method of the 3D semiconductor device provided by the present invention, two adjacent MOS devices share a gate, and the gate and the drain/source of the MOS device are both disposed on the surface of the semiconductor substrate, and the gate and the drain/source are horizontally connected, so that the channel length of the MOS device can be increased by increasing the gate width of the MOS device in the vertical direction, and the wafer area can be saved while reducing the short channel effect of the MOS device.
In addition, the embodiment of the invention also provides an electronic device, which comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus,
a memory for storing a computer program;
and the processor is used for realizing the method for forming the semiconductor device provided by the embodiment of the invention when executing the program stored in the memory.
In addition, other implementation manners of the auxiliary graph adding method implemented by the processor executing the program stored in the memory are the same as the implementation manners mentioned in the foregoing method embodiment section, and are not described again here.
The communication bus mentioned above for the control terminal may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, or the like. The communication bus may be divided into an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown, but this does not mean that there is only one bus or one type of bus.
The communication interface is used for communication between the electronic equipment and other equipment.
The Memory may include a Random Access Memory (RAM) or a Non-Volatile Memory (NVM), such as at least one disk Memory. Optionally, the memory may also be at least one memory device located remotely from the processor.
The Processor may be a general-purpose Processor, including a Central Processing Unit (CPU), a Network Processor (NP), and the like; but also Digital Signal Processors (DSPs), Application Specific Integrated Circuits (ASICs), Field Programmable Gate Arrays (FPGAs) or other Programmable logic devices, discrete Gate or transistor logic devices, discrete hardware components.
In still another embodiment provided by the present invention, there is also provided a computer-readable storage medium having stored therein instructions, which, when run on a computer, cause the computer to execute the method for forming a semiconductor device described in any of the above embodiments.
In the above embodiments, the implementation may be wholly or partially realized by software, hardware, firmware, or any combination thereof. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When loaded and executed on a computer, cause the processes or functions described in accordance with the embodiments of the invention to occur, in whole or in part. The computer may be a general purpose computer, a special purpose computer, a network of computers, or other programmable device. The computer instructions may be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another, for example, from one website site, computer, server, or data center to another website site, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, Digital Subscriber Line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.). The computer-readable storage medium can be any available medium that can be accessed by a computer or a data storage device, such as a server, a data center, etc., that incorporates one or more of the available media. The usable medium may be a magnetic medium (e.g., floppy Disk, hard Disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., Solid State Disk (SSD)), among others.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, as for the apparatus, the electronic device, and the computer-readable storage medium embodiments, since they are substantially similar to the method embodiments, the description is relatively simple, and in relation to the description, reference may be made to some portions of the description of the method embodiments.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (10)
1. A method of forming a semiconductor device, comprising:
providing a semiconductor substrate, wherein a plurality of discrete gate structures and a groove positioned between the adjacent gate structures are formed on the semiconductor substrate, and each gate structure comprises a first oxide layer, a gate material layer and a second oxide layer which are sequentially stacked along the direction far away from the semiconductor substrate;
forming a gate oxide layer exposing the semiconductor substrate on the bottom surface of the groove on the side wall of the groove, and covering a first semiconductor material layer on the side wall of the gate oxide layer and the bottom surface of the groove;
filling a third oxide layer in the trench, wherein the top surface of the third oxide layer is lower than the top surface of the first semiconductor material layer, so as to form an opening at the top end of the trench;
filling a second semiconductor material layer in the opening, wherein the second semiconductor material layer at least buries the third oxide layer and is connected with the first semiconductor material layer in the groove;
etching the gate structure, the second semiconductor material layer and the first semiconductor material layer to form a device isolation trench on the semiconductor substrate, wherein the device isolation trench defines a corresponding device region and enables at least two adjacent device regions to share the same gate structure;
and performing source-drain ion implantation on the second semiconductor material layer exposed on the side wall of the device isolation trench and the first semiconductor material layer to form a source region, a drain region and a channel region between the source region and the drain region, wherein the source region, the drain region and the channel region are respectively vertical to the gate structure.
2. The method of forming of claim 1, wherein the material of the first layer of semiconductor material and the second layer of semiconductor material each comprises at least one of doped polysilicon, doped monocrystalline silicon, and doped germanium.
3. The method of claim 1, wherein the first layer of semiconductor material is deposited on the sidewalls of the gate oxide layer and the bottom surface of the trench by a first deposition followed by an N-type or P-type ion implantation, or wherein the first layer of semiconductor material is deposited on the sidewalls of the gate oxide layer and the bottom surface of the trench by an in-situ N-type or P-type ion doping.
4. The method of claim 3, wherein the second semiconductor material layer is filled in the opening by a deposition followed by an N-type or P-type ion implantation, or by an in-situ doping of N-type or P-type ions; the conductivity type of the ions doped in the second semiconductor material layer is opposite to the conductivity type of the ions doped in the first semiconductor material layer.
5. The method of claim 1, wherein filling a third oxide layer in the trench comprises:
depositing a third oxide layer, wherein the deposited third oxide layer at least fills the groove;
flattening the third oxide layer until the top surface of the third oxide layer is flush with the top surface of the second oxide layer;
and etching back the third oxide layer until the top surface of the third oxide layer is lowered to the required height.
6. The method of forming of claim 1, wherein forming the gate structure on the semiconductor substrate comprises:
forming a first oxidation layer, a grid material layer, a second oxidation layer and a patterned photoresist layer on the semiconductor substrate from bottom to top in sequence;
and etching the first oxide layer, the gate material layer and the second oxide layer to the semiconductor substrate by taking the patterned photoresist layer as a mask so as to form a plurality of discrete gate structures, wherein the grooves are arranged between the adjacent gate structures.
7. The method of claim 1, wherein after forming the device isolation trench and before performing source-drain ion implantation on the second semiconductor material layer and the first semiconductor material layer exposed at the sidewall of the device isolation trench, a patterned photoresist layer is formed, wherein the patterned photoresist layer covers a top surface of the second semiconductor material layer in the device region and exposes the sidewall and a bottom surface of the device isolation trench; when source-drain ion implantation is carried out on the second semiconductor material layer exposed on the side wall of the device isolation ditch and the first semiconductor material layer, the patterned photoresist is used as a mask, and source-drain ion implantation is carried out on the second semiconductor material layer exposed on the side wall of the device isolation ditch and the first semiconductor material layer in an inclined ion implantation mode.
8. The method of claim 1, wherein after forming the device isolation trench and before or after performing source drain ion implantation on the second semiconductor material layer and the first semiconductor material layer exposed at the sidewall of the device isolation trench, an insulating dielectric material is filled in the device isolation trench to form a device isolation structure.
9. The method of forming of claim 1, wherein after forming the source region, the drain region, and the channel region, the method of forming further comprises:
forming an interlayer dielectric layer, wherein the interlayer dielectric layer buries the grid structure, the source region, the drain region and the channel region;
etching the interlayer dielectric layer to form a corresponding contact hole, wherein the bottom of the contact hole exposes a part of the top surface of at least one of the source region, the drain region, the channel region and the gate material layer in the gate structure;
and forming a conductive plug filled in the contact hole.
10. A3D semiconductor device, comprising:
the semiconductor structure comprises a semiconductor substrate, wherein a plurality of discrete gate structures and a groove positioned between every two adjacent gate structures are formed on the semiconductor substrate, and each gate structure comprises a first oxide layer, a gate material layer and a second oxide layer which are sequentially stacked along the direction far away from the semiconductor substrate;
the gate oxide layer covers the side wall of the groove and exposes the semiconductor substrate on the bottom surface of the groove;
the first semiconductor material layer covers the side wall of the gate oxide layer and the bottom surface of the groove;
the third oxide layer is filled in the groove, and the top surface of the third oxide layer is lower than that of the first semiconductor material layer so as to form an opening at the top end of the groove;
the second semiconductor material layer is filled in the opening, at least the third oxide layer is buried in the second semiconductor material layer, and the second semiconductor material layer is connected with the first semiconductor material layer in the groove;
the device isolation structure is positioned on the semiconductor substrate, defines a corresponding device region and enables at least two adjacent device regions to share the same grid structure;
and source and drain regions, wherein source and drain ion implantation is performed on the second semiconductor material layer and the first semiconductor material layer exposed from the side wall of the device isolation trench corresponding to the device isolation structure to form a source region, a drain region and a channel region between the source region and the drain region, which are required by the device region, and the source region, the drain region and the channel region are all perpendicular to the gate structure.
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