CN113008384A - Low-noise sampling circuit applied to infrared detector - Google Patents
Low-noise sampling circuit applied to infrared detector Download PDFInfo
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Abstract
A low noise sampling circuit for use in an infrared detector, comprising: the system comprises a signal impedance matching unit, a level matching unit, a filtering unit, an analog-to-digital conversion unit and an ultra-sampling digital filtering processing unit. The effect is as follows: the low-noise sampling circuit of the infrared detector has the advantages of low noise, small volume and the like, and can normally work under the conditions of minus 55 ℃ to plus 85 ℃; the frequency domain processing with poor effect due to serious noise aliasing is avoided, the pixel-level super-sampling time domain information is better utilized, and the sampling precision and the signal-to-noise ratio can be effectively improved.
Description
Technical Field
The invention relates to a low-noise sampling circuit applied to an infrared detector, and belongs to the technical field of signal processing.
Background
Infrared imaging is becoming more and more widely used in civilian, medical and military applications. Meanwhile, people have higher and higher requirements on image quality in the infrared imaging system. The particularity of the analog signal output by the infrared detector needs a low-noise sampling circuit meeting high requirements, the design of the sampling circuit determines the detection distance and the identification distance of an infrared imaging system, and the low-noise sampling circuit applied to the infrared detector has the advantages of low noise, small size and the like, and can normally work under the conditions of-55 ℃ to +85 ℃.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: the defects of the prior art are overcome, the low-noise sampling circuit applied to the infrared detector is provided, frequency domain processing with poor effect due to serious noise aliasing is avoided, pixel-level super-sampling time domain information is better utilized, and sampling precision and signal-to-noise ratio can be effectively improved.
The technical scheme of the invention is as follows:
a low noise sampling circuit for use in an infrared detector, comprising: the system comprises a signal impedance matching unit, a level matching unit, a filtering unit, an analog-to-digital conversion unit and an ultra-sampling digital filtering processing unit;
the signal impedance matching unit is the input end of a signal, the output end of the signal impedance matching unit is connected with the level matching unit, and the level matching unit is connected with the analog-to-digital conversion unit through the filtering unit; the impedance matching unit adopts a TLV3544 chip of Texas instruments; the level matching unit adopts an ADA4932-1 chip of Adenoki; the analog-to-digital conversion unit adopts an AD9645 chip of Addeno company; the ultra-sampling digital filtering unit is realized in an FPGA (field programmable gate array), and the FPGA adopts an A7 series of Xilinx company;
after an analog signal output by the infrared detector passes through the signal impedance matching unit, the signal level matching unit, the filtering unit and the analog-to-digital conversion unit, the FPGA finishes oversampling on the signal and performs digital filtering processing.
The signal impedance matching unit includes: a TLV3544 chip N1, a pull-down resistor R1, a capacitor C1 and a resistor R2;
one end of the pull-down resistor R1 is used as an input end to receive an externally input Vout1 signal (namely, an analog signal output by the infrared detector), one end of the pull-down resistor R1 is connected with the positive input end of the TLV3544 chip N1, and the other end of the pull-down resistor R1 is grounded; one end of the capacitor C1 is connected with an external power supply and a power supply end of the TLV3544 chip N1, and the other end of the capacitor C1 is grounded; the grounding end of the TLV3544 chip N1 is grounded, one end of a resistor R2 is connected with the inverted input end of the TLV3544 chip N1, and the other end of a resistor R2 is connected with the output end of the TLV3544 chip N1; the other end of the resistor R2 is connected as an output terminal to the level matching unit.
Signal level matching unit and filtering unit includes: an ADA4932-1 chip N2, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a capacitor C8, a capacitor C12, a capacitor C18 and a capacitor C13;
one end of the resistor R6 is used as an input end to receive an input signal VO1 sent by the signal impedance matching unit, and the other end of the resistor R6 is connected with one end of the capacitor C8, one end of the resistor R7 and the positive input end of the ADA4932-1 chip N2; the other end of the capacitor C8 is connected with the other end of the resistor R7 and a terminal pin 1 of the ADA4932-1 chip N2;
one end of the capacitor C12 is connected with an external power supply and a power supply end of the ADA4932-1 chip N2, and the other end of the capacitor C12 is grounded;
the ADA4932-1 chip N2 pin 9 is used for receiving VCM signals;
one end of the resistor R9 is used for receiving a VREF signal, and the other end of the resistor R9 is connected with the inverse input end of the ADA4932-1 chip N2, one end of the resistor R10 and one end of the capacitor C18; the other end of the resistor R10 is connected with the other end of the capacitor C18 and an ADA4932-1 chip N2 terminal pin 4; grounding the grounding end of the ADA4932-1 chip N2;
one end of the resistor R8 is connected with the negative output end of the ADA4932-1 chip N2, and the other end of the resistor R8 is connected with one end of the capacitor C13 and serves as a reverse output end;
one end of the resistor R11 is connected with the positive output end of the ADA4932-1 chip N2, and the other end of the resistor R11 is connected with the other end of the capacitor C13 and serves as a positive output end.
The analog-to-digital conversion unit includes: an AD9645 chip N3, a resistor R4, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C14, a capacitor C15, a capacitor C16 and a capacitor C17;
the AD9645 chip N3 has 6 AVDD pins, each two AVDD pins are connected with two capacitors connected in parallel, namely a capacitor C5, a capacitor C4, a capacitor C2, a capacitor C3, a capacitor C7 and a capacitor C6; the capacitor C14 and the capacitor C15 are connected in parallel to form a decoupling circuit which is connected with DRVDD and DGND, and the capacitor C16 and the capacitor C17 are connected in parallel to be connected with DRVDD and DGND; the capacitor C9 is connected with the capacitor C10 in parallel and connected with VREF and AGND;
one end of the resistor R4 is connected with an RBIAS port of the AD9645 chip N3, and the other end of the resistor R4 is grounded AGND;
one end of the capacitor C11 is connected to the VCM port of the AD9645 chip N3, and the other end of the capacitor C11 is grounded AGND.
And an FPGA chip XC7A100T-2CSG324I of Xilinx company is adopted to complete the ultra-sampling digital filtering processing unit.
The oversampling frequency is set to be 16 times of the output frequency of the detector pixel, and eight data are taken for average processing.
Compared with the prior art, the invention has the beneficial effects that:
the low-noise sampling circuit of the infrared detector has the advantages of low noise, small volume and the like, and can normally work under the conditions of minus 55 ℃ to plus 85 ℃.
Drawings
FIG. 1 is a diagram of an impedance matching unit of the present invention;
FIG. 2 is a diagram of a level matching and filtering unit according to the present invention;
FIG. 3 is a diagram of an analog-to-digital conversion unit according to the present invention.
Detailed Description
The invention is described in further detail below with reference to the figures and the detailed description.
The invention relates to a low-noise sampling circuit applied to an infrared detector, which comprises: the system comprises a signal impedance matching unit, a level matching unit, a filtering unit, an analog-to-digital conversion unit and an ultra-sampling digital filtering processing unit;
the signal impedance matching unit is the input end of a signal, the output end of the signal impedance matching unit is connected with the level matching unit, and the level matching unit is connected with the analog-to-digital conversion unit through the filtering unit; the impedance matching unit adopts TLV3544 chip of Texas Instruments (TI); the level matching unit adopts an ADA4932-1 chip of Addeno (ADI); the analog-to-digital conversion unit adopts an AD9645 chip of Addeno (ADI); the ultra-sampling digital filtering unit is realized in an FPGA (field programmable gate array), and the FPGA adopts an A7 series of Xilinx company;
and (3) signal processing flow: after an analog signal output by the infrared detector passes through the signal impedance matching unit, the signal level matching unit, the filtering unit and the analog-to-digital conversion unit, the FPGA finishes oversampling on the signal and performs digital filtering processing.
The signal impedance matching unit includes: a TLV3544 chip N1, a pull-down resistor R1, a capacitor C1 and a resistor R2;
one end of the pull-down resistor R1 is used as an input end to receive an externally input Vout1 signal (namely, an analog signal output by the infrared detector), one end of the pull-down resistor R1 is connected with the positive input end of the TLV3544 chip N1, and the other end of the pull-down resistor R1 is grounded; one end of the capacitor C1 is connected with an external power supply and a power supply end of the TLV3544 chip N1, and the other end of the capacitor C1 is grounded; the grounding end of the TLV3544 chip N1 is grounded, one end of a resistor R2 is connected with the inverted input end of the TLV3544 chip N1, and the other end of a resistor R2 is connected with the output end of the TLV3544 chip N1; the other end of the resistor R2 is connected as an output terminal to the level matching unit.
A signal level matching unit and a filtering unit using ADA4932-1 chip of Adenono (ADI) company includes: an ADA4932-1 chip N2, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a capacitor C8, a capacitor C12, a capacitor C18 and a capacitor C13;
one end of the resistor R6 is used as an input end to receive an input signal VO1 sent by the signal impedance matching unit, and the other end of the resistor R6 is connected with one end of the capacitor C8, one end of the resistor R7 and the positive input end of the ADA4932-1 chip N2; the other end of the capacitor C8 is connected with the other end of the resistor R7 and a terminal pin 1 of the ADA4932-1 chip N2;
one end of the capacitor C12 is connected with an external power supply and a power supply end of the ADA4932-1 chip N2, so that the power supply is filtered; the other end of the capacitor C12 is grounded;
the ADA4932-1 chip N2 pin 9 is used for receiving VCM signals;
one end of the resistor R9 is used for receiving a VREF signal, and the other end of the resistor R9 is connected with the inverse input end of the ADA4932-1 chip N2, one end of the resistor R10 and one end of the capacitor C18; the other end of the resistor R10 is connected with the other end of the capacitor C18 and an ADA4932-1 chip N2 terminal pin 4; grounding the grounding end of the ADA4932-1 chip N2;
one end of the resistor R8 is connected with the negative output end (pin 11) of the ADA4932-1 chip N2, and the other end of the resistor R8 is connected with one end of the capacitor C13 and serves as a reverse output end;
one end of the resistor R11 is connected to the positive output end (pin 10) of the ADA4932-1 chip N2, and the other end of the resistor R11 is connected to the other end of the capacitor C13 and serves as a positive output end.
The analog-to-digital conversion unit adopting an AD9645 chip of Addeno (ADI) company comprises: an AD9645 chip N3, a resistor R4, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C14, a capacitor C15, a capacitor C16 and a capacitor C17;
the AD9645 chip N3 has 6 AVDD pins, each two AVDD pins are connected with two capacitors connected in parallel, namely a capacitor C5, a capacitor C4, a capacitor C2, a capacitor C3, a capacitor C7 and a capacitor C6; the capacitor C14 and the capacitor C15 are connected in parallel to form a decoupling circuit which is connected with DRVDD and DGND, and the capacitor C16 and the capacitor C17 are connected in parallel to be connected with DRVDD and DGND; the capacitor C9 is connected with the capacitor C10 in parallel and connected with VREF and AGND;
one end of the resistor R4 is connected with an RBIAS port of the AD9645 chip N3, and the other end of the resistor R4 is grounded AGND;
one end of the capacitor C11 is connected to the VCM port of the AD9645 chip N3, and the other end of the capacitor C11 is grounded AGND.
And an FPGA chip XC7A100T-2CSG324I of Xilinx company is adopted to complete the ultra-sampling digital filtering processing unit. The oversampling frequency is set to be 16 times of the output frequency of the detector pixel, and eight data are taken for average processing.
Examples
The impedance matching unit mainly adopts a TLV3544 chip of Texas Instruments (TI) company to carry out impedance matching on an input analog signal, and comprises a TLV3544 chip N1 and peripheral circuits; as shown in fig. 1. The pull-down resistor R1 is connected with the positive input end of the TLV3544 chip N1, the pull-down resistor R1 takes the metal film resistor of 100k omega, the precision is 1%, and the input end signal is more stable; the capacitor C1 is a ceramic dielectric capacitor with the value of 0.1 muf, the precision is 1 percent, and the capacitor C1 is connected with the N1 power supply and the ground end of the TLV3544 chip and is a filter circuit for filtering noise in a 5V power supply; the resistor R2 is a metal film resistor with the value of 100 omega, the precision is 1 percent, and the resistor R2 is connected between the reverse input end and the output end of the TLV3544 chip N1.
The signal level matching unit and the filtering unit are made of ADA4932-1 chips from Adnao (ADI) corporation, including ADA4932-1 chip N2 and peripheral circuits, as shown in fig. 2. The input signal of the VO1 is connected with the positive input end of N2 through R6, and R6 takes the value of 499 omega of metal film resistance with the precision of 1 percent; the VREF signal is connected with the N2 reverse input end through R9; the C12 is connected with the power end of the N2 and the ground, so that the power supply is more stable; r8 is connected with the negative output end of N2, R11 is connected with the positive output end of N2, so that impedance matching is realized; c13 is connected with the positive output end and the negative output end of the N2, and the AC quantity of the differential signal is eliminated through coupling; r7 is connected in parallel with C8 and then connected across the positive input end and the negative output end of N2, and R10 is connected in parallel with C18 and then connected across the negative input end and the positive output end of N2. Wherein R6, R7, R9 and R10 take the values of 499 omega of metal film resistance, the precision is 1%; r8 and R10 take the values of 24.91 omega of metal film resistance, and the precision is 1 percent; the values of C8, C12 and C18 are ceramic dielectric capacitors with the precision of 1 percent, and the value is 0.1 muf; the value of C13 is 47pf ceramic dielectric capacitance with the precision of 1%.
The signal analog-to-digital conversion unit adopts an AD9645 chip of Addeno (ADI) company, and comprises: AD9645 chip N3 and peripheral circuits, as shown in FIG. 3. The AD9645 chip N3 has 6 AVDD pins, each two AVDD pins are connected with two capacitors connected in parallel, the sizes of the capacitors are 0.1 muf and 10 muf respectively, and the capacitors are C5, C4 and C2, C3, C7 and C6 respectively; the capacitor C14 and the capacitor C15 are connected in parallel to form a decoupling circuit which is connected with DRVDD and DGND; the capacitor C16 is connected with the capacitor C17 in parallel and connected with DRVDD and DGND; c9 is connected with a capacitor C10 in parallel, and VREF and AGND are connected; the pull-down resistor R4 is connected with RBIAS and AGND, so that the RBIAS pin is always at low level; capacitor C11 connects VCM and AGND, guarantees that VCM pin signal is more stable. The values of the capacitor C5, the capacitor C2, the capacitor C7, the capacitor C11, the capacitor C15 and the capacitor C17 are 0.1 muf of ceramic dielectric capacitance, and the precision is 1%; the values of the capacitor C3, the capacitor C4, the capacitor C6, the capacitor C14 and the capacitor C16 are 10 muf of ceramic dielectric capacitors, and the precision is 1%; the resistance R4 takes the value of 1k omega of metal film resistance, and the precision is 1%.
Noise analysis under conventional conditions, a mathematical model of white noise describes the noise in the actual signal closely, from which the energy spectral density within the signal band can be expressed as:
in the formula: e.g. of the typermsIs the average noise power; f. ofsIs the sampling frequency; e (f) is the in-band energy spectral density.
The comparative relationship between the sampling frequency and the nyquist frequency is expressed by an Oversampling Ratio (OSR), which is defined as:
in the formula: f. ofmIs the highest frequency of the input signal.
The in-band noise power through the signal input is:
in the formula: n is0The noise power output for oversampling.
As can be seen from equation (3), the in-band noise power can be reduced by increasing the OSR. Oversampling does not affect signal power, so oversampling can improve signal-to-noise ratio by reducing noise power without affecting signal power. Therefore, the invention adopts 16 times of oversampling frequency to perform data sampling so as to suppress the interference of white noise. The hardware is realized by high-speed AD and FPGA control.
Those skilled in the art will appreciate that the details of the invention not described in detail in the specification are within the skill of those skilled in the art.
Claims (6)
1. A low noise sampling circuit for use in an infrared detector, comprising: the system comprises a signal impedance matching unit, a level matching unit, a filtering unit, an analog-to-digital conversion unit and an ultra-sampling digital filtering processing unit;
the signal impedance matching unit is the input end of a signal, the output end of the signal impedance matching unit is connected with the level matching unit, and the level matching unit is connected with the analog-to-digital conversion unit through the filtering unit; the impedance matching unit adopts a TLV3544 chip of Texas instruments; the level matching unit adopts an ADA4932-1 chip of Adenoki; the analog-to-digital conversion unit adopts an AD9645 chip of Addeno company; the ultra-sampling digital filtering unit is realized in an FPGA (field programmable gate array), and the FPGA adopts an A7 series of Xilinx company;
after an analog signal output by the infrared detector passes through the signal impedance matching unit, the signal level matching unit, the filtering unit and the analog-to-digital conversion unit, the FPGA finishes oversampling on the signal and performs digital filtering processing.
2. The low-noise sampling circuit applied to the infrared detector as set forth in claim 1, wherein the signal impedance matching unit comprises: a TLV3544 chip N1, a pull-down resistor R1, a capacitor C1 and a resistor R2;
one end of a pull-down resistor R1 is used as an input end to receive an externally input Vout1 signal, one end of a pull-down resistor R1 is connected with the positive input end of the TLV3544 chip N1, and the other end of the pull-down resistor R1 is grounded; one end of the capacitor C1 is connected with an external power supply and a power supply end of the TLV3544 chip N1, and the other end of the capacitor C1 is grounded; the grounding end of the TLV3544 chip N1 is grounded, one end of a resistor R2 is connected with the inverted input end of the TLV3544 chip N1, and the other end of a resistor R2 is connected with the output end of the TLV3544 chip N1; the other end of the resistor R2 is connected as an output terminal to the level matching unit.
3. The low noise sampling circuit of claim 2, wherein the signal level matching unit and the filtering unit comprise: an ADA4932-1 chip N2, a resistor R6, a resistor R7, a resistor R8, a resistor R9, a resistor R10, a resistor R11, a capacitor C8, a capacitor C12, a capacitor C18 and a capacitor C13;
one end of the resistor R6 is used as an input end to receive an input signal VO1 sent by the signal impedance matching unit, and the other end of the resistor R6 is connected with one end of the capacitor C8, one end of the resistor R7 and the positive input end of the ADA4932-1 chip N2; the other end of the capacitor C8 is connected with the other end of the resistor R7 and a terminal pin 1 of the ADA4932-1 chip N2;
one end of the capacitor C12 is connected with an external power supply and a power supply end of the ADA4932-1 chip N2, and the other end of the capacitor C12 is grounded;
the ADA4932-1 chip N2 pin 9 is used for receiving VCM signals;
one end of the resistor R9 is used for receiving a VREF signal, and the other end of the resistor R9 is connected with the inverse input end of the ADA4932-1 chip N2, one end of the resistor R10 and one end of the capacitor C18; the other end of the resistor R10 is connected with the other end of the capacitor C18 and an ADA4932-1 chip N2 terminal pin 4; grounding the grounding end of the ADA4932-1 chip N2;
one end of the resistor R8 is connected with the negative output end of the ADA4932-1 chip N2, and the other end of the resistor R8 is connected with one end of the capacitor C13 and serves as a reverse output end;
one end of the resistor R11 is connected with the positive output end of the ADA4932-1 chip N2, and the other end of the resistor R11 is connected with the other end of the capacitor C13 and serves as a positive output end.
4. The low-noise sampling circuit applied to the infrared detector is characterized in that: the analog-to-digital conversion unit includes: an AD9645 chip N3, a resistor R4, a capacitor C2, a capacitor C3, a capacitor C4, a capacitor C5, a capacitor C6, a capacitor C7, a capacitor C9, a capacitor C10, a capacitor C11, a capacitor C14, a capacitor C15, a capacitor C16 and a capacitor C17;
the AD9645 chip N3 has 6 AVDD pins, each two AVDD pins are connected with two capacitors connected in parallel, namely a capacitor C5, a capacitor C4, a capacitor C2, a capacitor C3, a capacitor C7 and a capacitor C6; the capacitor C14 and the capacitor C15 are connected in parallel to form a decoupling circuit which is connected with DRVDD and DGND, and the capacitor C16 and the capacitor C17 are connected in parallel to be connected with DRVDD and DGND; the capacitor C9 is connected with the capacitor C10 in parallel and connected with VREF and AGND;
one end of the resistor R4 is connected with an RBIAS port of the AD9645 chip N3, and the other end of the resistor R4 is grounded AGND;
one end of the capacitor C11 is connected to the VCM port of the AD9645 chip N3, and the other end of the capacitor C11 is grounded AGND.
5. The low-noise sampling circuit applied to the infrared detector is characterized in that: and an FPGA chip XC7A100T-2CSG324I of Xilinx company is adopted to complete the ultra-sampling digital filtering processing unit.
6. The low-noise sampling circuit applied to the infrared detector is characterized in that: the oversampling frequency is set to be 16 times of the output frequency of the detector pixel, and eight data are taken for average processing.
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| CN110062306A (en) * | 2019-04-24 | 2019-07-26 | 深圳市中芯微电子有限公司 | A kind of bluetooth headset and audio-frequency amplifier with booster circuit |
| CN110932612A (en) * | 2019-11-07 | 2020-03-27 | 上海航天控制技术研究所 | Differential high-performance brushless motor driver and driving method |
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Application publication date: 20210622 |