CN112993005B - 具有平台结构的半导体元件及其制作方法 - Google Patents

具有平台结构的半导体元件及其制作方法 Download PDF

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CN112993005B
CN112993005B CN201911211806.4A CN201911211806A CN112993005B CN 112993005 B CN112993005 B CN 112993005B CN 201911211806 A CN201911211806 A CN 201911211806A CN 112993005 B CN112993005 B CN 112993005B
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lattice
mesa
semiconductor device
semiconductor
layer
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CN112993005A (zh
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张峻铭
廖文荣
侯俊良
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United Microelectronics Corp
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Abstract

本发明公开一种具有平台结构的半导体元件及其制作方法，其中该平台结构包含一基底，一平台凸出于基底，平台包含一个坡面和一上表面，前述坡面环绕上表面，其中一晶格破坏区设置于坡面的内侧，平台可选择性包含一绝缘层覆盖于晶格破坏区，其中绝缘层为氧化层或氮化层。

Description

具有平台结构的半导体元件及其制作方法
技术领域
本发明涉及一种平台(mesa)结构的制作方法和及其结构，特别是涉及一种在平台的坡面设置有晶格破坏区的平台结构的制作方法和及其结构。
背景技术
III-V族半导体化合物由于其半导体特性而可应用于形成许多种类的集成电路装置，例如高功率场效晶体管、高频晶体管或高电子迁移率晶体管(high electron mobilitytransistor，HEMT)。在高电子迁移率晶体管中，两种不同能隙(band gap)的半导体材料是结合而于结(junction)形成异质结(heterojunction)而为载流子提供通道。近年来，氮化镓系列的材料由于拥有较宽能隙与饱和速率高的特点而适合应用于高功率与高频率产品。氮化镓系列的高电子迁移率晶体管由材料本身的压电效应产生二维电子气(two-dimensional electron gas,2DEG)，相较于传统晶体管，高电子迁移率晶体管的电子速度及密度均较高，故可用以增加切换速度。
然而在形成电子迁移率晶体管的栅极电极时，会发生栅极电极接触到二维电子气，造成短路的问题。
发明内容
有鉴于此，本发明提供一种平台结构，其利用晶格破坏区确保栅极电极和二维电子气之间绝缘。
根据本发明的一优选实施例，一种平台结构包含一基底，一平台凸出于基底，平台包含一个坡面和一上表面，前述坡面环绕上表面，其中一晶格破坏区设置于坡面的内侧。此外，平台可选择性包含一绝缘层覆盖于晶格破坏区，其中绝缘层为氧化物或氮化物。
根据本发明的一优选实施例，一种平台结构的制作方法包含：首先提供一基底和一半导体堆叠层覆盖基底，接着蚀刻半导体堆叠层以形成多个沟槽，其中两个相邻的前述沟槽之间的半导体堆叠层构成一平台，最后以离子轰击各个沟槽以在各个沟槽的二个侧壁和一底部形成一晶格破坏区，之后可选择性地形成一绝缘层覆盖晶格破坏区，其中绝缘层为氧化层或氮化层。
为让本发明的上述目的、特征及优点能更明显易懂，下文特举优选实施方式，并配合所附的附图，作详细说明如下。然而如下的优选实施方式与附图仅供参考与说明用，并非用来对本发明加以限制者。
附图说明
图1至图10为本发明的一优选实施例所绘示的一种具有平台结构的半导体元件的制作方法的示意图，其中：
图1是提供基底的步骤；
图2接续图1的步骤；
图3是图2中其中的一个平台的立体示意图；
图4接续图2的步骤；
图5为图4中的平台和晶格破坏区的立体示意图；
图6接续图4的步骤；
图7为图6中的平台、晶格破坏区和绝缘层的立体示意图；
图8接续图6的步骤；
图9接续图8的步骤；以及
图10是形成栅极电极的步骤的示意图；
图11为本发明的另一优选实施例所绘示的平台的示意图。
主要元件符号说明
10 基底 12 半导体堆叠层
14 半导体基板 16 缓冲层
18 氮化镓层 20 氮化铝镓层
22 二维电子气 24 硬掩模
26 光致抗蚀剂 28 沟槽
28a 侧壁 28b 底面
30 平台 30a 坡面
30b 上表面 30c 底面
32 晶格破坏区 34 绝缘层
36 栅极电极 38 源极电极
40 漏极电极 42 高电子移动率晶体管
44 保护层 46 孔洞
100 平台结构 D1 第一方向
D2 第二方向 D3 第三方向
具体实施方式
图1至图10为根据本发明的一优选实施例所绘示的一种具有平台结构的半导体元件的制作方法。
如图1所示，首先提供一基底10，一半导体堆叠层12覆盖在基底10上，基底10可以包含半导体基板14和缓冲层16。缓冲层16覆盖在半导体基板14上，半导体基板14可以是硅基底、蓝宝石基底或硅覆绝缘基底，半导体堆叠层12覆盖在缓冲层16上，半导体堆叠层12至少包含二种相异的III-V族半导体层，III-V族半导体层可包含氮化铝、氮化铝镓或氮化镓，举例而言，III-V族半导体层包含一氮化镓层18和一氮化铝镓层20，其中氮化铝镓层20设置于氮化镓层18上，在氮化镓层18和氮化铝镓层20之间会形成二维电子气(2DEG)22。此外缓冲层16可以为氮化镓。
如图2所示，在图2左下方定义坐标方位，分别为第一方向D1、第二方向D2和第三方向D3，形成一硬掩模24覆盖半导体堆叠层12，之后再形成一光致抗蚀剂26覆盖硬掩模，然后图案化光致抗蚀剂26，接着以光致抗蚀剂26为掩模图案化硬掩模24，之后再以光致抗蚀剂26和硬掩模24为掩模，蚀刻半导体堆叠层12以形成多个沟槽28，其中两个相邻的沟槽28之间的半导体堆叠层12构成一平台30。沟槽28的深度至少要比二维电子气22的深度大，也就是沟槽28会把二维电子气22截断，较佳地沟槽28的深度大于氮化镓层18底部的深度，也就是说缓冲层16会作为沟槽28的底部。
图3所绘示的是图2中其中之一个平台的立体示意图，为了清楚显示平台，图3中省略了图2中的硬掩模和光致抗蚀剂。图3沿AA’切线方向的侧视图即是在图2中间位置的平台。如图3所示，平台30为一立体梯形，立体梯形包含有一个坡面30a、一个上表面30b和一个底面30c，上表面30b和底面30c平行并且上表面30b的面积小于底面30c的面积，坡面30a围绕上表面30b和底面30c，此外二维电子气22曝露在坡面30a上。然而，本发明的平台也可以是截头圆锥形，请参阅图11，图11中具有相同功能的元件将采用和图3相同的元件符号，在图11中平台30为截头圆锥形，平台30同样包含一个坡面30a、一个上表面30b和一个底面30c，上表面30b和底面30c平行并且上表面30b的面积小于底面30c的面积。在后续制作工艺将以图3中的平台30接续说明。
如图4所示，以光致抗蚀剂26和硬掩模24为掩模以离子轰击各个沟槽28以在各个沟槽28的二个侧壁28a和一底部28b形成一晶格破坏区32。详细来说以离子轰击时，是利用氮、氧、氢、氟、氦、氩、镁、锌、磷、氦、铁、氪、氙-131、硼或砷轰击沟槽28的侧壁28a和底部28b，使得沟槽28的侧壁28a和底部28b的内侧的晶格排列被破坏而形成晶格破坏区32。晶格破坏区32的厚度小于50纳米，也就是说离子轰击的深度小于50纳米。值得注意的是：由于沟槽28的侧壁28a和底部28b的晶格结构被破坏，也就是说氮化镓层18和氮化铝镓层20的纤锌矿态(wurtzite-type)晶格被损坏，被损坏的位置就不能形成二维电子气22。换而言之，在晶格破坏区32中没有二维电子气22。至此本发明的平台结构100业已完成，平台结构100包含基底10、平台30和晶格破坏区32。此外，光致抗蚀剂26在以离子轰击时可能被消耗完，之后在离子轰击结束后可进行清洗制作工艺完全将光致抗蚀剂26去除。
图5为图4中的平台和晶格破坏区的立体示意图，为了清楚显示晶格破坏区，图5中省略了图4中的硬掩模和光致抗蚀剂。图5沿BB’切线方向的侧视图即是在图4中间的位置的平台和晶格破坏区，请同时参阅图3、图4和图5，晶格破坏区32位于坡面30a的内侧，坡面30a也就是沟槽28的侧壁28a，值得注意的是在晶格破坏区32形成之后，坡面30a的表面都没有二维电子气22。
如图6所示，在形成晶格破坏区32后，视产品需求可选择性在各个沟槽28的侧壁28a和底部28b形成一绝缘层34，绝缘层34的厚度小于5纳米。绝缘层34形成的方式可以为进行一氧化制作工艺以在各个沟槽28的侧壁28a和底部28b形成一氧化层作为绝缘层34，或是进行一氮化制作工艺以在各个沟槽28的侧壁28a和底部28b形成一氮化层作为绝缘层34。
图7为图6中的平台、晶格破坏区和绝缘层的立体示意图，为了清楚显示绝缘层和晶格破坏区，图7中省略图6中的硬掩模。图7沿CC’切线方向的侧视图即是在图6中间位置的平台，如图7所示，绝缘层34位于坡面30a上并且覆盖晶格破坏区32。
在平台结构100完成之后，平台结构100可用于形成各种半导体元件，例如高电子移动率晶体管，如图8所示，平台结构100完成后移除硬掩模24，然后形成一栅极电极36、一源极电极38和一漏极电极40于平台30上，其中平台结构100、栅极电极36、源极电极38和漏极电极40共同构成一高电子移动率晶体管42。源极电极38和漏极电极40埋入于氮化铝镓层20中，而栅极电极36位于氮化铝镓层20的表面上，源极电极38和漏极电极40分别位于栅极电极36的两侧。
如图9所示，形成一保护层44覆盖沟槽28、平台结构100、栅极电极36、源极电极38和漏极电极40。之后再在保护层44上形成数个孔洞46以曝露栅极电极36、源极电极38和漏极电极40。
图10绘示的是形成源极电极38和漏极电极40完成之后，形成栅极电极36的步骤的示意图，如图10所示，栅极电极36形成时除了会形成在平台30的上表面30b上，也会顺应地覆盖坡面30a(请参阅图7获得更清楚的坡面30a和上表面30b位置)，若是没有本发明的晶格破坏区32或绝缘层34，栅极电极36就会接触到二维电子气22(请参阅图3获得二维电子气的位置)，之后移除坡面30a上的栅极电极36时，若没有移除干净将会造成元件问题。而本发明特别形成晶格破坏区32，使得栅极电极36接触的坡面30a内没有二维电子气22，再选择性地加上绝缘层34，可以更进一步隔绝栅极电极36和平台30内的二维电子气22，如此可以确保栅极电极36和二维电子气22之间完全绝缘。
图4为根据本发明的一优选实施例所绘示的一种平台结构，图5为图4中的平台和晶格破坏区的立体示意图，其中图5沿BB’切线方向的侧示图即是在图4中间位置的平台。请同时参阅图4和图5，一种平台结构100包含一基底10，数个平台30凸出于基底10，每个平台30的构造都相同，以下说明单个平台30的构造，平台30为一立体梯形或一截头圆锥形(如图11所示)或截头椭圆锥形(图未示)，平台30包含有一个坡面30a、一个上表面30b和一个底面30c，上表面30b和底面30c平行并且上表面30b的面积小于底面30c的面积，坡面30a围绕上表面30b和底面30c，一晶格破坏区32设置于坡面30a的内侧。平台30包含半导体堆叠层12，半导体堆叠层12较佳至少包含二种相异的III-V族半导体层，例如一氮化镓层18和一氮化铝镓层20，在氮化镓层18和氮化铝镓层20之间会形成二维电子气22。晶格破坏区32为部分的氮化镓层18和部分的氮化铝镓层20并且晶格破坏区32中包含氮、氧、氢、氟、氦、氩、镁、锌、磷、氦、铁、氪、氙-131、硼或砷。值得注意的是：晶格破坏区32中的氮化镓层18和氮化铝镓层20的纤锌矿态晶格被损坏，因此在晶格破坏区32中没有二维电子气22。此外晶格破坏区22的厚度小于50纳米。
根据本发明的另一优选实施例，如图6和图7所示，平台结构100可以另包含一绝缘层34设置在晶格破坏区32外围，绝缘层34可以为氧化层或氮化层，例如氮化硅、氧化硅、氧化铝(Al2O3)或氮化铝等。
根据本发明的另一优选实施例，请参阅图8，平台结构100上可以另外设置一栅极电极36、一源极电极38和一漏极电极40，其中栅极电极36位于氮化铝镓层20的上表面，源极电极38和漏极电极40埋入半导体堆叠层12，此外，源极电极38和漏极电极40分别位于栅极电极36两侧。平台结构100、栅极电极36、源极电极38和漏极电极40共同构成一高电子移动率晶体管42。
以上所述仅为本发明的优选实施例，凡依本发明权利要求所做的均等变化与修饰，都应属本发明的涵盖范围。

Claims (20)

1.一种具有平台结构的半导体元件，其特征在于，包含：
平台结构，包含：
基底；
平台，凸出于该基底，该平台包含一个坡面和一上表面，该坡面环绕该上表面，其中该平台包含两种相异的III-V族半导体层；以及
晶格破坏区，设置于该坡面的内侧并且接触该两种相异的III-V族半导体层之间的界面。
2.如权利要求1所述的具有平台结构的半导体元件，其中该晶格破坏区包含氮、氧、氢、氟、氦、氩、镁、锌、磷、铁、氪、氙-131、硼或砷。
3.如权利要求1所述的具有平台结构的半导体元件，其中该晶格破坏区内没有二维电子气。
4.如权利要求1所述的具有平台结构的半导体元件，另包含绝缘层，设置在该坡面上，其中该绝缘层包含氧化层或氮化层。
5.如权利要求4所述的具有平台结构的半导体元件，其中该绝缘层的厚度小于5纳米。
6.如权利要求1所述的具有平台结构的半导体元件，其中该晶格破坏区的厚度小于50纳米。
7.如权利要求1所述的具有平台结构的半导体元件，另包含：多个该平台，凸出于该基底，相邻的各该平台之间设置有沟槽。
8.如权利要求7所述的具有平台结构的半导体元件，其中该沟槽的侧壁为相邻的两个该多个平台各自的坡面，该沟槽的底部为该基底的上表面。
9.权利要求8所述的具有平台结构的半导体元件，其中该晶格破坏区设置于该沟槽的底部。
10.权利要求1所述的具有平台结构的半导体元件，其中该平台包含III-V族半导体堆叠层。
11.权利要求10所述的具有平台结构的半导体元件，另包含：
栅极电极，设置于该平台上；以及
源极电极和漏极电极，设置于该平台上并且分别位于该栅极电极两侧，其中该平台结构、该栅极电极、该源极电极和该漏极电极共同构成高电子移动率晶体管。
12.一种具有平台结构的半导体元件的制作方法，包含：
提供基底和半导体堆叠层覆盖该基底，其中该半导体堆叠层包含两种相异的III-V族半导体层；
蚀刻该半导体堆叠层以形成多个沟槽，其中两个相邻的该多个沟槽之间的该半导体堆叠层构成平台；以及
以离子轰击该多个沟槽以在各该沟槽的二个侧壁和一底部形成晶格破坏区，该晶格破坏区接触该两种相异的III-V族半导体层之间的界面；以及
在轰击该多个沟槽之后，形成源极电极和漏极电极于该平台上。
13.如权利要求12所述的具有平台结构的半导体元件的制作方法，另包含：
在形成该晶格破坏区后，在各该沟槽表面形成一绝缘层。
14.如权利要求13所述的具有平台结构的半导体元件的制作方法，其中该绝缘层的厚度小于5纳米。
15.如权利要求13所述的具有平台结构的半导体元件的制作方法，其中该绝缘层是利用氧化制作工艺或氮化制作工艺形成。
16.如权利要求12所述的具有平台结构的半导体元件的制作方法，另包含：
在形成该晶格破坏区后，形成栅极电极于该平台上；以及
形成保护层覆盖该多个沟槽、该平台、该栅极电极、该源极电极和该漏极电极。
17.如权利要求12所述的具有平台结构的半导体元件的制作方法，其中以离子轰击时，利用氮、氧、氢、氟、氦、氩、镁、锌、磷、铁、氪、氙-131、硼或砷轰击该多个侧壁和该底部。
18.如权利要求12所述的具有平台结构的半导体元件的制作方法，其中该平台包含一III-V族半导体堆叠层。
19.如权利要求12所述的具有平台结构的半导体元件的制作方法，其中该晶格破坏区中没有二维电子气。
20.如权利要求12所述的具有平台结构的半导体元件的制作方法，其中该晶格破坏区厚度小于50纳米。
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